Toshiba TXZ+ Series User manual

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
1 / 88
© 2020-2021
Toshiba Electronic Devices & Storage Corporation
2021-06
32-bit RISC microcontroller
TXZ+ Family
TMPM4G Group(1)
Reference Manual
Clock Control and Operation Mode
(CG-M4G(1)-C)
Revision 1.1

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
2 / 88
Contents
Preface ................................................................................................................................................................. 7
Related document.....................................................................................................................................................7
Conventions ..............................................................................................................................................................8
Terms and Abbreviations ........................................................................................................................................10
1. Clock Control and Operation Mode ............................................................................................................ 11
Outlines ............................................................................................................................................................11
Clock control ....................................................................................................................................................11
Clock type...................................................................................................................................................................11
The initial value by a reset action ...............................................................................................................................12
Clock System diagram................................................................................................................................................13
Warming up function...................................................................................................................................................14
The warming up timer for a high speed oscillation.........................................................................................................14
The warming up timer for a low speed oscillation ..........................................................................................................15
The directions for a warming up timer ...........................................................................................................................15
Clock multiplying circuit (PLL) for fsys ........................................................................................................................16
PLL setup after reset release ........................................................................................................................................16
The formula and the example of a setting of a PLL multiplication value ........................................................................16
Change of the PLL multiplication value under operation................................................................................................17
PLL operation start / stop / switching procedure............................................................................................................18
System clock ..............................................................................................................................................................19
The setting method of a system clock ...........................................................................................................................20
Low speed clock.........................................................................................................................................................22
ELOSC Setting (No Operation of External Low Speed Oscillator → Operation) ............................................................22
ELCLKIN Setting (No Operation of External Low Speed Oscillator → Operation) .........................................................22
Clock supply setting function ......................................................................................................................................23
Prescaler clock ...........................................................................................................................................................23
Operation mode ...............................................................................................................................................24
Details of an Operation mode.....................................................................................................................................24
The feature in each mode .............................................................................................................................................24
Transition to and Return from Low Power Consumption mode......................................................................................25
Selection of a Low Power Consumption mode ..............................................................................................................25
The peripheral function state in a Low Power Consumption mode ................................................................................26
Switch to and return from a Low Power Consumption mode......................................................................................28
IDLE mode transition flow .............................................................................................................................................28
STOP1 mode transition flow..........................................................................................................................................29
STOP2 mode transition flow..........................................................................................................................................30
Return from a Low Power Consumption mode...........................................................................................................31
The release source of a Low Power Consumption mode ..............................................................................................31
Warming up at the release of Low Power Consumption mode ......................................................................................32
Restart operation from STOP2 mode ............................................................................................................................33
Clock operation by mode transition ............................................................................................................................34
NORMAL →IDLE →NORMAL Operation mode transition ...........................................................................................34
NORMAL →STOP1 →NORMAL Operation mode transition .......................................................................................34

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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NORMAL →STOP2 →RESET →NORMAL Operation mode transition......................................................................35
Explanation of a register ..................................................................................................................................36
Register list.................................................................................................................................................................36
Detail of Register........................................................................................................................................................37
[CGPROTECT] (CG write protection register) ...............................................................................................................37
[CGOSCCR] (Oscillation control register)......................................................................................................................37
[CGSYSCR] (System clock control register)..................................................................................................................38
[CGSTBYCR] (Standby control register) .......................................................................................................................39
[CGPLL0SEL] (PLL selection register for fsys)..............................................................................................................39
[CGWUPHCR] (High speed oscillation warming up register).........................................................................................40
[CGWUPLCR] (Low speed oscillation warming up register) ..........................................................................................40
[CGFSYSMENC] (Middle speed clock supply and stop register C for fsysm)................................................................41
[CGFSYSMENA] (Middle speed clock supply and stop register A for fsysm) ................................................................42
[CGFSYSMENB] (Middle speed clock supply and stop register B for fsysm) ..............................................................44
[CGFSYSENA] (High speed clock supply and stop register A for fsysh) .....................................................................46
[CGFCEN] (Clock supply and stop register for fc) .......................................................................................................47
[CGSPCLKEN] (Clock supply for ADC and Debug circuit Register) ............................................................................47
[CGEXTEND2] (Function extension register 2) ...........................................................................................................48
[RLMLOSCCR] (Low speed oscillation and Internal High speed oscillation 2 clock control register) ...........................48
[RLMSHTDNOP](Power supply cut off control register) ..............................................................................................49
[RLMPROTECT](RLM write protection register)..........................................................................................................49
Information according to product .....................................................................................................................50
[CGFSYSENA] ...........................................................................................................................................................50
[CGFSYSMENA] ........................................................................................................................................................51
[CGFSYSENB] ...........................................................................................................................................................52
[CGFSYSENC] ...........................................................................................................................................................53
[CGFCEN] ..................................................................................................................................................................54
2. Memory Map ............................................................................................................................................... 55
Outline..............................................................................................................................................................55
TMPM4GxF20 ............................................................................................................................................................56
TMPM4GxF15 ............................................................................................................................................................57
TMPM4GxF10 ............................................................................................................................................................58
TMPM4GxFD..............................................................................................................................................................59
Bus Matrix ........................................................................................................................................................60
Structure.....................................................................................................................................................................61
Single chip mode...........................................................................................................................................................61
Single boot mode ..........................................................................................................................................................62
Connection table.........................................................................................................................................................63
Code area / SRAM area / SMIF area / External bus area..............................................................................................63
Peripheral Area .............................................................................................................................................................71
RAM Access...............................................................................................................................................................72
Control Registers ..........................................................................................................................................................72
3. Reset and Power Control............................................................................................................................ 74
Outline..............................................................................................................................................................74
Function and Operation ...................................................................................................................................74

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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Cold reset ...................................................................................................................................................................74
Reset by a Power On Reset Circuit (without using a RESET_N pin) .............................................................................75
Reset by a RESET_N pin ..............................................................................................................................................76
Reset extension by LVD ................................................................................................................................................78
Warm reset.................................................................................................................................................................79
Warm reset by REST_N pin ..........................................................................................................................................79
Warm reset by internal reset .........................................................................................................................................79
Reset by STOP2 mode release..................................................................................................................................80
Starting in reset and single boot mode .......................................................................................................................80
Start-up by RESET_N Pin Signal ..................................................................................................................................80
Start up by Power On Reset (Not Using RESET_N Pin Signal).....................................................................................81
Starting in the single boot mode when power supply is stable.......................................................................................82
Power On Reset Circuit ..............................................................................................................................................83
Operation at the time of a power on ..............................................................................................................................83
Operation at the time of turn off.....................................................................................................................................83
Precautions when turning off the power .....................................................................................................................84
About turn on power supply after turn off....................................................................................................................85
After reset release ......................................................................................................................................................85
A reset factor and the reset range .................................................................................................................................86
4. Revision history........................................................................................................................................... 87
RESTRICTIONS ON PRODUCT USE............................................................................................................... 88

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TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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List of Figure
Figure 1.1 Clock system diagram............................................................................................................. 13
Figure 1.2 Change state........................................................................................................................... 28
Figure 1.3 STOP2 mode restart operation flow ....................................................................................... 33
Figure 1.4 NORMAL → STOP1 → NORMAL Operation mode transition............................................... 34
Figure 1.5 NORMAL → STOP2 → RESET → NORMAL Operation mode transition ............................. 35
Figure 2.1 TMPM4GxF20......................................................................................................................... 56
Figure 2.2 TMPM4GxF15......................................................................................................................... 57
Figure 2.3 TMPM4GxF10......................................................................................................................... 58
Figure 2.4 TMPM4GxFD .......................................................................................................................... 59
Figure 2.5 Single chip mode .................................................................................................................... 61
Figure 2.6 Single boot mode.................................................................................................................... 62
Figure 3.1 The reset operation by a Power On Reset Circuit.................................................................. 75
Figure 3.2 Reset operation by a RESET_N pin (1).................................................................................. 76
Figure 3.3 Reset operation by a RESET_N pin (2).................................................................................. 77
Figure 3.4 The reset operation by LVD reset........................................................................................... 78
Figure 3.5 Warm reset Operation............................................................................................................. 79
Figure 3.6 Starting in power supply is on and single boot mode............................................................. 80
Figure 3.7 Starting single boot mode without using reset........................................................................ 81
Figure 3.8 Starting in the single boot mode when power supply is stable............................................... 82
Figure 3.9 Power On Reset Circuit .......................................................................................................... 83
Figure 3.10 Falling gradient when turning off the power ......................................................................... 84

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TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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List of Tables
Table 1.1 Details of a [CGPLL0SEL] <PLL0SET [23:0]>setup................................................................ 16
Table 1.2 PLL correction (example)......................................................................................................... 17
Table 1.3 PLL0SET setting value (example) ........................................................................................... 17
Table 1.4 Clock domains of CPU and peripherals................................................................................... 19
Table 1.5 Time interval for changing System clock ................................................................................. 19
Table 1.6 Example of operating frequency .............................................................................................. 20
Table 1.7 Operating frequency examples of High speed and Middle speed system clocks................... 20
Table 1.8 Time interval for changing prescaler clocks ............................................................................ 23
Table 1.9 Low Power Consumption mode selection................................................................................ 25
Table 1.10 Block operation status in each Low Power Consumption mode ........................................... 26
Table 1.11 Release source list................................................................................................................. 31
Table 1.12 Warming up............................................................................................................................ 32
Table 1.13 [CGFSYSENA] register corresponding to each product........................................................ 50
Table 1.14 [CGFSYSMENA] register corresponding to each product..................................................... 51
Table 1.15 [CGFSYSMENB] register corresponding to each product..................................................... 52
Table 1.16 [CGFSYSMENC] register corresponding to each product .................................................... 53
Table 1.17 [CGFCEN] register corresponding to each product............................................................... 54
Table 2.1 TMPM4GxF20 Single chip mode............................................................................................. 63
Table 2.2 TMPM4GxF20 Single boot mode............................................................................................. 64
Table 2.3 TMPM4GxF15 Single chip mode............................................................................................. 65
Table 2.4 TMPM4GxF15 Single boot mode............................................................................................. 66
Table 2.5 TMPM4GxF10 Single chip mode............................................................................................. 67
Table 2.6 TMPM4GxF10 Single boot mode............................................................................................. 68
Table 2.7 TMPM4GxFD Single chip mode .............................................................................................. 69
Table 2.8 TMPM4GxFD Single boot mode.............................................................................................. 70
Table 2.9 Peripheral Area ........................................................................................................................ 71
Table 2.10 The number of clocks to access each RAM .......................................................................... 72
Table 3.1 A reset factor and the range initialized .................................................................................... 86
Table 4.1 Revision history........................................................................................................................ 87

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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Preface
Related document
Document name
Arm®Documentation of Cortex®-M4
Exception
Input/Output Ports
Voltage Detection Circuit
Selective Clock Watch Dog Timer
Flash Memory
Datasheet of Products (Electrical Characteristics)

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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Conventions
●Numeric formats follow the rules as shown below:
Hexadecimal: 0xABC
Decimal: 123 or 0d123 - Only when it needs to be explicitly shown that they are decimal numbers.
Binary: 0b111 - It is possible to omit the “0b” when the number of bit can be distinctly understood from a
sentence.
●“_N” is added to the end of signal names to indicate low active signals.
●It is called “assert” that a signal moves to its active level, “deassert” to its inactive level.
●When two or more signal names are referred, they are described like as [m: n].
Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.
●The characters surrounded by [ ] defines the register.
Example: [ABCD]
●“n” substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], [XYZ3] [XYZn]
●"x" substitutes suffix number or character of units and channels in the Register List.
In case of unit, “x” means A, B, and C …
Example: [ADACR0], [ADBCR0], [ADCCR0] [ADxCR0]
In case of channel, “x” means 0, 1, and 2…
Example: [T32A0RUNA], [T32A1RUNA], [T32A2RUNA] [T32AxRUNA]
●The bit range of a register is written like as [m: n].
Example: Bit[3: 0] expresses the range of bit 3 to 0.
●The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD]<EFG> = 0x01 (hexadecimal), [XYZn]<VW> = 1 (binary)
●Word and Byte represent the following bit length.
Byte: 8 bits
Half word: 16 bits
Word: 32 bits
Double word: 64 bits
●Properties of each bit in a register are expressed as follows:
R: Read only
W: Write only
R/W: Read and Write are possible
●Unless otherwise specified, register access supports only word access.
●The register defined as reserved must not be rewritten. Moreover, do not use the read value.
●The value read from the bit having default value of "-" is unknown.
●When a register containing both of writable bits and read-only bits is written, read-only bits should be written
with their default value, In the cases that default is “-“, follow the definition of each register.
●Reserved bits of the Write-only register should be written with their default value. In the cases that default is
“-”, follow the definition of each register.
●Do not use read-modified-write processing to the register of a definition which is different by writing and
read out.

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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All other company names, product names, and service names mentioned herein may be trademarks of their
respective companies.
***********************************************************************************************************************
Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
***********************************************************************************************************************

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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Terms and Abbreviations
Some of abbreviations used in this document are as follows:
ADC Analog to Digital Converter
A-PMD Advanced Programmable Motor Control Circuit
CG Clock control and Generations
CEC Consumer Electronics Control
DAC Digital to Analog Converter
DNF Digital Noise Filter
EBIF External Bus Interface
EI2C I2C Interface Version A
ELOSC External Low speed Oscillator
EHOSC External High speed Oscillator
FIR Finite Impulse Response
fsys frequency of SYSTEM Clock
IHOSC Internal High Speed Oscillator
INT Interrupt
ISD Interval Sensing Detector
I2C Inter-Integrated Circuit
I2S Inter-IC Sound
LTTMR Long Term Timer
LVD Voltage Detection Circuit
MDMA Multi-function Direct Memory Access
NMI Non-Maskable Interrupt
NBDIF Non Break Debug Interface
OFD Oscillation Frequency Detector
POR Power On Reset Circuit
PORF Power On Reset Circuit for FLASH and debug
RMC Remote control Signal preprocessor
RLM Reset LOSC<Low power> Manager
RTC Real Time Clock
SIWDT Clock Selective Watchdog Timer
SMIF Serial Memory Interface
TRGSEL Trigger Selection Circuit
TSPI Serial Peripheral Interface
TSSI Serial Synchronous Interface
T32A 32-bit Timer Event Counter
UART Universal Asynchronous Receiver Transmitter

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TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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1. Clock Control and Operation Mode
Outlines
The clock/mode control block can select a clock gear and prescaler clock, and set the warming-up of oscillator and
so on. Furthermore, it has Normal mode and a low power consumption mode in order to reduce power
consumption using mode transition.
Functions related to a clock are as follows.
●System clock control
●Prescaler clock control
Clock control
Clock type
This section shows a list of clocks:
EHCLKIN : The high speed clock input from the external
fosc : A clock generated in the internal oscillation circuit or input from the X1 and X2 pins after
being selected by [CGOSCCR]<OSCSEL>.
fPLL : A clock multiplied with PLL0
fc : A clock selected by [CGPLL0SEL]<PLL0SEL> (High speed clock)
ELCLKIN : The low speed clock input from the external
fs : A clock output from an external low speed oscillator
fsysh : A high speed system clock selected by [CGSYSCR]<GEAR[2:0] >
fsysm : A middle speed system clock selected by [CGSYSCR]<GEAR[2:0] ><MCKSEL[1:0] >
ΦT0h : A high speed clock selected by [CGSYSCR]<PRCK[3:0]> (High speed prescaler clock)
ΦT0m : A middle speed clock selected by [CGSYSCR]<PRCK[3:0]> <MCKSEL[1:0] > (Middle speed
prescaler clock)
fIHOSC1 : A clock generated with the internal high speed oscillator 1
fIHOSC2 : A clock generated with the internal high speed oscillator 2
ADCLK : A conversion clock for AD converter
TRCLKIN : A clock for tracing facilities of a debugging circuit (TRACE or SWV)
Note:The high speed system clock and the middle speed system clock are collectively called System clock
(fsys). And the high speed prescaler clock and the middle speed prescaler clock are collectively called
Prescaler clock (ΦT0).

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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The initial value by a reset action
A clock setup is initialized to the following states by a reset action.
External high speed oscillator : Stop
Internal high speed oscillator 1 : Oscillation
Internal high speed oscillator 2 : Stop (Note)
External low speed oscillator : Stop
PLL (multiplying circuit) : Stop
Gear clock : fc (no frequency dividing)
Note: The state after the initialization done by the reset from the pin depends on [RLMLOSCCR]<POSCEN>
setting.

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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Clock System diagram
The figure below shows a clock system diagram.
Internal High
speed ocillator1
Ex terna l
High s peed
oscillator1
X2
X1
[CGOSCCR]<EOSCEN[1:0]>
After Res et: Stop
fosc
[CGOSCCR]<IHOSC1EN>
After Res et: Oscillation
f
IH O SC1
[CGWUPHCR]
<WUCLK>
High s peed
Warming up timer
[CGWUPHCR]<WUON>
[CGWUPHCR]<WUPT[15:4]>
Internal High
speed oscil lator2
[RLMLOSCCR]<POSCEN>
After Res et: Stop(Note)
OFD
[CGOSCCR]
<OSCSEL>
fpll
[CGPLL0SEL]
<PLL0SEL>
ADC
Ex terna l
Low speed
oscillator
XT2
XT1
Low speed
Warming up timer
[CGWUPLCR]<WULO N>
[CGWUPLCR]<WUPTL[18:4]>
fs
[Peripheral function clock inputs]
RTC, ISD, TR GS EL
fc
[Peripheral function prescaler inputs]
（High s peed pr es caler clock）
TSPI0 to 5
[R LM L O S CCR ]
<XTE N>
After Res et: Stop
[CGSYSCR]
<PRCK[3:0]>
[CGSYSCR]
<GEAR[2:0]>
[CGSPCLKEN]
<TR C KE N>
1/64
SysTick
TRCK
1/64 1/1281/161/81/41/2 1/32 1/256 1/5 12
fc
1/2
1/4 1/8
1/16
fosc
fsysh
Source clock control
[CGSPCLKEN]
<ADCKEN>
EHCLKI N
f
IH O SC2
fsysh
CPU
1/4
ELOSC
PLL0
[CGSYSCR]
<MCKSE L[1:0]>
1/41/2
ΦT0m
1/41/2
[CGFSYSMENA]
<IPMENAx>
[CGFSYSENA]
<IP E NAx >
ΦT0h
[Peripheral function prescaler inputs]
（Mid dle speed prescaler clock)
FUART,UART, T32A
TSPI6 to 8, I2S, TS SI
fsysm
UART, F UART , I2C, EI2C, TSSI,
I2S, T32A, ADC, DAC, TSPI6 to 8,
A-PMD, PORT, TR GS EL, OFD, NBD,
SIWDT, TR M
[CGFSYSMENA]
<IPMENAx>
[CGFSYSMENB]
<IP ME N Bx >
[CGFSYSMENC]
<IP ME N Cx >
CG, HDMAC,SM IF,EBIF,TSPI0 to 5
[CGFSYSENA]
<IP E NAx >
fsysh
fsysh
fsysh
fc
DNF
DEBUG
TRCLKIN
SIWDT
SIWDT
FLASH
LTTMR
[Peripheral function clock inputs]
RMC, CEC
MDMAC
[CG EXTEND2]
<RSV22[2:0]>
MDMACSWRST
（High speed system clock）
CPU, RAM0 to 2, BOOTROM,
CodeFL ASH, DataFLASH, INTIF(IB,IMN)
ELCLKIN
[R LM L O S CCR ]
<DRCOSCL>
（Mid dle speed system clock）
RAM3 to 5, BackupRAM,
FLASH(SFR), LTTMR, RLM, LVD,
INTIF(IA), RTC, ISD, RMC, CEC
ADCLK
[CGFCEN]
<FCIPENx>
Note: The state after the initialization done by the reset from the pin depends on [RLM LOSCCR]<POSCEN> setting.
[CGFCEN]
<FCIPEN23>
Figure 1.1 Clock system diagram

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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Warming up function
A warming up function starts the warming up timer for high speed oscillator automatically to secure the oscillation
stable time when the STOP1 mode is released.
It is also available as a count-up timer which uses the warming up timer for high speed oscillator to secure the
stability of an external oscillator or an internal oscillator.
This chapter explains the setting method to the register for warming up timers, and the case where it is used as a
count-up timer. The detailed explanation at the time of STOP1 mode release, refer to "1.3.3.2 Warming up at the
release of Low Power Consumption mode".
The warming up timer for a high speed oscillation
A 16-bit up-counter is built in as a warming up timer only for a high speed oscillation. Also when setting it before
changes to the STOP1 mode, calculate with the following formula and set [CGWUPHCR]<WUPT[15:4]> to the
upper 12 bits of the result. Lower 4bits are ignored.
<Formula>
(Using external high speed oscillator)
Warming up timer setting value (16 bits)
= (warming up time (s) / clock period (s)) - 16
(Example) When 5ms of warming up time is set up with 10 MHz (100 ns of clock periods) of oscillator
Warming up timer setting value (16 bits) = (5ms / 100ns) - 16
= 50000 - 16
= 49984
= 0xC340
Since upper 12 bits are used, set the register as follows.
[CGWUPHCR]<WUPT[15:4]> = 0xC34
(Using internal high speed oscillator1)
Warming up timer setting value (16 bits)
= (warming up time (s) -63.3μs ) / clock period (s)) - 41
(Example) When 163.4μs of warming time is set up with 10 MHz (100 ns of clock periods) of oscillator
Warming up timer setting value (16 bits) = ((163.4μs – 63.3μs) / 100ns) - 41
= (100.1μs / 100ns) - 41
= 960
= 0x03C0
Since upper 12 bits are used, set the register as follows.
[CGWUPHCR]<WUPT[15:4]> = 0x03C
Setting range is 0x03C ≤<WUPT[15:4]> ≤0xFFF, Warming up time is set from 163.4 μs to 6.6194 ms.

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TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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The warming up timer for a low speed oscillation
A 19-bit up-counter is built in as a warming up timer only for a low speed oscillation. Calculate with the following
formula and set [CGWUPHCR]<WUPT[18:4]> to the upper 15 bits of the result. Lower 4bits are ignored. 16 is
subtracted in order to perform the count for lower 4bits, even when a set point is 0x0000.
<Formula>
Warming up timer setting value (19 bits)
= (warming up time (s) / clock period (s)) - 16
(Example) When 50 ms of warming time is set up with 32 kHz (clock period 31.25μs) of oscillators
Warming up timer setting value (19 bits) = (50ms / 31.25μs) - 16
= 1600 - 16
= 1584
= 0x00630
Since upper 15 bits are used, set the register as follows.
[CGWUPLCR]<WUPTL[18:4]> = 0x0063
In the case of 32 kHz, it setting range is 0x0000 ≤<WUPTL[18:4]> ≤0x7FFF, Warming up time is set from
500μs to 16.384s.
The directions for a warming up timer
The directions for a warming up function are explained.
(1) Selection of a clock
In a high speed oscillation, the clock classification (an internal oscillation/external oscillation) counted with
a warming-up timer is selected by [CGWUPHCR] <WUCLK>.
(2) Calculation of a warming up timer setting value
The warming up time can set any value to the timer for a high speed oscillation / for a low speed oscillation.
Please compute and set up from each formula.
(3) The start of warming up, and a termination Confirmation
When software (command) performs the start of warming-up, starting warming-up count is carried out by
setting [CGWUPHCR]<WUON> (or [CGWUPLCR] <WULON>) to "1".
Termination is confirmed with [CGWUPHCR]<WUEF> (or [CGWUPLCR] <WULEF>) that becomes
from "1" to "0". "1" indicates under warming up and "0" indicates termination. After a counting end, the
timer is reset and returns to an initial state.
It is not forced to terminate, although "0" is written to [CGWUPHCR]<WUON>(or [CGWUPLCR]
<WULON>) during timer operation. Writing "0" is ignored.
Note: Since it is operating with the oscillating clock, a warming up timer includes an error, when Oscillation
frequency has fluctuation. Therefore, it should be taken as an approximate time.

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
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Clock multiplying circuit (PLL) for fsys
The clock multiplying circuit outputs the fPLL clock (maximum 200MHz) multiplied by the optimum condition for
the frequency (8 MHz to 24 MHz) of the output clock fOSC of the high speed oscillator.
So, it is possible to make frequency to an oscillator low and to make an internal clock high speed by this circuit.
PLL setup after reset release
The PLL is disabled after reset release.
In order to use the PLL, set [CGPLL0SEL]<PLL0SET[23:0]> to a multiplication value while [CGPLL0SEL]
<PLL0ON> is "0". Then wait until approximately 100 μs has elapsed as a PLL initial stabilization time, and set
<PLL0ON> to "1" to start PLL operation.
After that, to use fPLL clock which is multiplied fosc, wait until approximately 400 μs has elapsed as a lock up time.
Then set "1" to [CGPLL0SEL]<PLL0SEL>.
Note that a warming up time is required until PLL operation becomes stable using the warming up function, etc.
The formula and the example of a setting of a PLL multiplication value
The details of the items of [CGPLL0SEL] <PLL0SET[23:0]> which set up a PLL multiplication value are shown
below.
Table 1.1 Details of a [CGPLL0SEL] <PLL0SET [23:0]>setup
The items of PLL0SET
Function
[23:17]
Correction
value setup
The quotient of f
OSC
/450000 (integer). For detail refer to the Table
1.2.
[16:14]
fosc setup
000: 6 ≤ fosc ≤ 7(Unit: MHz)
001: 7 < fosc ≤ 8
010: 8 < fosc ≤ 10
011: 10 < fosc ≤ 12
100: 12 < fosc ≤ 15
101: 15 < fosc ≤ 19
110: 19 < fosc ≤ 24
111: Reserved
[13:12]
Dividing setup
00: Reserved
01: Dividing by 2 (x1/2)
10: Dividing by 4 (x1/4)
11: Dividing by 8 (x1/8)
[11:8]
Fractional part
Multiplication
setup
0000: 0.0000
0001: 0.0625
0010: 0.1250
0011: 0.1875
0100: 0.2500
0101: 0.3125
0110: 0.3750
0111: 0.4375
1000: 0.5000
1001: 0.5625
1010: 0.6250
1011: 0.6875
1100: 0.7500
1101: 0.8125
1110: 0.8750
1111: 0.9375
[7:0]
Integer part
Multiplication
setup
0x00: 0
0x01: 1
0x02: 2
:
0xFD: 253
0xFE: 254
0xFF: 255
Note: A multiplication value is the total of <PLL0SET [7:0]> (integer part) and <PLL0SET [11:8]>
(fractional part).
fPLL is denoted by the following formulas.
fPLL= fosc x([CGPLL0SEL] <PLL0SET[7:0]> + [CGPLL0SEL] <PLL0SET [11:8]>) x ([CGPLL0SEL]
<PLL0SET [13:12]>)
Note1: Frequency accuracy is not guaranteed.

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Note2: There is no Linearity in the frequency by the Fractional part Multiplication setup.
Note3: fPLL ≤Maximum Operating Frequency
Table 1.2 PLL correction (example)
fOSC(MHz) <PLL0SET [23:17] >
(a decimal, an integral value)
8.00 18
10.00 23
12.00 27
16.00 36
20.00 45
24.00 54
The PLL correction value can be calculated below.
fosc = 10.0 MHz o'clock, 10.0/0.45 = 22.22 23;
A fractional part is rounded up.
The main examples of a setting of [CGPLL0SEL] <PLL0SET [23:0]> are shown below.
It multiplies by PLL, and dividing is carried out and the target Clock frequency (fPLL) is generated for input
frequency (fosc).
A dividing value is chosen from 1/2, 1/4, and 1/8.
Moreover, set up the frequency after multiplication in the following ranges.
200 MHz ≤(fOSC × Multiplication value) ≤400 MHz
Table 1.3 PLL0SET setting value (example)
f
osc
(MHz)
Multiplication
value
Dividing
value
f
PLL
(MHz)
<PLL0SET[23:0]>
8.00 50.0000 1/2 200 0x245032
10.00 40.0000 1/2 200 0x2E9028
12.00
33.3150
1/2
199.89
0x36D521
16.00
25.0000
1/2
200
0x495019
16.00 12.5000 1/2 100 0x49580C
20.00 20.0000 1/2 200 0x5B9014
24.00 16.6575 1/2 199.89
0x6D9A10
Change of the PLL multiplication value under operation
To change the setting of a PLL multiplication during PLL multiplication clock operation, set
[CGPLL0SEL]<PLL0SEL> to "0" that does not use a PLL multiplication clock. And [CGPLL0SEL] <PLL0ST>
=0 is read to confirm that a multiplication clock setting is not used, then, [CGPLL0SEL] <PLL0ON> is set to "0",
and PLL is stopped.
Then, the multiplication value of [CGPLL0SEL] <PLL0SET[23:0]> is changed, as reset time of PLL, after about
100 μs has elapsed [CGPLL0SEL] <PLL0ON> is set to "1", and operation of PLL is started.
Then, [CGPLL0SEL] <PLL0SEL> is set to "1" after lock-up time (about 400µs) has elapsed.
Finally, [CGPLL0SEL]<PLL0ST> are read and it checks having changed.

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PLL operation start / stop / switching procedure
(1) fc setup (PLL stop → PLL start)
As an fc setup, the example of switching procedure from the PLL stop state to the PLL operation state is as
follows.
<< The example of switching procedure >>
1 [CGSYSCR]<MCKSEL[1:0]> = 01 or 1*
Ratios of (High speed system clock vs Middle speed system clock)
and (High speed prescaler clock vs High speed system clock) are
changed.
2
[CGSYSCR]<MCKSELGST><MCKSELPST>
is read
Wait until they become the values set at Step 1.
3
[CGPLL0SEL] <PLL0SET[23:0]> = 0xX
A PLL multiplication value setup is chosen.
4
Wait 100 μs or more.
Latency time after a multiplication setup
5
[CGPLL0SEL]<PLL0ON> = 1
PLL operation for fsys is carried out to an oscillation.
6
Wait 400 μs or more.
PLL output clock stable latency time
7
[CGPLL0SEL]<PLL0SEL> = 1
PLL selection for fsys is carried out to PLL use (fPLL).
8 [CGPLL0SEL]<PLL0ST> is read
It waits until the PLL selection status for fsys becomes PLL use (f
PLL
)
(= 1).
Note1: 1 and 2 are executed when the ratio of the system clock should be changed.
Note2: 3 to 6 are unnecessary when the state before switching is [CGPLL0SEL] <PLL0ON> = 1.
When changing from the state where the PLL output clock is stable, it can be changed to the PLL
operation state by execution of only 7 and 8.
(2) fc setup (conduct PLL → PLL stop)
As an fc setup, the example of switching procedure from the PLL operation state to a PLL stop state is as follows.
<< The example of switching sequence >>
1
[CGPLL0SEL]<PLL0SEL> = 0
Select the PLL for fsys to “PLL is unused (fosc)”.
2 [CGPLL0SEL]<PLL0ST> is read
Wait until the status of the PLL for fsys becomes “PLL is unused
(fosc) (=0)”.
3
[CGPLL0SEL]<PLL0ON> =0
Set the PLL operation for fsys to stop.
<< The state before switching >>
[CGPLL0SEL]<PLL0ON> = 0
Stops the PLL operation for fsys.
[CGPLL0SEL]<PLL0SEL> = 0
Selects the setting of the PLL for fsys to “PLL is unused (fosc)”.
[CGPLL0SEL]<PLL0ST> = 0
Indicates the status of the PLL for fsys to “PLL is unused (fosc)”.
[CGSYSCR]<MCKSEL> = 00
Ratios of (High speed system clock vs Middle speed system clock)
and (High speed prescaler clock vs Middle speed system clock) are
1:1.
<< The state before switching >>
[CGPLL0SEL]<PLL0ON> = 1
Sets the PLL for fsys to oscillate.
[CGPLL0SEL]<PLL0SEL> = 1
Selects the PLL for fsys to “PLL is used (fPLL)”.
[CGPLL0SEL]<PLL0ST> = 1
Indicates the status of the PLL for fsys to “PLL is used (fPLL)”.

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System clock
An internal high speed oscillation clock or external high speed oscillation clock (connected oscillator or clock
input) can be used as a source of system clock.
The system clock consists of “High speed system clock (fsysh)(maximum 200MHz )” for high speed operation and
“Middle speed system clock (fsysm)(maximum 100MHz)” which is generated by dividing High speed system clock.
Middle speed system clock is used by peripheral function to save power dissipation without degrading CPU
performance. The clock domains of the peripheral function can be checked in Table 1.4.
High speed system clock can be generated by dividing fc using [CGSYSCR] <GEAR [2:0]> (Clock gear). And
Middle speed system clock is generated by dividing the high speed system clock using [CGSYSCR]
<MCKSEL[1:0]>. Although a setting can be changed during operation, after register writing before the clock
actually changes, a time interval shown in Table 1.5 is required. The completion of the clock change should be
checked by [CGSYSCR] <GEARST [2:0]> <MCKSELGST[1:0]>.
Table 1.4 Clock domains of CPU and peripherals
Clock domain
Block
High speed system clock
CPU, Code FLASH, Data FLASH, HDMAC, EBIF, SMIF,
TSPI(ch0 to 5), CG, INTIF, RAM0 to 2, BootROM
Middle speed system clock
MDMAC, NBDIF, I2C, SIWDT, UART, FUART, DAC, TSPI(ch6 to
8), T32A, ADC, Port, PMD, DNF, LTTMR, LVD, RLM, ISD, TRM,
FLASH(SFR), OFD, EI2C, I2S, FIR, TSSI, TRGSEL, RAM3 to 5,
Backup RAM
Table 1.5 Time interval for changing System clock
System clock
High speed (fsysh)
Middle speed (fsysm)
fsys
16 fc cycles at maximum
16 fc cycles at maximum
fsys/2
-
32 fc cycles at maximum
fsys/4
-
64 fc cycles at maximum
Note1: The clock gear and the system clock should not be changed while the peripheral function such as the
timer/counter is operating.
Note2: An access between High speed system clock domain and Middle speed system clock domain cannot be
done when the system clock is changing.

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Table 1.6 shows the example of operating frequency by the clock gear ratio (1/1 to 1/16) to the frequency fc set up
with Oscillation frequency, a PLL multiplication value, etc.
Table 1.6 Example of operating frequency
External
Oscillation
(MHz)
External
Clock
input
(MHz)
Built-in
oscillation
IHOSC1
(MHz)
PLL
Multiplication
value
(after dividing)
Maximum
Frequency
(fc)(MHz)
Operating frequency (MHz) by
clock gear ratio
PLL=ON
Operating frequency (MHz)
by clock gear ratio
PLL=OFF
1/1 1/2 1/4 1/8 1/16 1/1 1/2 1/4 1/8 1/16
8 8 - 25 200 200 100 50 25 12.5 8 4 2 1 -
10 10 10 20 200 200 100 50 25 12.5 10 5 2.5 1.25 -
12 12 - 16 192 192 96 48 24 12 12 6 3 1.5 -
16 16 - 12 192 192 96 48 24 12 16 8 4 2 1
20 20 - 10 200 200 100 50 25 12.5 20 10 5 2.5 1.25
Table 1.7 Operating frequency examples of High speed and Middle speed system clocks
High speed
system clock
fsysh (MHz)
Middle speed system
clock
fsysm (MHz)
1/1
1/2
1/4
200 - 100 50
160 - 80 40
100 100 50 25
80 80 40 20
Note: The maximum frequency of Middle speed system clock is 100 MHz.
The setting method of a system clock
(1) fosc setup (Internal oscillation → External oscillation)
As a fosc setup, the example of switching procedure to the external high speed oscillation (EHOSC) from an
internal high speed oscillation 1 (IHOSC1) is shown below.
<< The example of switching procedure >>
1
[PYPDN]<bit[1:0]> = 00
[PYPUP]<bit[1:0]> = 00
[PYIE]<bit[1:0]> = 00
Disable the pull-down resistors of X1 and X2 pins.
Disable the pull-up resistors of X1 and X2 pins.
Disable input control of X1 and X2 pins.
2 [CGOSCCR]<EOSCEN[1:0]> = 01
It is an external oscillation (EHOSC) about selection of an external
oscillation of operation.
3
[CGWUPHCR]<WUCLK> = 1
[CGWUPHCR] <WUPT[15:4]> =
arbitrary value
It is the external (EHOSC) about high speed oscillation warming up
clock selection.
A warming-up timer is set to
oscillator stable time.
4
[CGWUPHCR]<WUON> = 1
High speed oscillation warming up is started.
5 [CGWUPHCR]<WUEF> is read.
It waits until it becomes the termination of high speed oscillation
warming up (= 0).
6
[CGOSCCR]<OSCSEL> = 1
It is high speed oscillation selection for fosc to the exterior (EHOSC).
7 [CGOSCCR]<OSCF> is read
It waits until the high speed oscillation selection status for fosc
becomes outside (= 1).
8
[CGOSCCR]<IHOSC1EN> = 0
An internal high speed oscillator1 is suspended.
<< The state before switching >>
[CGOSCCR]<IHOSC1EN> = 1
An internal high speed oscillator1 oscillates.
[CGOSCCR]<OSCSEL> = 0
The high speed oscillation selection for fosc is an inside (IHOSC1).
[CGOSCCR]<OSCF> = 0
The high speed oscillation selection status for fosc is an inside
(IHOSC1).
An oscillator is connected to X1 / X2 pin.
Do not connect any devices except a resonator.