Texas Instruments Sitara AM335x User manual

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
AM335x Sitara™ Processors
1 Device Overview
1.1 Features
1– Supports Protocols such as EtherCAT®,
• Up to 1-GHz Sitara™ ARM®Cortex®-A8 32‑Bit PROFIBUS, PROFINET, EtherNet/IP™, and
RISC Processor More
– NEON™ SIMD Coprocessor – Two Programmable Real-Time Units (PRUs)
– 32KB of L1 Instruction and 32KB of Data Cache • 32-Bit Load/Store RISC Processor Capable
With Single-Error Detection (Parity) of Running at 200 MHz
– 256KB of L2 Cache With Error Correcting Code • 8KB of Instruction RAM With Single-Error
(ECC) Detection (Parity)
– 176KB of On-Chip Boot ROM • 8KB of Data RAM With Single-Error
– 64KB of Dedicated RAM Detection (Parity)
– Emulation and Debug - JTAG • Single-Cycle 32-Bit Multiplier With 64-Bit
– Interrupt Controller (up to 128 Interrupt Accumulator
Requests) • Enhanced GPIO Module Provides Shift-
• On-Chip Memory (Shared L3 RAM) In/Out Support and Parallel Latch on
– 64KB of General-Purpose On-Chip Memory External Signal
Controller (OCMC) RAM – 12KB of Shared RAM With Single-Error
– Accessible to All Masters Detection (Parity)
– Supports Retention for Fast Wakeup – Three 120-Byte Register Banks Accessible by
• External Memory Interfaces (EMIF) Each PRU
– mDDR(LPDDR), DDR2, DDR3, DDR3L – Interrupt Controller Module (INTC) for Handling
Controller: System Input Events
• mDDR: 200-MHz Clock (400-MHz Data – Local Interconnect Bus for Connecting Internal
Rate) and External Masters to the Resources Inside
• DDR2: 266-MHz Clock (532-MHz Data Rate) the PRU-ICSS
• DDR3: 400-MHz Clock (800-MHz Data Rate) – Peripherals Inside the PRU-ICSS:
• DDR3L: 400-MHz Clock (800-MHz Data • One UART Port With Flow Control Pins,
Rate) Supports up to 12 Mbps
• 16-Bit Data Bus • One Enhanced Capture (eCAP) Module
• 1GB of Total Addressable Space • Two MII Ethernet Ports that Support
Industrial Ethernet, such as EtherCAT
• Supports One x16 or Two x8 Memory Device
Configurations • One MDIO Port
– General-Purpose Memory Controller (GPMC) • Power, Reset, and Clock Management (PRCM)
Module
• Flexible 8-Bit and 16-Bit Asynchronous
Memory Interface With up to Seven Chip – Controls the Entry and Exit of Stand-By and
Selects (NAND, NOR, Muxed-NOR, SRAM) Deep-Sleep Modes
• Uses BCH Code to Support 4-, 8-, or 16-Bit – Responsible for Sleep Sequencing, Power
ECC Domain Switch-Off Sequencing, Wake-Up
Sequencing, and Power Domain Switch-On
• Uses Hamming Code to Support 1-Bit ECC Sequencing
– Error Locator Module (ELM) – Clocks
• Used in Conjunction With the GPMC to • Integrated 15- to 35-MHz High-Frequency
Locate Addresses of Data Errors from Oscillator Used to Generate a Reference
Syndrome Polynomials Generated Using a Clock for Various System and Peripheral
BCH Algorithm Clocks
• Supports 4-, 8-, and 16-Bit per 512-Byte • Supports Individual Clock Enable and
Block Error Location Based on BCH Disable Control for Subsystems and
Algorithms Peripherals to Facilitate Reduced Power
• Programmable Real-Time Unit Subsystem and Consumption
Industrial Communication Subsystem (PRU-ICSS)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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• Five ADPLLs to Generate System Clocks Transmission (SPDIF, IEC60958-1, and
(MPU Subsystem, DDR Interface, USB and AES-3 Formats)
Peripherals [MMC and SD, UART, SPI, I2C], • FIFO Buffers for Transmit and Receive (256
L3, L4, Ethernet, GFX [SGX530], LCD Pixel Bytes)
Clock) – Up to Six UARTs
– Power • All UARTs Support IrDA and CIR Modes
• Two Nonswitchable Power Domains (Real- • All UARTs Support RTS and CTS Flow
Time Clock [RTC], Wake-Up Logic Control
[WAKEUP]) • UART1 Supports Full Modem Control
• Three Switchable Power Domains (MPU – Up to Two Master and Slave McSPI Serial
Subsystem [MPU], SGX530 [GFX], Interfaces
Peripherals and Infrastructure [PER]) • Up to Two Chip Selects
• Implements SmartReflex™ Class 2B for • Up to 48 MHz
Core Voltage Scaling Based On Die – Up to Three MMC, SD, SDIO Ports
Temperature, Process Variation, and • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
Performance (Adaptive Voltage Scaling
[AVS]) • MMCSD0 has Dedicated Power Rail for
1.8‑V or 3.3-V Operation
• Dynamic Voltage Frequency Scaling (DVFS) • Up to 48-MHz Data Transfer Rate
• Real-Time Clock (RTC) • Supports Card Detect and Write Protect
– Real-Time Date (Day-Month-Year-Day of Week)
and Time (Hours-Minutes-Seconds) Information • Complies With MMC4.3, SD, SDIO 2.0
Specifications
– Internal 32.768-kHz Oscillator, RTC Logic and
1.1-V Internal LDO – Up to Three I2C Master and Slave Interfaces
– Independent Power-on-Reset • Standard Mode (up to 100 kHz)
(RTC_PWRONRSTn) Input • Fast Mode (up to 400 kHz)
– Dedicated Input Pin (EXT_WAKEUP) for – Up to Four Banks of General-Purpose I/O
External Wake Events (GPIO) Pins
– Programmable Alarm Can be Used to Generate • 32 GPIO Pins per Bank (Multiplexed With
Internal Interrupts to the PRCM (for Wakeup) or Other Functional Pins)
Cortex-A8 (for Event Notification) • GPIO Pins Can be Used as Interrupt Inputs
– Programmable Alarm Can be Used With (up to Two Interrupt Inputs per Bank)
External Output (PMIC_POWER_EN) to Enable – Up to Three External DMA Event Inputs that can
the Power Management IC to Restore Non-RTC Also be Used as Interrupt Inputs
Power Domains – Eight 32-Bit General-Purpose Timers
• Peripherals • DMTIMER1 is a 1-ms Timer Used for
– Up to Two USB 2.0 High-Speed OTG Ports Operating System (OS) Ticks
With Integrated PHY • DMTIMER4–DMTIMER7 are Pinned Out
– Up to Two Industrial Gigabit Ethernet MACs (10, – One Watchdog Timer
100, 1000 Mbps) – SGX530 3D Graphics Engine
• Integrated Switch • Tile-Based Architecture Delivering up to 20
• Each MAC Supports MII, RMII, RGMII, and Million Polygons per Second
MDIO Interfaces • Universal Scalable Shader Engine (USSE) is
• Ethernet MACs and Switch Can Operate a Multithreaded Engine Incorporating Pixel
Independent of Other Functions and Vertex Shader Functionality
• IEEE 1588v2 Precision Time Protocol (PTP) • Advanced Shader Feature Set in Excess of
– Up to Two Controller-Area Network (CAN) Ports Microsoft VS3.0, PS3.0, and OGL2.0
• Supports CAN Version 2 Parts A and B • Industry Standard API Support of Direct3D
– Up to Two Multichannel Audio Serial Ports Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0,
(McASPs) and OpenMax
• Transmit and Receive Clocks up to 50 MHz • Fine-Grained Task Switching, Load
• Up to Four Serial Data Pins per McASP Port Balancing, and Power Management
With Independent TX and RX Clocks • Advanced Geometry DMA-Driven Operation
• Supports Time Division Multiplexing (TDM), for Minimum CPU Interaction
Inter-IC Sound (I2S), and Similar Formats • Programmable High-Quality Image Anti-
• Supports Digital Audio Interface Aliasing
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• Fully Virtualized Memory Addressing for OS – Up to Three 32-Bit Enhanced Quadrature
Operation in a Unified Memory Architecture Encoder Pulse (eQEP) Modules
– LCD Controller • Device Identification
– Contains Electrical Fuse Farm (FuseFarm) of
• Up to 24-Bit Data Output; 8 Bits per Pixel Which Some Bits are Factory Programmable
(RGB) • Production ID
• Resolution up to 2048 × 2048 (With
Maximum 126-MHz Pixel Clock) • Device Part Number (Unique JTAG ID)
• Integrated LCD Interface Display Driver • Device Revision (Readable by Host ARM)
(LIDD) Controller • Debug Interface Support
• Integrated Raster Controller – JTAG and cJTAG for ARM (Cortex-A8 and
• Integrated DMA Engine to Pull Data from the PRCM), PRU-ICSS Debug
External Frame Buffer Without Burdening the – Supports Device Boundary Scan
Processor via Interrupts or a Firmware Timer – Supports IEEE 1500
• 512-Word Deep Internal FIFO • DMA
• Supported Display Types: – On-Chip Enhanced DMA Controller (EDMA) has
– Character Displays - Uses LIDD Three Third-Party Transfer Controllers (TPTCs)
Controller to Program these Displays and One Third-Party Channel Controller
– Passive Matrix LCD Displays - Uses LCD (TPCC), Which Supports up to 64
Raster Display Controller to Provide Programmable Logical Channels and Eight
Timing and Data for Constant Graphics QDMA Channels. EDMA is Used for:
Refresh to a Passive Display • Transfers to and from On-Chip Memories
– Active Matrix LCD Displays - Uses • Transfers to and from External Storage
External Frame Buffer Space and the (EMIF, GPMC, Slave Peripherals)
Internal DMA Engine to Drive Streaming • Inter-Processor Communication (IPC)
Data to the Panel – Integrates Hardware-Based Mailbox for IPC and
– 12-Bit Successive Approximation Register Spinlock for Process Synchronization Between
(SAR) ADC Cortex-A8, PRCM, and PRU-ICSS
• 200K Samples per Second • Mailbox Registers that Generate Interrupts
• Input can be Selected from any of the Eight – Four Initiators (Cortex-A8, PRCM, PRU0,
Analog Inputs Multiplexed Through an 8:1 PRU1)
Analog Switch • Spinlock has 128 Software-Assigned Lock
• Can be Configured to Operate as a 4-Wire, Registers
5-Wire, or 8-Wire Resistive Touch Screen • Security
Controller (TSC) Interface – Crypto Hardware Accelerators (AES, SHA, PKA,
– Up to Three 32-Bit eCAP Modules RNG)
• Configurable as Three Capture Inputs or • Boot Modes
Three Auxiliary PWM Outputs – Boot Mode is Selected via Boot Configuration
– Up to Three Enhanced High-Resolution PWM Pins Latched on the Rising Edge of the
Modules (eHRPWMs) PWRONRSTn Reset Input Pin
• Dedicated 16-Bit Time-Base Counter With • Packages:
Time and Frequency Controls – 298-Pin S-PBGA-N298 Via Channel Package
• Configurable as Six Single-Ended, Six Dual- (ZCE Suffix), 0.65-mm Ball Pitch
Edge Symmetric, or Three Dual-Edge – 324-Pin S-PBGA-N324 Package
Asymmetric Outputs (ZCZ Suffix), 0.80-mm Ball Pitch
1.2 Applications
• Gaming Peripherals • Connected Vending Machines
• Home and Industrial Automation • Weighing Scales
• Consumer Medical Appliances • Educational Consoles
• Printers • Advanced Toys
• Smart Toll Systems
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1.3 Description
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image,
graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The
devices support high-level operating systems (HLOS). Linux®and Android™ are available free of charge
from TI.
The AM335x microprocessor contain the subsystems shown in Figure 1-1 and a brief description of each
follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR
SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming
effects.
The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) is
separate from the ARM core, allowing independent operation and clocking for greater efficiency and
flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as
EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the
programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC)
resources, provides flexibility in implementing fast, real-time responses, specialized data handling
operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE
AM3359ZCZ NFBGA (324) 15.0 mm x 15.0 mm
AM3358ZCZ NFBGA (324) 15.0 mm x 15.0 mm
AM3357ZCZ NFBGA (324) 15.0 mm x 15.0 mm
AM3356ZCZ, AM3356ZCE NFBGA (324), NFBGA (298) 15.0 mm x 15.0 mm, 13.0 mm x 13.0 mm
AM3354ZCZ, AM3354ZCE NFBGA (324), NFBGA (298) 15.0 mm x 15.0 mm, 13.0 mm x 13.0 mm
AM3352ZCZ, AM3352ZCE NFBGA (324), NFBGA (298) 15.0 mm x 15.0 mm, 13.0 mm x 13.0 mm
(1) For more information, see Section 9,Mechanical Packaging and Orderable Information.
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ARM
Cortex-A8
Up to 1 GHz
32K and 32K L1 + SED
256K L2 + ECC
176K ROM 64K RAM
Graphics
PowerVR
SGX
3D GFX
Crypto
64K
shared
RAM
24-bit LCD controller
Touch screen controller
Display
PRU-ICSS
EtherCAT, PROFINET,
EtherNet/IP,
and more
L3 and L4 interconnect
USB 2.0 HS
OTG + PHY x2
CAN x2
(Ver. 2 A and B)
McASP x2
(4 channel)
I C x3
2
SPI x2
UART x6
Serial System Parallel
eDMA
Timers x8
WDT
RTC
eHRPWM x3
eQEP x3
PRCM
eCAP x3
ADC (8 channel)
12-bit SAR
JTAG
Crystal
Oscillator x2
MMC, SD and
SDIO x3
GPIO
EMAC (2-port) 10M, 100M, 1G
IEEE 1588v2, and switch
(MII, RMII, RGMII)
mDDR(LPDDR), DDR2,
DDR3, DDR3L
(16-bit; 200, 266, 400, 400 MHz)
NAND and NOR (16-bit ECC)
Memory interface
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1.4 Functional Block Diagram
Figure 1-1 shows the AM335x microprocessor functional block diagram.
Figure 1-1. AM335x Functional Block Diagram
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Table of Contents
7.2 Recommended Clock and Control Signal Transition
1 Device Overview ......................................... 1Behavior............................................ 116
1.1 Features .............................................. 17.3 OPP50 Support.................................... 116
1.2 Applications........................................... 37.4 Controller Area Network (CAN).................... 117
1.3 Description............................................ 47.5 DMTimer ........................................... 118
1.4 Functional Block Diagram ........................... 57.6 Ethernet Media Access Controller (EMAC) and
2 Revision History ......................................... 7Switch.............................................. 119
3 Device Comparison ..................................... 87.7 External Memory Interfaces........................ 127
4 Terminal Configuration and Functions ............ 10 7.8 I2C.................................................. 191
4.1 Pin Diagrams........................................ 10 7.9 JTAG Electrical Data and Timing.................. 193
4.2 Pin Attributes........................................ 18 7.10 LCD Controller (LCDC) ............................ 194
4.3 Signal Descriptions.................................. 51 7.11 Multichannel Audio Serial Port (McASP) .......... 210
5 Specifications........................................... 80 7.12 Multichannel Serial Port Interface (McSPI) ........ 215
5.1 Absolute Maximum Ratings......................... 80 7.13 Multimedia Card (MMC) Interface ................. 221
5.2 ESD Ratings ........................................ 81 7.14 Programmable Real-Time Unit Subsystem and
5.3 Power-On Hours (POH)............................. 82 Industrial Communication Subsystem (PRU-ICSS) 224
5.4 Operating Performance Points (OPPs) ............. 82 7.15 Universal Asynchronous Receiver Transmitter
(UART)............................................. 233
5.5 Recommended Operating Conditions............... 85 8 Device and Documentation Support.............. 236
5.6 Power Consumption Summary...................... 87 8.1 Device Support..................................... 236
5.7 DC Electrical Characteristics........................ 89 8.2 Documentation Support............................ 238
5.8 Thermal Resistance Characteristics for ZCE and
ZCZ Packages ...................................... 93 8.3 Related Links ...................................... 238
5.9 External Capacitors ................................. 94 8.4 Community Resources............................. 239
5.10 Touch Screen Controller and Analog-to-Digital 8.5 Trademarks ........................................ 239
Subsystem Electrical Parameters................... 97 8.6 Electrostatic Discharge Caution ................... 239
6 Power and Clocking ................................... 99 8.7 Glossary............................................ 239
6.1 Power Supplies...................................... 99 9 Mechanical, Packaging, and Orderable
6.2 Clock Specifications................................ 107 Information............................................. 240
7 Peripheral Information and Timings .............. 116 9.1 Via Channel........................................ 240
7.1 Parameter Information ............................. 116 9.2 Packaging Information ............................. 240
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (June 2014) to Revision H Page
• Changed PRU-ICSS description and added industrial extended temperature and Footnote (4) for AM3352 in
Table 3-1............................................................................................................................... 8
• Changed Section 4 title to Terminal Configuration and Functions............................................................ 10
• Changed Section 4.1 title to Pin Diagrams ...................................................................................... 10
• Changed Section 4.2 title to Pin Attributes ...................................................................................... 18
• Added Industrial Extended temperatures to Table 5-1......................................................................... 82
• Added Industrial Extended Temperature values to Parameters F13 and F22 in Table 7-21............................ 127
• Changed Parameter F7, F15, and F17 OPP50 MAX value and added Footnote to F7, F15 and F17; added
additional Parameters F7, F15, and F17 and corresponding Footnotes in Table 7-22................................... 128
• Deleted FAST MODE MIN values for Parameters 9-12 and Footnote (4) in Table 7-69. These values were
incorrectly added in Revision G.................................................................................................. 191
• Deleted FAST MODE MIN values for Parameters 23-26 and Footnote (1) in Table 7-70. These values were
incorrectly added in Revision G.................................................................................................. 192
• Added Industrial Extended Temperature values to Parameter 5 in Table 7-84 ........................................... 218
• Added Industrial Extended Temperature values and added 1.8-V and 3.3-V Mode to Table 7-87..................... 221
• Changed MIN values for Parameters 12 and 13 in Table 7-90.............................................................. 223
• Added industrial extended temperature range to Figure 8-1................................................................. 237
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3 Device Comparison
Table 3-1 shows the features supported across different AM335x devices.
Table 3-1. Device Features Comparison
FUNCTION AM3352 AM3354 AM3356 AM3357 AM3358 AM3359
ARM Cortex-A8 Yes Yes Yes Yes Yes Yes
Frequency(1) 300 MHz 600 MHz 300 MHz 300 MHz 600 MHz 600 MHz
600 MHz 800 MHz 600 MHz 600 MHz 800 MHz 800 MHz
800 MHz 1000 MHz 800 MHz 800 MHz 1000 MHz
1000 MHz
MIPS(2) 600 1200 600 600 1200 1200
1200 1600 1200 1200 1600 1600
1600 2000 1600 1600 2000
2000
On-chip L1 cache 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB
On-chip L2 cache 256 KB 256 KB 256 KB 256 KB 256 KB 256 KB
Graphics accelerator (SGX530) — 3D — — 3D 3D
Hardware acceleration Crypto Crypto Crypto Crypto Crypto Crypto
accelerator accelerator accelerator accelerator accelerator accelerator
Programmable real-time unit subsystem — — Features Features Features Features
and industrial communication subsystem including basic including all including basic including all
(PRU-ICSS) Industrial Industrial Industrial Industrial
protocols protocols protocols protocols
On-chip memory 128 KB 128 KB 128 KB 128 KB 128 KB 128 KB
Display options LCD LCD LCD LCD LCD LCD
General-purpose memory 1 16-bit (GPMC, 1 16-bit (GPMC, 1 16-bit (GPMC, 1 16-bit (GPMC, 1 16-bit (GPMC, 1 16-bit (GPMC,
NAND flash, NAND flash, NAND flash, NAND flash, NAND flash, NAND flash,
NOR flash, NOR flash, NOR flash, NOR flash, NOR flash, NOR flash,
SRAM) SRAM) SRAM) SRAM) SRAM) SRAM)
DRAM(3) 1 16-bit (LPDDR- 1 16-bit (LPDDR- 1 16-bit (LPDDR- 1 16-bit (LPDDR- 1 16-bit (LPDDR- 1 16-bit (LPDDR-
400, DDR2-532, 400, DDR2-532, 400, DDR2-532, 400, DDR2-532, 400, DDR2-532, 400, DDR2-532,
DDR3-800) DDR3-800) DDR3-800) DDR3-800) DDR3-800) DDR3-800)
Universal serial bus (USB) ZCE: 1 port ZCE: 1 port ZCE: 1 port No ZCE Available No ZCE Available No ZCE Available
ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports
Ethernet media access controller 10/100/1000 10/100/1000 10/100/1000 10/100/1000 10/100/1000 10/100/1000
(EMAC) with 2-port switch
Multimedia card (MMC) 3 3 3 3 3 3
Controller-area network (CAN) 2 2 2 2 2 2
Universal asynchronous receiver and 6 6 6 6 6 6
transmitter (UART)
Analog-to-digital converter (ADC) 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit
Enhanced high-resolution PWM modules 3 3 3 3 3 3
(eHRPWM)
Enhanced capture modules (eCAP) 3 3 3 3 3 3
Enhanced quadrature encoder pulse 3 3 3 3 3 3
(eQEP)
Real-time clock (RTC) 1 1 1 1 1 1
333333
Inter-integrated circuit (I2C)
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Table 3-1. Device Features Comparison (continued)
FUNCTION AM3352 AM3354 AM3356 AM3357 AM3358 AM3359
Multichannel audio serial port (McASP) 2 2 2 2 2 2
Multichannel serial port interface 2 2 2 2 2 2
(McSPI)
Enhanced direct memory access 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch
(EDMA)
Input/output (I/O) supply 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V
Operating temperature range -40 to 125°C(4) -40 to 105°C -40 to 105°C -40 to 105°C -40 to 105°C -40 to 105°C
-40 to 105°C -40 to 90°C -40 to 90°C -40 to 90°C -40 to 90°C -40 to 90°C
-40 to 90°C 0 to 90°C 0 to 90°C 0 to 90°C
0 to 90°C
(1) Frequencies listed correspond to silicon revision 2.1. Earlier silicon revisions support 275 MHz, 500 MHz, 600 MHz, and 720 MHz.
(2) MPIS listed correspond to silicon revision 2.1. Earlier silicon revisions support 560, 1000, 1200, and 1440.
(3) DRAM speeds listed are data rates.
(4) Industrial extended temperature only supported for 300-MHz and 600-MHz frequencies.
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4 Terminal Configuration and Functions
4.1 Pin Diagrams
NOTE
The terms 'ball', 'pin', and 'terminal' are used interchangeably throughout the document. An
attempt is made to use 'ball' only when referring to the physical package.
4.1.1 ZCE Package Pin Maps (Top View)
The pin maps below show the pin assignments on the ZCE package in three sections (left, middle, and
right).
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Left
Pin map section location
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ZCE Pin Map [Section Left - Top View]
A B C D E F
19 VSS I2C0_SCL UART1_TXD UART1_RTSn UART0_RXD UART0_CTSn
18 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RXD ECAP0_IN_PWM0_OUT UART0_RTSn
17 SPI0_CS0 SPI0_D1 EXTINTn XXXX UART1_CTSn UART0_TXD
16 WARMRSTn SPI0_CS1 XXXX XXXX XXXX VDDS
15 EMU0 XDMA_EVENT_INTR1 XDMA_EVENT_INTR0 XXXX PWRONRSTn XXXX
14 TDO TCK TMS EMU1 XXXX VDDSHV6
13 TRSTn TDI CAP_VBB_MPU CAP_VDD_SRAM_MPU VDDSHV6 VSS
12 AIN7 AIN5 VDDS_SRAM_MPU_BB VDDS VDDSHV6 VSS
11 AIN1 AIN3 XXXX XXXX VDDSHV6 VDD_CORE
10 AIN6 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VSS VSS XXXX
9VREFP VREFN XXXX XXXX VSS VDD_CORE
8AIN2 AIN0 AIN4 VSSA_ADC VSS VSS
7RTC_KALDO_ENn RTC_PWRONRSTn PMIC_POWER_EN VDDA_ADC VSS VSS
6RTC_XTALIN RESERVED VDDS_RTC CAP_VDD_RTC XXXX VSS
5RTC_XTALOUT EXT_WAKEUP VDDS_PLL_DDR XXXX DDR_A4 XXXX
4DDR_WEn DDR_BA2 XXXX XXXX XXXX DDR_A12
3DDR_BA0 DDR_A3 DDR_A8 XXXX DDR_A15 DDR_A0
2DDR_A5 DDR_A9 DDR_CK DDR_A7 DDR_A10 DDR_RASn
1VSS DDR_A6 DDR_CKn DDR_A2 DDR_BA1 DDR_CASn
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Middle
Pin map section location
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ZCE Pin Map [Section Middle - Top View]
G H J K L M
19 MMC0_CLK MMC0_DAT3 MII1_COL MII1_RX_ER MII1_RX_DV MII1_RX_CLK
18 MMC0_DAT0 MMC0_DAT2 MII1_CRS RMII1_REF_CLK MII1_TXD0 MII1_TXD1
17 MMC0_CMD MMC0_DAT1 XXXX MII1_TX_EN XXXX MII1_TXD3
16 USB0_DRVVBUS VDDS_PLL_MPU XXXX VDD_CORE XXXX VDDS
15 VDDSHV4 VDDSHV4 VSS VDD_CORE VSS VDDSHV5
14 XXXX VDDSHV4 VSS XXXX VSS VDDSHV5
13 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE
12 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE
11 VDD_CORE VSS VSS VSS VSS VSS
10 XXXX VSS XXXX XXXX XXXX VSS
9VDD_CORE VSS VSS VSS VSS VSS
8VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE
7XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE
6XXXX VDDS_DDR VSS XXXX VSS VDDS_DDR
5VDDS_DDR VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR
4DDR_A11 DDR_VREF XXXX VDDS_DDR XXXX DDR_D11
3DDR_CKE DDR_A14 XXXX DDR_DQM1 XXXX DDR_D10
2DDR_RESETn DDR_CSn0 DDR_A1 DDR_D8 DDR_DQSn1 DDR_D12
1DDR_ODT DDR_A13 DDR_VTP DDR_D9 DDR_DQS1 DDR_D13
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Right
Pin map section location
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ZCE Pin Map [Section Right - Top View]
N P R T U V W
19 MII1_TX_CLK MII1_RXD1 MDC USB0_VBUS USB0_DP USB0_ID VSS
18 MII1_TXD2 MII1_RXD0 VDDA3P3V_USB0 USB0_CE USB0_DM GPMC_BEn1 GPMC_WPn
17 MII1_RXD3 MDIO VDDA1P8V_USB0 XXXX GPMC_CSn3 GPMC_AD15 GPMC_AD14
16 MII1_RXD2 VSSA_USB XXXX XXXX XXXX GPMC_CLK GPMC_AD9
15 VDDSHV5 XXXX GPMC_WAIT0 XXXX GPMC_CSn2 GPMC_AD8 GPMC_AD7
14 XXXX VSS XXXX VDDS GPMC_AD6 GPMC_CSn1 GPMC_AD5
13 XXXX VSS VDDSHV1 GPMC_AD13 GPMC_AD12 GPMC_AD4 GPMC_AD3
12 VSS VSS VDDSHV1 GPMC_AD10 GPMC_AD11 GPMC_AD2 XTALOUT
11 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX VSS_OSC XTALIN
10 XXXX XXXX VSS VSS VDDS_OSC GPMC_ADVn_ALE GPMC_AD0
9VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX GPMC_AD1 GPMC_OEn_REn
8VSS VSS VDDSHV1 VDDS_PLL_CORE_LCD GPMC_WEn GPMC_BEn0_CLE GPMC_CSn0
7XXXX VSS VDDSHV6 LCD_HSYNC LCD_VSYNC LCD_DATA15 LCD_AC_BIAS_EN
6XXXX VDDSHV6 XXXX VDDS LCD_DATA13 LCD_DATA12 LCD_DATA14
5VDDS_DDR XXXX VPP XXXX LCD_DATA10 LCD_DATA11 LCD_PCLK
4DDR_D0 DDR_D1 XXXX XXXX XXXX LCD_DATA8 LCD_DATA9
3DDR_DQM0 DDR_D4 DDR_D7 XXXX LCD_DATA7 LCD_DATA6 LCD_DATA5
2DDR_D14 DDR_D2 DDR_DQSn0 DDR_D6 LCD_DATA1 LCD_DATA3 LCD_DATA4
1DDR_D15 DDR_D3 DDR_DQS0 DDR_D5 LCD_DATA0 LCD_DATA2 VSS
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4.1.2 ZCZ Package Pin Maps (Top View)
The pin maps below show the pin assignments on the ZCZ package in three sections (left, middle, and
right).
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Left
Pin map section location
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ZCZ Pin Map [Section Left - Top View]
A B C D E F
18 VSS EXTINTn ECAP0_IN_PWM0_OUT UART1_CTSn UART0_CTSn MMC0_DAT2
17 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RTSn UART0_RTSn MMC0_DAT3
16 SPI0_CS0 SPI0_D1 I2C0_SCL UART1_RXD UART0_TXD USB0_DRVVBUS
15 XDMA_EVENT_INTR0 PWRONRSTn SPI0_CS1 UART1_TXD UART0_RXD USB1_DRVVBUS
14 MCASP0_AHCLKX EMU1 EMU0 XDMA_EVENT_INTR1 VDDS VDDSHV6
13 MCASP0_ACLKX MCASP0_FSX MCASP0_FSR MCASP0_AXR1 VDDSHV6 VDD_MPU
12 TCK MCASP0_ACLKR MCASP0_AHCLKR MCASP0_AXR0 VDDSHV6 VDD_MPU
11 TDO TDI TMS CAP_VDD_SRAM_MPU VDDSHV6 VDD_MPU
10 WARMRSTn TRSTn CAP_VBB_MPU VDDS_SRAM_MPU_BB VDDSHV6 VDD_MPU
9VREFN VREFP AIN7 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VDDS
8AIN6 AIN5 AIN4 VDDA_ADC VSSA_ADC VSS
7AIN3 AIN2 AIN1 VDDS_RTC VDDS_PLL_DDR VDD_CORE
6RTC_XTALIN AIN0 PMIC_POWER_EN CAP_VDD_RTC VDDS VDD_CORE
5VSS_RTC RTC_PWRONRSTn EXT_WAKEUP DDR_A6 VDDS_DDR VDDS_DDR
4RTC_XTALOUT RTC_KALDO_ENn DDR_BA0 DDR_A8 DDR_A2 DDR_A10
3RESERVED DDR_BA2 DDR_A3 DDR_A15 DDR_A12 DDR_A0
2VDD_MPU_MON DDR_WEn DDR_A4 DDR_CK DDR_A7 DDR_A11
1VSS DDR_A5 DDR_A9 DDR_CKn DDR_BA1 DDR_CASn
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Middle
Pin map section location
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ZCZ Pin Map [Section Middle - Top View]
G H J K L M
18 MMC0_CMD RMII1_REF_CLK MII1_TXD3 MII1_TX_CLK MII1_RX_CLK MDC
17 MMC0_CLK MII1_CRS MII1_RX_DV MII1_TXD0 MII1_RXD3 MDIO
16 MMC0_DAT0 MII1_COL MII1_TX_EN MII1_TXD1 MII1_RXD2 MII1_RXD0
15 MMC0_DAT1 VDDS_PLL_MPU MII1_RX_ER MII1_TXD2 MII1_RXD1 USB0_CE
14 VDDSHV6 VDDSHV4 VDDSHV4 VDDSHV5 VDDSHV5 VSSA_USB
13 VDD_MPU VDD_MPU VDD_MPU VDDS VSS VDD_CORE
12 VSS VSS VDD_CORE VDD_CORE VSS VSS
11 VSS VDD_CORE VSS VSS VSS VDD_CORE
10 VDD_CORE VSS VSS VSS VSS VSS
9VSS VSS VSS VSS VDD_CORE VSS
8VSS VSS VSS VDD_CORE VDD_CORE VSS
7VDD_CORE VSS VSS VSS VDD_CORE VSS
6VDD_CORE VSS VSS VDD_CORE VDD_CORE VSS
5VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VPP
4DDR_RASn DDR_A14 DDR_VREF DDR_D12 DDR_D14 DDR_D1
3DDR_CKE DDR_A13 DDR_VTP DDR_D11 DDR_D13 DDR_D0
2DDR_RESETn DDR_CSn0 DDR_DQM1 DDR_D10 DDR_DQSn1 DDR_DQM0
1DDR_ODT DDR_A1 DDR_D8 DDR_D9 DDR_DQS1 DDR_D15
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Right
Pin map section location
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ZCZ Pin Map [Section Right - Top View]
N P R T U V
18 USB0_DM USB1_CE USB1_DM USB1_VBUS GPMC_BEn1 VSS
17 USB0_DP USB1_ID USB1_DP GPMC_WAIT0 GPMC_WPn GPMC_A11
16 VDDA1P8V_USB0 USB0_ID VDDA1P8V_USB1 GPMC_A10 GPMC_A9 GPMC_A8
15 VDDA3P3V_USB0 USB0_VBUS VDDA3P3V_USB1 GPMC_A7 GPMC_A6 GPMC_A5
14 VSSA_USB VDDS GPMC_A4 GPMC_A3 GPMC_A2 GPMC_A1
13 VDD_CORE VDDSHV3 GPMC_A0 GPMC_CSn3 GPMC_AD15 GPMC_AD14
12 VDD_CORE VDDSHV3 GPMC_AD13 GPMC_AD12 GPMC_AD11 GPMC_CLK
11 VSS VDDSHV2 VDDS_OSC GPMC_AD10 XTALOUT VSS_OSC
10 VSS VDDSHV2 VDDS_PLL_CORE_LCD GPMC_AD9 GPMC_AD8 XTALIN
9VDD_CORE VDDS GPMC_AD6 GPMC_AD7 GPMC_CSn1 GPMC_CSn2
8VDD_CORE VDDSHV1 GPMC_AD2 GPMC_AD3 GPMC_AD4 GPMC_AD5
7VSS VDDSHV1 GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD0 GPMC_AD1
6VDDS VDDSHV6 LCD_AC_BIAS_EN GPMC_BEn0_CLE GPMC_WEn GPMC_CSn0
5VDDSHV6 VDDSHV6 LCD_HSYNC LCD_DATA15 LCD_VSYNC LCD_PCLK
4DDR_D5 DDR_D7 LCD_DATA3 LCD_DATA7 LCD_DATA11 LCD_DATA14
3DDR_D4 DDR_D6 LCD_DATA2 LCD_DATA6 LCD_DATA10 LCD_DATA13
2DDR_D3 DDR_DQSn0 LCD_DATA1 LCD_DATA5 LCD_DATA9 LCD_DATA12
1DDR_D2 DDR_DQS0 LCD_DATA0 LCD_DATA4 LCD_DATA8 VSS
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4.2 Pin Attributes
The AM335x Sitara Processors Technical Reference Manual (SPRUH73) and this document may
reference internal signal names when discussing peripheral input and output signals since many of the
AM335x package terminals can be multiplexed to one of several peripheral signals. The following table
has a Pin Name column that lists all device terminal names and a Signal Name column that lists all
internal signal names multiplexed to each terminal which provides a cross reference of internal signal
names to terminal names. This table also identifies other important terminal characteristics.
1. BALL NUMBER: Package ball numbers associated with each signals.
2. PIN NAME: The name of the package pin or terminal.
Note: The table does not take into account subsystem terminal multiplexing options.
3. SIGNAL NAME: The signal name for that pin in the mode being used.
4. MODE: Multiplexing mode number.
(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the
terminal corresponds to the name of the terminal. There is always a function mapped on the
primary mode. Notice that primary mode is not necessarily the default mode.
Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE
column.
(b) Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are
effectively used for alternate functions, while some modes are not used and do not correspond to a
functional configuration.
5. TYPE: Signal direction
– I = Input
– O = Output
– I/O = Input and Output
– D = Open drain
– DS = Differential
– A = Analog
– PWR = Power
– GND = Ground
Note: In the safe_mode, the buffer is configured in high-impedance.
6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low.
– 0: The buffer drives VOL (pulldown or pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
– 1: The buffer drives VOH (pulldown or pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
– Z: High-impedance
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
7. BALL RESET REL. STATE: State of the terminal after the active low PWRONRSTn terminal
transitions from low to high.
– 0: The buffer drives VOL (pulldown or pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
– 1: The buffer drives VOH (pulldown or pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
– Z: High-impedance.
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
8. RESET REL. MODE: The mode is automatically configured after the active low PWRONRSTn terminal
transitions from low to high.
9. POWER: The voltage supply that powers the terminal’s IO buffers.
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10. HYS: Indicates if the input buffer is with hysteresis.
11. BUFFER STRENGTH: Drive strength of the associated output buffer.
12. PULLUP OR PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.
Pullup and pulldown resistors can be enabled or disabled via software.
13. IO CELL: IO cell information.
Note: Configuring two terminals to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration.
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Table 4-1. Pin Attributes (ZCE and ZCZ Packages)
BALL RESET BUFFER PULLUP
ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS
PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13]
NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10]
[7] (mA) [11] [12]
B8 B6 AIN0 AIN0 0 A (22) Z Z 0 VDDA_ADC / NA 25 NA Analog
VDDA_ADC
A11 C7 AIN1 AIN1 0 A (21) Z Z 0 VDDA_ADC / NA 25 NA Analog
VDDA_ADC
A8 B7 AIN2 AIN2 0 A (21) Z Z 0 VDDA_ADC / NA 25 NA Analog
VDDA_ADC
B11 A7 AIN3 AIN3 0 A (20) Z Z 0 VDDA_ADC / NA 25 NA Analog
VDDA_ADC
C8 C8 AIN4 AIN4 0 A (20) Z Z 0 VDDA_ADC / NA 25 NA Analog
VDDA_ADC
B12 B8 AIN5 AIN5 0 A Z Z 0 VDDA_ADC / NA NA NA Analog
VDDA_ADC
A10 A8 AIN6 AIN6 0 A Z Z 0 VDDA_ADC / NA NA NA Analog
VDDA_ADC
A12 C9 AIN7 AIN7 0 A Z Z 0 VDDA_ADC / NA NA NA Analog
VDDA_ADC
C13 C10 CAP_VBB_MPU CAP_VBB_MPU NA A
D6 D6 CAP_VDD_RTC CAP_VDD_RTC NA A
B10 D9 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A
D13 D11 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A
F3 F3 DDR_A0 ddr_a0 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
J2 H1 DDR_A1 ddr_a1 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
D1 E4 DDR_A2 ddr_a2 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
B3 C3 DDR_A3 ddr_a3 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
E5 C2 DDR_A4 ddr_a4 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
A2 B1 DDR_A5 ddr_a5 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
B1 D5 DDR_A6 ddr_a6 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
D2 E2 DDR_A7 ddr_a7 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
C3 D4 DDR_A8 ddr_a8 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
B2 C1 DDR_A9 ddr_a9 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
E2 F4 DDR_A10 ddr_a10 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
G4 F2 DDR_A11 ddr_a11 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/
VDDS_DDR HSTL
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