ARTERY AT32WB415 Series User manual

AT32WB415 Series Reference Manual
2022.04.13 Page 1 Ver 2.00
ARM®-based 32-bit Cortex®-M4 MCU with 256 KB Flash, sLib, USBFS, 11
timers, ADC, 2 COMPs, 6 communication interfaces
Feature
Wireless Bluetooth module
−Dual core Bluetooth® SIG specification 5.0 compliant
−2.4 GHz low-power transceiver
−Clocks: 16 MHz crystal oscillator, 64 MHz PLL,
interal 32 kHz clock
−Peripherals: 8 x GPIOs with 2-channel PWM, 2 x
UARTs (UART21 is connected to MCU USART3)
Core: ARM®32-bit Cortex®-M4F CPU
−150 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−DSP instructions
Memories
−256 KBytes of Flash memory
−18 Kbytes of boot code area used as a Bootloader
or as a general instruction/data memory (one-time-
configured)
−sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
−32 KBytes of SRAM
Power control (PWC)
−2.6 V ~ 3.6 V application suppy
−Power-on reset (POR)/ low-voltage reset (LVR), and
power voltage monitor (PVM)
−Low power: Sleep, Deepsleep, and Standby modes,
−VBAT supply for LEXT, ERTC and 42 x 16-bit battery
powered registers (BPR)
Clock and reset management (CRM)
−External master clock input
−Internal 48 MHz factory-trimmed clock (HICK),
accuracy 1% at TA=25 °C, 2.5 % at TA=-40 to
+105 °C, with automatic clock calibration (ACC)
−PLL with configurable frequency multiplication
(31~500) and division factor (1~15)
−32 kHz crystal oscillator (LEXT)
−Internal 40 kHz RC oscillator (LICK)
1 x 12-bit 0.5 μs A/D converter (up to 16 input
channels)
−Conversion range: 0 V to 3.6 V
−Sample and hold capability
−Temperature sensor
2 x COMP
DMA: 12-channel DMA controller
−Peripherals supported: timers, ADC, SPI, I2C and
USART
Debug mode
−Serial wire debug (SWD)
Fast I/O Interfaces
−All mappable to 16 external interrupt vectors
−Almost 5 V-tolerant
−All fast I/Os, registers accessible with fAHBspeed
Up to 11 Timers (TMR)
−6 x 16-bitand 1 x32-bit timers, each with 4 IC/OC/PWM
or pulse counter and quadrature (incremental) encoder
input
−2 x Watchdog timers (WDT and WWDT)
−SysTick timer: 24-bitdowncounter
ERTC: enhanced RTC
Up to 6 communication interfaces
−I2Cinterface (SMBus/PMBus)
−Up to3 x USARTs (ISO7816 interface, LIN, IrDA and
modem control)
−SPI interface
−CANinterface (2.0B Active)
−USB fullspeedinterface/host/OTGcontroller
−Infrared transmitter (IRTMR)
CRC Calculation Unit
96-bit ID (UID)
Packaging
−QFN48 7 x 7 mm
List of Models
Internal Flash
Model
256 KBytes
AT32WB415CCU7-7

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Contents
1System architecture...................................................................... 27
1.1 System overview..........................................................................29
1.1.1 ARM CortexTM-M4 processor........................................................ 29
1.1.2 Bit band...................................................................................... 29
1.1.3 Interrupt and exception vectors .................................................... 31
1.1.4 System Tick (SysTick) ................................................................. 34
1.1.5 Reset ......................................................................................... 34
1.2 List of abbreviations for registers ..................................................36
1.3 Device characteristics information.................................................36
1.3.1 Flash memory size register .......................................................... 36
1.3.2 Device electronic signature.......................................................... 36
2Memory resources ........................................................................ 37
2.1 Internal memory address map.......................................................37
2.2 Flash memory..............................................................................38
2.3 SRAM memory.............................................................................38
2.4 Peripheral address map................................................................38
3Power control (PWC)..................................................................... 41
3.1 Introduction .................................................................................41
3.2 Main Features .............................................................................41
3.3 POR/LVR ....................................................................................42
3.4 Power voltage monitor (PVM)........................................................42
3.5 Power domain..............................................................................43
3.6 Power saving modes ....................................................................43
3.7 PWC registers .............................................................................45
3.7.1 Power control register (PWC_CTRL) ............................................ 45
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 45
4Clock and reset manage (CRM) ..................................................... 47
4.1 Clock ..........................................................................................47
4.1.1 Clock sources ............................................................................. 47

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4.1.2 System clock............................................................................... 48
4.1.3 Peripheral clock .......................................................................... 48
4.1.4 Clock fail detector ....................................................................... 48
4.1.5 Auto step-by-step system clock switch.......................................... 48
4.1.6 Internal clock output.................................................................... 49
4.1.7 Interrupts.................................................................................... 49
4.2 Reset..........................................................................................49
4.2.1 System reset............................................................................... 49
4.2.2 Battery powered domain reset...................................................... 49
4.3 CRM registers .............................................................................50
4.3.1 Clock control register (CRM_CTRL).............................................. 50
4.3.2 Clock configuration register (CRM_CFG) ...................................... 51
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 53
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 54
4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) ........................ 55
4.3.6 APB peripheral clock enable register (CRM_AHBEN)..................... 55
4.3.7 APB2 peripheral clock enable register (CRM_AHB2EN) ................. 56
4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN)................. 57
4.3.9 Battery powered domain control register (CRM_BPDC).................. 58
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 58
4.3.11 APB peripheral reset register (CRM_APBRST).............................. 59
4.3.12 PLL configuration register (CRM_PLL).......................................... 59
4.3.13 Additional register (CRM_MISC1)................................................. 60
4.3.14 OTG_FS extended control register (CRM_OTG_EXTCTRL)............ 60
4.3.15 Additional register (CRM_MISC2)................................................. 60
5Flash memory controller (FLASH)................................................. 62
5.1 FLASH introduction......................................................................62
5.2 Flash memory operation ...............................................................63
5.2.1 Unlock/lock ................................................................................. 63
5.2.2 Erase operation........................................................................... 64
5.2.3 Programming operation................................................................ 66
5.2.4 Read operation ........................................................................... 67
5.3 Main Flash memory extension area ...............................................67
5.4 User system data area ................................................................. 67

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5.4.1 Unlock/lock ................................................................................. 67
5.4.2 Erase operation........................................................................... 67
5.4.3 Programming operation................................................................ 68
5.4.4 Read operation ........................................................................... 70
5.5 Flash memory protection ..............................................................70
5.5.1 Access protection........................................................................ 70
5.5.2 Erase/program protection............................................................. 70
5.6 Special functions .........................................................................71
5.6.1 Security library settings ............................................................... 71
5.6.2 Bootloader code area used as Flash memory extension................. 72
5.6.3 CRC verify .................................................................................. 72
5.7 Flash memory registers ................................................................73
5.7.1 Flash performance select register (FLASH_PSR) .......................... 73
5.7.2 Flash unlock register (FLASH_UNLOCK) ...................................... 74
5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 74
5.7.4 Flash status register (FLASH_STS) .............................................. 74
5.7.5 Flash control register (FLASH_CTRL)........................................... 74
5.7.6 Flash address register (FLASH_ADDR) ........................................ 75
5.7.7 User system data register (FLASH_USD)...................................... 75
5.7.8 Erase/program protection status register (FLASH_EPPS) .............. 76
5.7.9 Flash security library status register0 (SLIB_STS0)....................... 76
5.7.10 Flash security library status register1 (SLIB_STS1)....................... 76
5.7.11 Security library password clear register (SLIB_PWD_CLR) ............ 77
5.7.12 Security library additional status register (SLIB_MISC_STS).......... 77
5.7.13 Flash CRC address register (FLASH_CRC_ARR) .......................... 77
5.7.14 Flash CRC control register (FLASH_CRC_CTRL) .......................... 77
5.7.15 Flash CRC check result register (FLASH_CRC_CHKR).................. 78
5.7.16 Security library password setting register (SLIB_SET_PWD).......... 78
5.7.17 Security library address setting register (SLIB_SET_RANGE) ........ 78
5.7.18 Flash extension memory security library setting register
(EM_SLIB_SET).................................................................................... 79
5.7.19 Boot mode setting register (BTM_MODE_SET) ............................. 79
5.7.20 Security library unlock register (FLASH_UNLOCK) ........................ 79
6General-purpose I/Os (GPIOs)....................................................... 80

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6.1 Introduction .................................................................................80
6.2 Functional overview .....................................................................80
6.2.1 GPIO structure............................................................................ 80
6.2.2 GPIO reset status........................................................................ 80
6.2.3 General-purpose input configuration............................................. 81
6.2.4 Analog input/output configuration ................................................. 81
6.2.5 General-purpose output configuration........................................... 81
6.2.6 GPIO port protection ................................................................... 81
6.3 GPIO registers.............................................................................81
6.3.1 GPIO configuration register low (GPIOx_CFGLR) (x=A…F) ............ 82
6.3.2 GPIO configuration register high (GPIOx_CFGHR) (x=A…F) .......... 82
6.3.3 GPIO input register (GPIOx_IDT) (x=A…F) ................................... 82
6.3.4 GPIO output register (GPIOx_ODT) (x= A…F) ............................... 83
6.3.5 GPIO set/clear register (GPIOx_SCR) (x=A…F) ............................ 83
6.3.6 GPIO bit clear register (GPIOx_CLR) (x=A…F) ............................. 83
6.3.7 GPIO write protection register (GPIOx_WPR) (x=A…F) ................. 83
7Multiplexed function I/Os (IOMUX) ................................................ 84
7.1 Introduction .................................................................................84
7.2 Functional overview .....................................................................84
7.2.1 IOMUX structure ......................................................................... 84
7.2.2 MUX Input configuration .............................................................. 85
7.2.3 MUX output or bidirectional MUX configuration ............................. 85
7.2.4 Peripheral MUX function configuration.......................................... 85
7.2.5 IOMUX map priority ..................................................................... 85
7.2.5.1 Hardware preemption .............................................................. 86
7.2.5.2 Debug port priority .................................................................. 86
7.2.5.3 Other peripheral output priority ................................................ 86
7.2.6 External interrupt/wake-up lines ................................................... 86
7.3 IOMUX registers ..........................................................................87
7.3.1 Event output control register (IOMUX_EVTOUT) ........................... 87
7.3.2 IOMUX remap register (IOMUX_REMAP) ...................................... 88
7.3.3 IOMUX external interrupt configuration register1 (IOMUX_EXINTC1)89
7.3.4 IOMUX external interrupt configuration register2 (IOMUX_EXINTC2)90
7.3.5 IOMUX external interrupt configuration register3 (IOMUX_EXINTC3)91

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7.3.6 IOMUX external interrupt configuration register4 (IOMUX_EXINTC4)92
7.3.7 IOMUX remap register2 (IOMUX_REMAP2) .................................. 92
7.3.8 IOMUX remap register3 (IOMUX_REMAP3) .................................. 93
7.3.9 IOMUX remap register4 (IOMUX_REMAP4) .................................. 93
7.3.10 IOMUX remap register5 (IOMUX_REMAP5) .................................. 94
7.3.11 IOMUX remap register6 (IOMUX_REMAP6) .................................. 94
7.3.12 IOMUX remap register7 (IOMUX_REMAP7) .................................. 95
7.3.13 IOMUX remap register8 (IOMUX_REMAP8) .................................. 96
8External interrupt/Event controller (EXINT) .................................. 97
8.1 EXINT introduction.......................................................................97
8.2 Function overview and configuration procedure ..............................97
8.3 EXINT registers ...........................................................................98
8.3.1 Interrupt enable register (EXINT_INTEN)...................................... 98
8.3.2 Event enable register (EXINT_EVTEN) ......................................... 98
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1)...................... 98
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2)...................... 99
8.3.5 Software trigger register (EXINT_ SWTRG)................................... 99
8.3.6 Interrupt status register (EXINT_ INTSTS) .................................... 99
9DMA controller (DMA) ................................................................. 100
9.1 Introduction ............................................................................... 100
9.2 Main features ............................................................................ 100
9.3 Function overview...................................................................... 101
9.3.1 DMA configuration......................................................................101
9.3.2 Handshake mechanism...............................................................101
9.3.3 Arbiter .......................................................................................101
9.3.4 Programmable data transfer width ...............................................102
9.3.5 Errors ........................................................................................103
9.3.6 Interrupts...................................................................................103
9.3.7 Fixed DMA request mapping .......................................................103
9.3.8 Flexible DMA request mapping....................................................103
9.4 DMA registers............................................................................ 105
9.4.1 DMA interrupt status register (DMA_STS) ....................................106
9.4.2 DMA interrupt flag clear register (DMA_CLR) ...............................107

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9.4.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…7) ..109
9.4.4 DMA channel-x number of data register (DMA_CxDTCNT) (x = 1…7)110
9.4.5 DMA channel-x peripheral address register (DMA_CxPADDR)
(x = 1…7) ............................................................................................110
9.4.6 DMA channel-x memory address register (DMA_CxMADDR) (x = 1…7)111
9.4.7 DMA channel source register (DMA_SRC_SEL0)..........................111
9.4.8 DMA channel source register1 (DMA_SRC_SEL1)........................111
10 CRC calculation unit (CRC)......................................................... 112
10.1 CRC introduction ....................................................................... 112
10.2 CRC registers............................................................................ 112
10.2.1 Data register (CRC_DT)..............................................................112
10.2.2 Common data register (CRC_CDT)..............................................112
10.2.3 Control register (CRC_CTRL)......................................................113
10.2.4 Initialization register (CRC_IDT) .................................................113
11 I2C interface ................................................................................ 114
11.1 I2C introduction.......................................................................... 114
11.2 I2C main features....................................................................... 114
11.3 I2C function overview ................................................................. 114
11.4 I2C interface .............................................................................. 115
11.4.1 I2C slave communication flow......................................................117
11.4.2 I2C master communication flow ...................................................118
11.4.3 Data transfer using DMA.............................................................124
11.4.4 SMBus.......................................................................................125
11.4.5 I2C interrupt requests .................................................................127
11.4.6 I2C debug mode .........................................................................127
11.5 I2C registers .............................................................................. 127
11.5.1 Control register1 (I2C_CTRL1)....................................................128
11.5.2 Control register2 (I2C_CTRL2)....................................................129
11.5.3 Own address register1 (I2C_OADDR1) ........................................130
11.5.4 Own address register2 (I2C_OADDR2) ........................................130
11.5.5 Data register (I2C_DT) ...............................................................130
11.5.6 Status register1 (I2C_STS1) .......................................................131
11.5.7 Status register2 (I2C_STS2) .......................................................133

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11.5.8 Clock control register (I2C_ CLKCTRL) .......................................133
12 Universal synchronous/asynchronous receiver/transmitter (USART)135
12.1 USART introduction ................................................................... 135
12.2 Full-duplex/half-duplex selector .................................................. 137
12.3 Mode selector............................................................................ 137
12.3.1 Introduction................................................................................137
12.3.2 Configuration procedure .............................................................137
12.4 USART frame format and configuration........................................ 138
12.5 DMA transfer introduction........................................................... 138
12.5.1 Transmission using DMA ............................................................138
12.5.2 Reception using DMA .................................................................138
12.6 Baud rate generation.................................................................. 139
12.6.1 Introduction................................................................................139
12.6.2 Configuration .............................................................................139
12.7 Transmitter................................................................................ 139
12.7.1 Transmitter introduction..............................................................139
12.7.2 Transmitter configuration ............................................................139
12.8 Receiver ................................................................................... 140
12.8.1 Receiver introduction..................................................................140
12.8.2 Receiver configuration................................................................140
12.8.3 Start bit and noise detection .......................................................141
12.9 Interrupt requests ...................................................................... 142
12.10I/O pin control............................................................................ 142
12.11USART registers........................................................................ 143
12.11.1 Status register (USART_STS) ..................................................143
12.11.2 Data register (USART_DT).......................................................144
12.11.3 Baud rate register (USART_BAUDR) ........................................144
12.11.4 Control register1 (USART_CTRL1) ...........................................144
12.11.5 Control register2 (USART_CTRL2) ...........................................146
12.11.6 Control register3 (USART_CTRL3) ...........................................147
12.11.7 Guard time and divider register (USART_GDIV) ........................148
13 Serial peripheral interface (SPI).................................................. 149
13.1 SPI introduction......................................................................... 149

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13.2 Functional overview ................................................................... 149
13.2.1 SPI description...........................................................................149
13.2.2 Full-duplex/half-duplex selector ..................................................150
13.2.3 Chip select controller..................................................................152
13.2.4 SPI_SCK controller ....................................................................152
13.2.5 CRC ..........................................................................................152
13.2.6 DMA transfer..............................................................................153
13.2.7 Transmitter ................................................................................154
13.2.8 Receiver ....................................................................................154
13.2.9 Motorola mode ...........................................................................155
13.2.10 Interrupts ................................................................................157
13.2.11 IO pin control ..........................................................................158
13.2.12 Precautions.............................................................................158
13.3 SPI registers ............................................................................. 158
13.3.1 SPI control register1 (SPI_CTRL1) ..............................................158
13.3.2 SPI control register2 (SPI_CTRL2) ..............................................159
13.3.3 SPI status register (SPI_STS) .....................................................160
13.3.4 SPI data register (SPI_DT) .........................................................160
13.3.5 SPICRC register (SPI_CPOLY) ...................................................161
13.3.6 SPIRxCRC register (SPI_RCRC) .................................................161
13.3.7 SPITxCRC register (SPI_TCRC)..................................................161
14 Timer .......................................................................................... 162
14.1 General-purpose timer (TMR2 to TMR5) ...................................... 162
14.1.1 TMRx introduction ......................................................................162
14.1.2 TMRx main features ...................................................................163
14.1.3 TMRx functional overview ...........................................................163
14.1.3.1 Count clock .......................................................................... 163
14.1.3.2 Counting mode ..................................................................... 165
14.1.3.3 TMR input function................................................................ 167
14.1.3.4 TMR output function.............................................................. 168
14.1.3.5 TMR synchronization............................................................. 170
14.1.3.6 Debug mode ......................................................................... 173
14.1.4 TMRx registers...........................................................................173
14.1.4.1 Control register1 (TMRx_CTRL1) ........................................... 174
14.1.4.2 Control register2 (TMRx_CTRL2) ........................................... 175

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14.1.4.3 Slave timer control register (TMRx_STCTRL) .......................... 175
14.1.4.4 DMA/interrupt enable register (TMRx_IDEN) ........................... 176
14.1.4.5 Interrupt status register (TMRx_ISTS) .................................... 177
14.1.4.6 Software event register (TMRx_SWEVT) ................................. 178
14.1.4.7 Channel mode register1 (TMRx_CM1) .................................... 178
14.1.4.8 Channel mode register2 (TMRx_CM2) .................................... 180
14.1.4.9 Channel control register (TMRx_CCTRL) ................................ 181
14.1.4.10 Counter value (TMRx_CVAL) ............................................... 182
14.1.4.11 Division value (TMRx_DIV) .................................................. 182
14.1.4.12 Period register (TMRx_PR) .................................................. 182
14.1.4.13 Channel 1 data register (TMRx_C1DT).................................. 182
14.1.4.14 Channel 2 data register (TMRx_C2DT).................................. 182
14.1.4.15 Channel 3 data register (TMRx_C3DT).................................. 183
14.1.4.16 Channel 4 data register (TMRx_C4DT).................................. 183
14.1.4.17 DMA control register (TMRx_DMACTRL) ............................... 183
14.1.4.18 DMA data register (TMRx_DMADT)....................................... 183
14.2 General-purpose timer (TMR9 to TMR11) .................................... 184
14.2.1 TMRx introduction ......................................................................184
14.2.2 TMRx main features ...................................................................184
14.2.2.1 TMR9 main features .............................................................. 184
14.2.2.2 TMR10 and TMR11 main features .......................................... 184
14.2.3 TMRx functional overview ...........................................................185
14.2.3.1 Count clock .......................................................................... 185
14.2.3.2 Counting mode ..................................................................... 186
14.2.3.3 TMR input function................................................................ 187
14.2.3.4 TMR output function.............................................................. 188
14.2.3.5 TMR synchronization............................................................. 189
14.2.3.6 Debug mode ......................................................................... 190
14.2.4 TMR9 registers ..........................................................................191
14.2.4.1 Control register1 (TMR9_CTRL1) ........................................... 191
14.2.4.2 Slave timer control register (TMR9_STCTRL) .......................... 192
14.2.4.3 DMA/interrupt enable register (TMR9_IDEN) ........................... 192
14.2.4.4 Interrupt status register (TMR9_ISTS) .................................... 193
14.2.4.5 Software event register (TMR9_SWEVT)................................. 194
14.2.4.6 Channel mode register1 (TMR9_CM1) .................................... 194
14.2.4.7 Channel control register (TMR9_CCTRL) ................................ 196
14.2.4.8 Counter value (TMR9_CVAL) ................................................. 197
14.2.4.9 Division value (TMR9_DIV) .................................................... 197