ARTERY AT32WB415 Series User manual

AT32WB415 Series Reference Manual
2022.04.13 Page 1 Ver 2.00
ARM®-based 32-bit Cortex®-M4 MCU with 256 KB Flash, sLib, USBFS, 11
timers, ADC, 2 COMPs, 6 communication interfaces
Feature
Wireless Bluetooth module
−Dual core Bluetooth® SIG specification 5.0 compliant
−2.4 GHz low-power transceiver
−Clocks: 16 MHz crystal oscillator, 64 MHz PLL,
interal 32 kHz clock
−Peripherals: 8 x GPIOs with 2-channel PWM, 2 x
UARTs (UART21 is connected to MCU USART3)
Core: ARM®32-bit Cortex®-M4F CPU
−150 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−DSP instructions
Memories
−256 KBytes of Flash memory
−18 Kbytes of boot code area used as a Bootloader
or as a general instruction/data memory (one-time-
configured)
−sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
−32 KBytes of SRAM
Power control (PWC)
−2.6 V ~ 3.6 V application suppy
−Power-on reset (POR)/ low-voltage reset (LVR), and
power voltage monitor (PVM)
−Low power: Sleep, Deepsleep, and Standby modes,
−VBAT supply for LEXT, ERTC and 42 x 16-bit battery
powered registers (BPR)
Clock and reset management (CRM)
−External master clock input
−Internal 48 MHz factory-trimmed clock (HICK),
accuracy 1% at TA=25 °C, 2.5 % at TA=-40 to
+105 °C, with automatic clock calibration (ACC)
−PLL with configurable frequency multiplication
(31~500) and division factor (1~15)
−32 kHz crystal oscillator (LEXT)
−Internal 40 kHz RC oscillator (LICK)
1 x 12-bit 0.5 μs A/D converter (up to 16 input
channels)
−Conversion range: 0 V to 3.6 V
−Sample and hold capability
−Temperature sensor
2 x COMP
DMA: 12-channel DMA controller
−Peripherals supported: timers, ADC, SPI, I2C and
USART
Debug mode
−Serial wire debug (SWD)
Fast I/O Interfaces
−All mappable to 16 external interrupt vectors
−Almost 5 V-tolerant
−All fast I/Os, registers accessible with fAHBspeed
Up to 11 Timers (TMR)
−6 x 16-bitand 1 x32-bit timers, each with 4 IC/OC/PWM
or pulse counter and quadrature (incremental) encoder
input
−2 x Watchdog timers (WDT and WWDT)
−SysTick timer: 24-bitdowncounter
ERTC: enhanced RTC
Up to 6 communication interfaces
−I2Cinterface (SMBus/PMBus)
−Up to3 x USARTs (ISO7816 interface, LIN, IrDA and
modem control)
−SPI interface
−CANinterface (2.0B Active)
−USB fullspeedinterface/host/OTGcontroller
−Infrared transmitter (IRTMR)
CRC Calculation Unit
96-bit ID (UID)
Packaging
−QFN48 7 x 7 mm
List of Models
Internal Flash
Model
256 KBytes
AT32WB415CCU7-7

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Contents
1System architecture...................................................................... 27
1.1 System overview..........................................................................29
1.1.1 ARM CortexTM-M4 processor........................................................ 29
1.1.2 Bit band...................................................................................... 29
1.1.3 Interrupt and exception vectors .................................................... 31
1.1.4 System Tick (SysTick) ................................................................. 34
1.1.5 Reset ......................................................................................... 34
1.2 List of abbreviations for registers ..................................................36
1.3 Device characteristics information.................................................36
1.3.1 Flash memory size register .......................................................... 36
1.3.2 Device electronic signature.......................................................... 36
2Memory resources ........................................................................ 37
2.1 Internal memory address map.......................................................37
2.2 Flash memory..............................................................................38
2.3 SRAM memory.............................................................................38
2.4 Peripheral address map................................................................38
3Power control (PWC)..................................................................... 41
3.1 Introduction .................................................................................41
3.2 Main Features .............................................................................41
3.3 POR/LVR ....................................................................................42
3.4 Power voltage monitor (PVM)........................................................42
3.5 Power domain..............................................................................43
3.6 Power saving modes ....................................................................43
3.7 PWC registers .............................................................................45
3.7.1 Power control register (PWC_CTRL) ............................................ 45
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 45
4Clock and reset manage (CRM) ..................................................... 47
4.1 Clock ..........................................................................................47
4.1.1 Clock sources ............................................................................. 47

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4.1.2 System clock............................................................................... 48
4.1.3 Peripheral clock .......................................................................... 48
4.1.4 Clock fail detector ....................................................................... 48
4.1.5 Auto step-by-step system clock switch.......................................... 48
4.1.6 Internal clock output.................................................................... 49
4.1.7 Interrupts.................................................................................... 49
4.2 Reset..........................................................................................49
4.2.1 System reset............................................................................... 49
4.2.2 Battery powered domain reset...................................................... 49
4.3 CRM registers .............................................................................50
4.3.1 Clock control register (CRM_CTRL).............................................. 50
4.3.2 Clock configuration register (CRM_CFG) ...................................... 51
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 53
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 54
4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) ........................ 55
4.3.6 APB peripheral clock enable register (CRM_AHBEN)..................... 55
4.3.7 APB2 peripheral clock enable register (CRM_AHB2EN) ................. 56
4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN)................. 57
4.3.9 Battery powered domain control register (CRM_BPDC).................. 58
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 58
4.3.11 APB peripheral reset register (CRM_APBRST).............................. 59
4.3.12 PLL configuration register (CRM_PLL).......................................... 59
4.3.13 Additional register (CRM_MISC1)................................................. 60
4.3.14 OTG_FS extended control register (CRM_OTG_EXTCTRL)............ 60
4.3.15 Additional register (CRM_MISC2)................................................. 60
5Flash memory controller (FLASH)................................................. 62
5.1 FLASH introduction......................................................................62
5.2 Flash memory operation ...............................................................63
5.2.1 Unlock/lock ................................................................................. 63
5.2.2 Erase operation........................................................................... 64
5.2.3 Programming operation................................................................ 66
5.2.4 Read operation ........................................................................... 67
5.3 Main Flash memory extension area ...............................................67
5.4 User system data area ................................................................. 67

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5.4.1 Unlock/lock ................................................................................. 67
5.4.2 Erase operation........................................................................... 67
5.4.3 Programming operation................................................................ 68
5.4.4 Read operation ........................................................................... 70
5.5 Flash memory protection ..............................................................70
5.5.1 Access protection........................................................................ 70
5.5.2 Erase/program protection............................................................. 70
5.6 Special functions .........................................................................71
5.6.1 Security library settings ............................................................... 71
5.6.2 Bootloader code area used as Flash memory extension................. 72
5.6.3 CRC verify .................................................................................. 72
5.7 Flash memory registers ................................................................73
5.7.1 Flash performance select register (FLASH_PSR) .......................... 73
5.7.2 Flash unlock register (FLASH_UNLOCK) ...................................... 74
5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 74
5.7.4 Flash status register (FLASH_STS) .............................................. 74
5.7.5 Flash control register (FLASH_CTRL)........................................... 74
5.7.6 Flash address register (FLASH_ADDR) ........................................ 75
5.7.7 User system data register (FLASH_USD)...................................... 75
5.7.8 Erase/program protection status register (FLASH_EPPS) .............. 76
5.7.9 Flash security library status register0 (SLIB_STS0)....................... 76
5.7.10 Flash security library status register1 (SLIB_STS1)....................... 76
5.7.11 Security library password clear register (SLIB_PWD_CLR) ............ 77
5.7.12 Security library additional status register (SLIB_MISC_STS).......... 77
5.7.13 Flash CRC address register (FLASH_CRC_ARR) .......................... 77
5.7.14 Flash CRC control register (FLASH_CRC_CTRL) .......................... 77
5.7.15 Flash CRC check result register (FLASH_CRC_CHKR).................. 78
5.7.16 Security library password setting register (SLIB_SET_PWD).......... 78
5.7.17 Security library address setting register (SLIB_SET_RANGE) ........ 78
5.7.18 Flash extension memory security library setting register
(EM_SLIB_SET).................................................................................... 79
5.7.19 Boot mode setting register (BTM_MODE_SET) ............................. 79
5.7.20 Security library unlock register (FLASH_UNLOCK) ........................ 79
6General-purpose I/Os (GPIOs)....................................................... 80

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6.1 Introduction .................................................................................80
6.2 Functional overview .....................................................................80
6.2.1 GPIO structure............................................................................ 80
6.2.2 GPIO reset status........................................................................ 80
6.2.3 General-purpose input configuration............................................. 81
6.2.4 Analog input/output configuration ................................................. 81
6.2.5 General-purpose output configuration........................................... 81
6.2.6 GPIO port protection ................................................................... 81
6.3 GPIO registers.............................................................................81
6.3.1 GPIO configuration register low (GPIOx_CFGLR) (x=A…F) ............ 82
6.3.2 GPIO configuration register high (GPIOx_CFGHR) (x=A…F) .......... 82
6.3.3 GPIO input register (GPIOx_IDT) (x=A…F) ................................... 82
6.3.4 GPIO output register (GPIOx_ODT) (x= A…F) ............................... 83
6.3.5 GPIO set/clear register (GPIOx_SCR) (x=A…F) ............................ 83
6.3.6 GPIO bit clear register (GPIOx_CLR) (x=A…F) ............................. 83
6.3.7 GPIO write protection register (GPIOx_WPR) (x=A…F) ................. 83
7Multiplexed function I/Os (IOMUX) ................................................ 84
7.1 Introduction .................................................................................84
7.2 Functional overview .....................................................................84
7.2.1 IOMUX structure ......................................................................... 84
7.2.2 MUX Input configuration .............................................................. 85
7.2.3 MUX output or bidirectional MUX configuration ............................. 85
7.2.4 Peripheral MUX function configuration.......................................... 85
7.2.5 IOMUX map priority ..................................................................... 85
7.2.5.1 Hardware preemption .............................................................. 86
7.2.5.2 Debug port priority .................................................................. 86
7.2.5.3 Other peripheral output priority ................................................ 86
7.2.6 External interrupt/wake-up lines ................................................... 86
7.3 IOMUX registers ..........................................................................87
7.3.1 Event output control register (IOMUX_EVTOUT) ........................... 87
7.3.2 IOMUX remap register (IOMUX_REMAP) ...................................... 88
7.3.3 IOMUX external interrupt configuration register1 (IOMUX_EXINTC1)89
7.3.4 IOMUX external interrupt configuration register2 (IOMUX_EXINTC2)90
7.3.5 IOMUX external interrupt configuration register3 (IOMUX_EXINTC3)91

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7.3.6 IOMUX external interrupt configuration register4 (IOMUX_EXINTC4)92
7.3.7 IOMUX remap register2 (IOMUX_REMAP2) .................................. 92
7.3.8 IOMUX remap register3 (IOMUX_REMAP3) .................................. 93
7.3.9 IOMUX remap register4 (IOMUX_REMAP4) .................................. 93
7.3.10 IOMUX remap register5 (IOMUX_REMAP5) .................................. 94
7.3.11 IOMUX remap register6 (IOMUX_REMAP6) .................................. 94
7.3.12 IOMUX remap register7 (IOMUX_REMAP7) .................................. 95
7.3.13 IOMUX remap register8 (IOMUX_REMAP8) .................................. 96
8External interrupt/Event controller (EXINT) .................................. 97
8.1 EXINT introduction.......................................................................97
8.2 Function overview and configuration procedure ..............................97
8.3 EXINT registers ...........................................................................98
8.3.1 Interrupt enable register (EXINT_INTEN)...................................... 98
8.3.2 Event enable register (EXINT_EVTEN) ......................................... 98
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1)...................... 98
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2)...................... 99
8.3.5 Software trigger register (EXINT_ SWTRG)................................... 99
8.3.6 Interrupt status register (EXINT_ INTSTS) .................................... 99
9DMA controller (DMA) ................................................................. 100
9.1 Introduction ............................................................................... 100
9.2 Main features ............................................................................ 100
9.3 Function overview...................................................................... 101
9.3.1 DMA configuration......................................................................101
9.3.2 Handshake mechanism...............................................................101
9.3.3 Arbiter .......................................................................................101
9.3.4 Programmable data transfer width ...............................................102
9.3.5 Errors ........................................................................................103
9.3.6 Interrupts...................................................................................103
9.3.7 Fixed DMA request mapping .......................................................103
9.3.8 Flexible DMA request mapping....................................................103
9.4 DMA registers............................................................................ 105
9.4.1 DMA interrupt status register (DMA_STS) ....................................106
9.4.2 DMA interrupt flag clear register (DMA_CLR) ...............................107

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9.4.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…7) ..109
9.4.4 DMA channel-x number of data register (DMA_CxDTCNT) (x = 1…7)110
9.4.5 DMA channel-x peripheral address register (DMA_CxPADDR)
(x = 1…7) ............................................................................................110
9.4.6 DMA channel-x memory address register (DMA_CxMADDR) (x = 1…7)111
9.4.7 DMA channel source register (DMA_SRC_SEL0)..........................111
9.4.8 DMA channel source register1 (DMA_SRC_SEL1)........................111
10 CRC calculation unit (CRC)......................................................... 112
10.1 CRC introduction ....................................................................... 112
10.2 CRC registers............................................................................ 112
10.2.1 Data register (CRC_DT)..............................................................112
10.2.2 Common data register (CRC_CDT)..............................................112
10.2.3 Control register (CRC_CTRL)......................................................113
10.2.4 Initialization register (CRC_IDT) .................................................113
11 I2C interface ................................................................................ 114
11.1 I2C introduction.......................................................................... 114
11.2 I2C main features....................................................................... 114
11.3 I2C function overview ................................................................. 114
11.4 I2C interface .............................................................................. 115
11.4.1 I2C slave communication flow......................................................117
11.4.2 I2C master communication flow ...................................................118
11.4.3 Data transfer using DMA.............................................................124
11.4.4 SMBus.......................................................................................125
11.4.5 I2C interrupt requests .................................................................127
11.4.6 I2C debug mode .........................................................................127
11.5 I2C registers .............................................................................. 127
11.5.1 Control register1 (I2C_CTRL1)....................................................128
11.5.2 Control register2 (I2C_CTRL2)....................................................129
11.5.3 Own address register1 (I2C_OADDR1) ........................................130
11.5.4 Own address register2 (I2C_OADDR2) ........................................130
11.5.5 Data register (I2C_DT) ...............................................................130
11.5.6 Status register1 (I2C_STS1) .......................................................131
11.5.7 Status register2 (I2C_STS2) .......................................................133

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11.5.8 Clock control register (I2C_ CLKCTRL) .......................................133
12 Universal synchronous/asynchronous receiver/transmitter (USART)135
12.1 USART introduction ................................................................... 135
12.2 Full-duplex/half-duplex selector .................................................. 137
12.3 Mode selector............................................................................ 137
12.3.1 Introduction................................................................................137
12.3.2 Configuration procedure .............................................................137
12.4 USART frame format and configuration........................................ 138
12.5 DMA transfer introduction........................................................... 138
12.5.1 Transmission using DMA ............................................................138
12.5.2 Reception using DMA .................................................................138
12.6 Baud rate generation.................................................................. 139
12.6.1 Introduction................................................................................139
12.6.2 Configuration .............................................................................139
12.7 Transmitter................................................................................ 139
12.7.1 Transmitter introduction..............................................................139
12.7.2 Transmitter configuration ............................................................139
12.8 Receiver ................................................................................... 140
12.8.1 Receiver introduction..................................................................140
12.8.2 Receiver configuration................................................................140
12.8.3 Start bit and noise detection .......................................................141
12.9 Interrupt requests ...................................................................... 142
12.10I/O pin control............................................................................ 142
12.11USART registers........................................................................ 143
12.11.1 Status register (USART_STS) ..................................................143
12.11.2 Data register (USART_DT).......................................................144
12.11.3 Baud rate register (USART_BAUDR) ........................................144
12.11.4 Control register1 (USART_CTRL1) ...........................................144
12.11.5 Control register2 (USART_CTRL2) ...........................................146
12.11.6 Control register3 (USART_CTRL3) ...........................................147
12.11.7 Guard time and divider register (USART_GDIV) ........................148
13 Serial peripheral interface (SPI).................................................. 149
13.1 SPI introduction......................................................................... 149

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13.2 Functional overview ................................................................... 149
13.2.1 SPI description...........................................................................149
13.2.2 Full-duplex/half-duplex selector ..................................................150
13.2.3 Chip select controller..................................................................152
13.2.4 SPI_SCK controller ....................................................................152
13.2.5 CRC ..........................................................................................152
13.2.6 DMA transfer..............................................................................153
13.2.7 Transmitter ................................................................................154
13.2.8 Receiver ....................................................................................154
13.2.9 Motorola mode ...........................................................................155
13.2.10 Interrupts ................................................................................157
13.2.11 IO pin control ..........................................................................158
13.2.12 Precautions.............................................................................158
13.3 SPI registers ............................................................................. 158
13.3.1 SPI control register1 (SPI_CTRL1) ..............................................158
13.3.2 SPI control register2 (SPI_CTRL2) ..............................................159
13.3.3 SPI status register (SPI_STS) .....................................................160
13.3.4 SPI data register (SPI_DT) .........................................................160
13.3.5 SPICRC register (SPI_CPOLY) ...................................................161
13.3.6 SPIRxCRC register (SPI_RCRC) .................................................161
13.3.7 SPITxCRC register (SPI_TCRC)..................................................161
14 Timer .......................................................................................... 162
14.1 General-purpose timer (TMR2 to TMR5) ...................................... 162
14.1.1 TMRx introduction ......................................................................162
14.1.2 TMRx main features ...................................................................163
14.1.3 TMRx functional overview ...........................................................163
14.1.3.1 Count clock .......................................................................... 163
14.1.3.2 Counting mode ..................................................................... 165
14.1.3.3 TMR input function................................................................ 167
14.1.3.4 TMR output function.............................................................. 168
14.1.3.5 TMR synchronization............................................................. 170
14.1.3.6 Debug mode ......................................................................... 173
14.1.4 TMRx registers...........................................................................173
14.1.4.1 Control register1 (TMRx_CTRL1) ........................................... 174
14.1.4.2 Control register2 (TMRx_CTRL2) ........................................... 175

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14.1.4.3 Slave timer control register (TMRx_STCTRL) .......................... 175
14.1.4.4 DMA/interrupt enable register (TMRx_IDEN) ........................... 176
14.1.4.5 Interrupt status register (TMRx_ISTS) .................................... 177
14.1.4.6 Software event register (TMRx_SWEVT) ................................. 178
14.1.4.7 Channel mode register1 (TMRx_CM1) .................................... 178
14.1.4.8 Channel mode register2 (TMRx_CM2) .................................... 180
14.1.4.9 Channel control register (TMRx_CCTRL) ................................ 181
14.1.4.10 Counter value (TMRx_CVAL) ............................................... 182
14.1.4.11 Division value (TMRx_DIV) .................................................. 182
14.1.4.12 Period register (TMRx_PR) .................................................. 182
14.1.4.13 Channel 1 data register (TMRx_C1DT).................................. 182
14.1.4.14 Channel 2 data register (TMRx_C2DT).................................. 182
14.1.4.15 Channel 3 data register (TMRx_C3DT).................................. 183
14.1.4.16 Channel 4 data register (TMRx_C4DT).................................. 183
14.1.4.17 DMA control register (TMRx_DMACTRL) ............................... 183
14.1.4.18 DMA data register (TMRx_DMADT)....................................... 183
14.2 General-purpose timer (TMR9 to TMR11) .................................... 184
14.2.1 TMRx introduction ......................................................................184
14.2.2 TMRx main features ...................................................................184
14.2.2.1 TMR9 main features .............................................................. 184
14.2.2.2 TMR10 and TMR11 main features .......................................... 184
14.2.3 TMRx functional overview ...........................................................185
14.2.3.1 Count clock .......................................................................... 185
14.2.3.2 Counting mode ..................................................................... 186
14.2.3.3 TMR input function................................................................ 187
14.2.3.4 TMR output function.............................................................. 188
14.2.3.5 TMR synchronization............................................................. 189
14.2.3.6 Debug mode ......................................................................... 190
14.2.4 TMR9 registers ..........................................................................191
14.2.4.1 Control register1 (TMR9_CTRL1) ........................................... 191
14.2.4.2 Slave timer control register (TMR9_STCTRL) .......................... 192
14.2.4.3 DMA/interrupt enable register (TMR9_IDEN) ........................... 192
14.2.4.4 Interrupt status register (TMR9_ISTS) .................................... 193
14.2.4.5 Software event register (TMR9_SWEVT)................................. 194
14.2.4.6 Channel mode register1 (TMR9_CM1) .................................... 194
14.2.4.7 Channel control register (TMR9_CCTRL) ................................ 196
14.2.4.8 Counter value (TMR9_CVAL) ................................................. 197
14.2.4.9 Division value (TMR9_DIV) .................................................... 197

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14.2.4.10 Period register (TMR9_PR) .................................................. 197
14.2.4.11 Channel 1 data register (TMR9_C1DT) ................................. 197
14.2.4.12 Channel 2 data register (TMR9_C2DT) ................................. 198
14.2.5 TMR10 and TMR11 registers.......................................................198
14.2.5.1 Control register1 (TMRx_CTRL1) ........................................... 198
14.2.5.2 DMA/interrupt enable register (TMRx_IDEN) ........................... 199
14.2.5.3 Interrupt status register (TMRx_ISTS) .................................... 199
14.2.5.4 Software event register (TMRx_SWEVT) ................................. 199
14.2.5.5 Channel mode register1 (TMRx_CM1) .................................... 200
14.2.5.6 Channel control register (TMRx_CCTRL) ................................ 201
14.2.5.7 Counter value (TMRx_CVAL) ................................................. 202
14.2.5.8 Division value (TMRx_DIV) .................................................... 202
14.2.5.9 Period register (TMRx_PR) .................................................... 202
14.2.5.10 Channel 1 data register (TMRx_C1DT).................................. 202
14.3 Advanced-control timers (TMR1) ................................................. 203
14.3.1 TMR1 introduction ......................................................................203
14.3.2 TMR1 main features ...................................................................203
14.3.3 TMR1 functional overview...........................................................203
14.3.3.1 Count clock .......................................................................... 203
14.3.3.2 Counting mode ..................................................................... 205
14.3.3.3 TMR input function................................................................ 208
14.3.3.4 TMR output function.............................................................. 209
14.3.3.5 TMR break function............................................................... 212
14.3.3.6 TMR synchronization............................................................. 213
14.3.3.7 Debug mode ......................................................................... 214
14.3.4 TMR1 registers ..........................................................................214
14.3.4.1 TMR1 control register1 (TMR1_CTRL1) .................................. 214
14.3.4.2 TMR1 control register2 (TMR1_CTRL2) .................................. 215
14.3.4.3 TMR1 slave timer control register (TMR1_STCTRL) ................. 216
14.3.4.4 TMR1 DMA/interrupt enable register (TMR1_IDEN).................. 217
14.3.4.5 TMR1 interrupt status register (TMR1_ISTS) ........................... 218
14.3.4.6 TMR1 software event register (TMR1_SWEVT)........................ 219
14.3.4.7 TMR1 channel mode register1 (TMR1_CM1) ........................... 219
14.3.4.8 TMR1 channel mode register2 (TMR1_CM2) ........................... 221
14.3.4.9 TMR1 Channel control register (TMR1_CCTRL)....................... 222
14.3.4.10 TMR1 counter value (TMR1_CVAL) ...................................... 224
14.3.4.11 TMR1 division value (TMR1_DIV) ......................................... 224
14.3.4.12 TMR1 period register (TMR1_PR)......................................... 224

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14.3.4.13 TMR1 repetition period register (TMR1_RPR)........................ 224
14.3.4.14 TMR1 channel 1 data register (TMR1_C1DT)......................... 224
14.3.4.15 TMR1 channel 2 data register (TMR1_C2DT)......................... 224
14.3.4.16 TMR1 channel 3 data register (TMR1_C3DT)......................... 225
14.3.4.17 TMR1 channel 4 data register (TMRx_C4DT)......................... 225
14.3.4.18 TMR1 break register (TMR1_BRK)........................................ 225
14.3.4.19 TMR1 DMA control register (TMR1_DMACTRL) ..................... 226
14.3.4.20 TMR1 DMA data register (TMR1_DMADT)............................. 226
15 Window watchdog timer (WWDT) ................................................ 227
15.1 WWDT introduction .................................................................... 227
15.2 WWDT main features ................................................................. 227
15.3 WWDT functional overview ......................................................... 227
15.4 Debug mode.............................................................................. 228
15.5 WWDT registers ........................................................................ 228
15.5.1 Control register (WWDT_CTRL) ..................................................228
15.5.2 Configuration register (WWDT_CFG)...........................................229
15.5.3 Status register (WWDT_STS)......................................................229
16 Watchdog timer (WDT) ................................................................ 230
16.1 WDT introduction ....................................................................... 230
16.2 WDT main features .................................................................... 230
16.3 WDT functional overview ............................................................ 230
16.4 Debug mode.............................................................................. 231
16.5 WDT registers ........................................................................... 231
16.5.1 Command register (WDT_CMD) ..................................................231
16.5.2 Divider register (WDT_DIV).........................................................231
16.5.3 Reload register (WDT_RLD)........................................................232
16.5.4 Status register (WDT_STS).........................................................232
17 Enhanced real-time clock (ERTC) ............................................... 233
17.1 ERTC introduction...................................................................... 233
17.2 ERTC main features................................................................... 233
17.3 ERTC function overview ............................................................. 234
17.3.1 ERTC clock................................................................................234

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17.3.2 ERTC initialization......................................................................234
17.3.3 Periodic automatic wakeup .........................................................236
17.3.4 ERTC calibration ........................................................................236
17.3.5 Reference clock detection...........................................................237
17.3.6 Time stamp................................................................................237
17.3.7 Tamper detection .......................................................................238
17.3.8 Multiplexed function output .........................................................238
17.3.9 ERTC wakeup ............................................................................239
17.4 ERTC registers.......................................................................... 239
17.4.1 ERTC time register (ERTC_TIME) ...............................................240
17.4.2 ERTC date register (ERTC_DATE) ..............................................240
17.4.3 ERTC control register (ERTC_CTRL)...........................................241
17.4.4 ERTC initialization and status register (ERTC_STS).....................242
17.4.5 ERTC divider register (ERTC_DIV)..............................................243
17.4.6 ERTC wakeup timer register (ERTC_WAT) ..................................243
17.4.7 ERTC coarse calibration register (ERTC_CCAL) ..........................244
17.4.8 ERTC alarm clock A register (ERTC_ALA) ...................................244
17.4.9 ERTC alarm clock B register (ERTC_ALB) ...................................245
17.4.10 ERTC write protection register (ERTC_WP) ..............................245
17.4.11 ERTC subsecond register (ERTC_SBS) ....................................245
17.4.12 ERTC time adjustment register (ERTC_TADJ)...........................245
17.4.13 ERTC time stamp time register (ERTC_TSTM) ..........................246
17.4.14 ERTC time stamp date register (ERTC_TSDT) ..........................246
17.4.15 ERTC time stamp subsecond register (ERTC_TSSBS) ...............246
17.4.16 ERTC smooth calibration register (ERTC_SCAL) .......................246
17.4.17 ERTC tamper configuration register (ERTC_TAMP) ...................247
17.4.18 ERTC alarm clock A subsecond register (ERTC_ALASBS) .........248
17.4.19 ERTC alarm clock B subsecond register (ERTC_ALBSBS) .........248
17.4.20 ERTC battery powered domain data register (ERTC_BPRx) .......248
18 Analog-to-digital converter (ADC)............................................... 249
18.1 ADC introduction ....................................................................... 249
18.2 ADC main features..................................................................... 249
18.3 ADC structure............................................................................ 249
18.4 ADC functional overview............................................................. 250

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18.4.1 Channel management.................................................................250
18.4.1.1 Internal temperature sensor ................................................... 251
18.4.1.2 Internal reference voltage...................................................... 251
18.4.2ADC operation process...............................................................251
18.4.2.1 Power-on and calibration ....................................................... 251
18.4.2.2 Trigger................................................................................. 252
18.4.2.3 Sampling and conversion sequence........................................ 253
18.4.3 Conversion sequence management .............................................253
18.4.3.1 Sequence mode .................................................................... 253
18.4.3.2 Automatic preempted group conversion mode ......................... 254
18.4.3.3 Repetition mode.................................................................... 254
18.4.3.4 Partition mode ...................................................................... 254
18.4.4 Data management ......................................................................255
18.4.4.1 Data alignment ..................................................................... 255
18.4.4.2 Data read ............................................................................. 255
18.4.5 Voltage monitoring .....................................................................256
18.4.6 Status flag and interrupts............................................................256
18.5 ADC registers............................................................................ 256
18.5.1 ADC status register (ADC_STS) ..................................................257
18.5.2 ADC control register1 (ADC_CTRL1)...........................................257
18.5.3 ADC control register2 (ADC_CTRL2) ...........................................258
18.5.4 ADC sampling time register 1 (ADC_SPT1)..................................260
18.5.5 ADC sampling time register 2 (ADC_SPT2)..................................261
18.5.6 ADC preempted channel data offset register x (ADC_ PCDTOx)
(x=1..4) 262
18.5.7 ADC voltage monitor high threshold register (ADC_VWHB)...........262
18.5.8 ADC voltage monitor low threshold register (ADC_ VWLB)............262
18.5.9 ADC ordinary sequence register 1 (ADC_ OSQ1) .........................262
18.5.10 ADC ordinary sequence register 2 (ADC_ OSQ2) ......................263
18.5.11 ADC ordinary sequence register 3 (ADC_ OSQ3) ......................263
18.5.12 ADC preempted sequence register (ADC_ PSQ)........................263
18.5.13 ADC preempted data register x (ADC_ PDTx) (x=1..4) ...............264
18.5.14 ADC ordinary data register (ADC_ ODT) ...................................264
19 Controller area network (CAN) .................................................... 265
19.1 CAN introduction ....................................................................... 265

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19.2 CAN main features..................................................................... 265
19.3 Baud rate .................................................................................. 265
19.4 Interrupt management ................................................................ 268
19.5 Design tips................................................................................ 269
19.6 Functional overview ................................................................... 269
19.6.1 General description ....................................................................269
19.6.2 Operating modes........................................................................270
19.6.3 Test modes................................................................................270
19.6.4 Message filtering........................................................................271
19.6.5 Message transmission ................................................................273
19.6.6 Message reception .....................................................................274
19.6.7 Error management......................................................................275
19.7 CAN registers............................................................................ 275
19.7.1 CAN control and status registers.................................................277
19.7.1.1 CAN master control register (CAN_MCTRL) ............................ 277
19.7.1.2 CAN master status register (CAN_MSTS)................................ 278
19.7.1.3 CAN transmit status register (CAN_TSTS) .............................. 279
19.7.1.4 CAN receive FIFO 0 register (CAN_RF0) ................................ 282
19.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ................................ 282
19.7.1.6 CAN interrupt enable register (CAN_INTEN) ........................... 283
19.7.1.7 CAN error status register (CAN_ESTS) ................................... 284
19.7.1.8 CAN bit timing register (CAN_BTMG) ..................................... 285
19.7.2 CAN mailbox registers ................................................................285
19.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ......... 286
19.7.2.2 Transmit mailbox data length and time stamp register
(CAN_TMCx) (x=0..2)......................................................................... 286
19.7.2.3 Transmit mailbox data low register (CAN_TMDTLx) (x=0..2) ..... 286
19.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) ... 287
19.7.2.5 Receive FIFO mailbox identifier register (CAN_RFIx) (x=0..1) .. 287
19.7.2.6Receive FIFO mailbox data length and time stamp register
(CAN_RFCx) (x=0..1) ......................................................................... 287
19.7.2.7 Receive FIFO mailbox data low register
(CAN_RFDTLx) (x=0..1) ..................................................................... 287
19.7.2.8 Receive FIFO mailbox data high register
(CAN_RFDTHx) (x=0..1)..................................................................... 288
19.7.3 CAN filter registers.....................................................................288
19.7.3.1 CAN filter control register (CAN_FCTRL) ................................ 288

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19.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ............. 288
19.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG)...... 288
19.7.3.4 CAN filter FIFO association register (CAN_ FRF) .................... 288
19.7.3.5 CAN filter activation control register (CAN_ FACFG)................ 289
19.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx) (i=0..13; x=1..2)289
20 Universal serial bus full-seed device interface (OTGFS)............. 290
20.1 USBFS structure........................................................................ 290
20.2 OTGFS functional description ..................................................... 290
20.3 OTGFS clock and pin configuration ............................................. 291
20.3.1 OTGFS clock configuration .........................................................291
20.3.2 OTGFS pin configuration ............................................................291
20.4 OTGFS interrupts ...................................................................... 291
20.5 OTGFS functional description ..................................................... 292
20.5.1 OTGFS initialization ...................................................................292
20.5.2 OTGFS FIFO configuration .........................................................293
20.5.2.1 Device mode ........................................................................ 293
20.5.2.2 Host mode............................................................................ 294
20.5.2.3 Refresh controller transmit FIFO ............................................ 295
20.5.3 OTGFS host mode......................................................................295
20.5.3.1 Host initialization .................................................................. 295
20.5.3.2 OTGFS channel initialization.................................................. 296
20.5.3.3 Halting a channel.................................................................. 296
20.5.3.4 Queue depth......................................................................... 296
20.5.3.5 Special cases ....................................................................... 298
20.5.3.6 Host HFIR feature ................................................................. 298
20.5.3.7 Initialize bulk and control IN transfers..................................... 299
20.5.3.8 Initialize bulk and control OUT/SETUP transfers...................... 301
20.5.3.9 Initialize interrupt IN transfers................................................ 303
20.5.3.10 Initialize interrupt OUT transfers .......................................... 305
20.5.3.11 Initialize synchronous IN transfers........................................ 307
20.5.3.12 Initialize synchronous OUT transfers .................................... 308
20.5.4 OTGFS device mode ..................................................................310
20.5.4.1 Device initialization............................................................... 310
20.5.4.2 Endpoint initialization on USB reset........................................ 310
20.5.4.3 Endpoint initialization on enumeration completion.................... 311
20.5.4.4 Endpoint initialization on SetAddress command ....................... 311

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20.5.4.5 Endpoint initialization on SetConfiguration/SetInterface command311
20.5.4.6 Endpoint activation ............................................................... 311
20.5.4.7 USB endpoint deactivation..................................................... 312
20.5.4.8 Control write transfers (SETUP/Data OUT/Status IN) ............... 312
20.5.4.9 Control read transfers (SETUP/Data IN/Status OUT)................ 312
20.5.4.10 Control transfers (SETUP/Status IN)..................................... 313
20.5.4.11 Read FIFO packets ............................................................. 313
20.5.4.12 OUT data transfers.............................................................. 314
20.5.4.13 IN data transfers ................................................................. 316
20.5.4.14 Non-periodic (bulk and control) IN data transfers ................... 317
20.5.4.15 Non-synchronous OUT data transfers ................................... 318
20.5.4.16 Synchronous OUT data transfers.......................................... 320
20.5.4.17 Enable synchronous endpoints ............................................. 322
20.5.4.18 Incomplete synchronous OUT data transfers ......................... 323
20.5.4.19 Incomplete synchronous IN data transfers............................. 324
20.5.4.20 Periodic IN (interrupt and synchronous) data transfers ........... 325
20.6 OTGFS control and status registers............................................. 326
20.6.1 CSR register map.......................................................................326
20.6.2 OTGFS register address map......................................................328
20.6.3 OTGFS global registers ..............................................................330
20.6.3.1 OTGFS status and control register (OTGFS_GOTGCTL) .......... 330
20.6.3.2 OTGFS interrupt status control register (OTGFS_GOTGINT) .... 331
20.6.3.3 OTGFS AHB configuration register (OTGFS_GAHBCFG) .......... 331
20.6.3.4 OTGFS USB configuration register (OTGFS_GUSBCFG) .......... 332
20.6.3.5 OTGFS reset register (OTGFS_GRSTCTL).............................. 333
20.6.3.6 OTGFS interrupt register (OTGFS_GINTSTS).......................... 335
20.6.3.7 OTGFS interrupt mask register (OTGFS_GINTMSK) ................ 338
20.6.3.8 OTGFS receive status debug read/OTG status read and POP registers
(OTGFS_GRXSTSR / OTGFS_GRXSTSP)............................................ 339
20.6.3.9 OTGFS receive FIFO size register (OTGFS_GRXFSIZ) ............ 340
20.6.3.10OTGFS non-periodic Tx FIFO size (OTGFS_GNPTXFSIZ)/Endpoint 0
Tx FIFO size registers (OTGFS_DIEPTXF0)......................................... 341
20.6.3.11OTGFS non-periodic Tx FIFO size/request queue status register
(OTGFS_GNPTXSTS) ........................................................................ 341
20.6.3.12 OTGFS general controller configuration register
(OTGFS_GCCFG) .............................................................................. 342
20.6.3.13 OTGFS controller ID register (OTGFS_GUID) ........................ 342
20.6.3.14 OTGFS host periodic Tx FIFO size register
(OTGFS_HPTXFSIZ) .......................................................................... 342

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20.6.3.15OTGFS device IN endpoint Tx FIFO size register (OTGFS_DIEPTXFn)
(x=1…3, where n is the FIFO number) ................................................. 343
20.6.4 Host-mode registers ...................................................................343
20.6.4.1 OTGFS host mode configuration register (OTGFS_HCFG)........ 343
20.6.4.2 OTGFS host frame interval register (OTGFS_HFIR) ................. 344
20.6.4.3 OTGFS host frame number/frame time remaining register
(OTGFS_HFNUM) .............................................................................. 344
20.6.4.4 OTGFS host periodic Tx FIFO/request queue register
(OTGFS_HPTXSTS)........................................................................... 344
20.6.4.5 OTGFS host all channels interrupt register (OTGFS_HAINT) .... 345
20.6.4.6 OTGFS host all channels interrupt mask register
(OTGFS_HAINTMSK) ......................................................................... 345
20.6.4.7 OTGFS host port control and status register (OTGFS_HPRT) ... 345
20.6.4.8 OTGFS host channelx characteristics register (OTGFS_HCCHARx)
(x = 0...8, where x= channel number) .................................................. 347
20.6.4.9 OTGFS host channelx interrupt register (OTGFS_HCINTx)
(x = 0...8, where x= channel number) .................................................. 348
20.6.4.10OTGFS host channelx interrupt mask register (OTGFS_HCINTMSKx)
(x = 0...8, where x= channel number) .................................................. 349
20.6.4.11 .....OTGFS host channelx transfer size register (OTGFS_HCTSIZx)
(x = 0...8, where x= channel number) .................................................. 349
20.6.5 Device-mode registers................................................................349
20.6.5.1 OTGFS device configure register (OTGFS_DCFG)................... 349
20.6.5.2 OTGFS device control register (OTGFS_DCTL) ....................... 350
20.6.5.3 OTGFS device status register (OTGFS_DSTS) ........................ 351
20.6.5.4 OTGFS device OTGFSIN endpoint common interrupt mask register
(OTGFS_DIEPMSK) ........................................................................... 352
20.6.5.5 OTGFS device OUT endpoint common interrupt mask register
(OTGFS_DOEPMSK).......................................................................... 353
20.6.5.6 OTGFS device all endpoints interrupt mask register
(OTGFS_DAINT)................................................................................ 353
20.6.5.7 OTGFS all endpoints interrupt mask register (OTGFS_DAINTMSK)353
20.6.5.8 OTGFS device IN endpoint FIFO empty interrupt mask register
(OTGFS_DIEPEMPMSK) .................................................................... 354
20.6.5.9 OTGFS device control IN endpoint 0 control register
(OTGFS_DIEPCTL0) .......................................................................... 354
20.6.5.10 OTGFS device IN endpoint-x control register (OTGFS_DIEPCTLx)
(x=x=1…3, where x is endpoing number) ............................................. 355
20.6.5.11 OTGFS device control OUT endpoint 0 control register
(OTGFS_DOEPCTL0)......................................................................... 357

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20.6.5.12 OTGFS device control OUT endpoint-x control register
(OTGFS_DOEPCTLx) (x=1…3, where x if endpoint number) .................. 358
20.6.5.13OTGFS device IN endpoint-x interrupt register (OTGFS_DIEPINTx)
(x=0…3, where x if endpoint number) .................................................. 360
20.6.5.14OTGFS device OUT endpoint-x interrupt register (OTGFS_DOEPINTx)
(x=0…3, where x if endpoint number) .................................................. 361
20.6.5.15 OTGFS device IN endpoint 0 transfer size register
(OTGFS_DIEPTSIZ0) ......................................................................... 361
20.6.5.16 OTGFS device OUT endpoint 0 transfer size register
(OTGFS_DOEPTSIZ0)........................................................................ 362
20.6.5.17 OTGFS device IN endpoint-x transfer size register
(OTGFS_DIEPTSIZx) (x=1…3, where x is endpoint number) .................. 362
20.6.5.18 OTGFS device IN endpoint transmit FIFO status register
(OTGFS_DTXFSTSx) (x=1…3, where x is endpoint number ).................. 363
20.6.5.19 OTGFS device OUT endpoint-x transfer size register
(OTGFS_DOEPTSIZx) (x=1…3, where x is endpoint number) ................ 363
20.6.6 Power and clock control registers................................................364
20.6.6.1 OTGFS power and clock gating control register
(OTGFS_PCGCCTL) .......................................................................... 364
21 Comparator (COMP) .................................................................... 365
21.1 COMP introduction..................................................................... 365
21.2 Main features ............................................................................ 365
21.3 Interrupt management ................................................................ 366
21.4 Design tips................................................................................ 366
21.5 Functional overview ................................................................... 366
21.5.1 Analog comparator .....................................................................366
21.6 CMP registers............................................................................ 367
21.6.1 Comparator control and status register 1 (COMP_CTRLSTS1) ..................367
21.6.2 Comparator Control/Status Register 2 (COMP_CTRLSTS2) .....................369
22 Debug (DEBUG) .......................................................................... 370
22.1 Debug introduction..................................................................... 370
22.2 Debug and Trace ....................................................................... 370
22.3 I/O pin control............................................................................ 370
22.4 DEGUB registers ....................................................................... 371
22.4.1 DEBUG device ID (DEBUG_IDCODE)..........................................371

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22.4.2 DEBUG control register (DEBUG_CTRL) .....................................371
23 Revision history.......................................................................... 373