Atmel ATA5278 User manual

Features
•SPI for Microcontroller Connection with Up to 1 Mbit/s
•Internal Data Buffer for Timing-independent Data Transmission
•Programmable Driver Current Regulation
•One-chip Antenna Driver Stage for 1A Peak Current
•LF Baud Rates Between 1 kbaud and 4 kbaud
•Quick Start Control (QSC) for Fast Oscillation Build-up and Decay Timing
•Integrated Oscillator for Ceramic Resonators
•Power Supply Range from 7.5V to 16V Direct Battery Input
(Up to 28V With Limited Function Range)
•Amplitude Shift Keying (ASK) Modulation
•Phase Shift Keying (PSK) Modulation
•Carrier Frequency Range from 100 kHz to 150 kHz
•Operational Temperature –40°C to +105°C
•EMI and ESD According to Automotive Requirements
•Highly Integrated — Less External Components Required
Applications
•Hands-free Car Access (Passive Entry/Go)
•Tire Pressure Measurement
•Home Access Control
•Care Watch Systems
Benefits
•Diagnosis Function and Overtemperature Protection
•Load Dump Protection Up to 45V for 12V Boards
•Power-down Mode for Minimum Power Consumption
1. Description
The ATA5278 device is an integrated BCDMOS antenna driver IC dedicated as a
transmitter for Passive Entry/Go (PEG) car applications and for other hands-free
access control applications.
It includes the full functionality of generating a magnetic LF field in conjunction with an
antenna coil to transmit data to a receiver in a key fob, card or transponder. A micro-
controller can access the chip via a bi-directional serial interface.
Stand-alone
Antenna Driver
ATA5278
Rev. 4832C–RKE–02/06

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ATA5278
Figure 1-1. Block Diagram
2. Pin Configuration
Figure 2-1. Pinning QFN28
5-V
regulator Oscillator
SPI
ATA5278
Boost
converter
control
Driver control
logic
Control
and
status
register
Current and
zero crossing
sensing
TESTDGND SCANE
AGND
VSHUNT
QSC
DRV1
CBOOST
PGND1
PGND2
VDS
VL1 VL2 VL3 VBATT VDD OSCI OSCO CLKO
PGND3
CINT
S_CS
S_CLK
S_DI
S_DO
LF data buffer
LS driver
HS driver
MODACTIVE
NRES
Voltage
interface
VIF
PGND1
PGND2
PGND3
VDS
DRV1
CBOOST
QSC
S_CLK
S_CS
OSCI
OSCO
VIF
CLKO
TEST
VL3 VL2 VL1 VBATT VDD S_DO S_DI
VSHUNT
AGND
DGND
CINT
MODACTIVE
NRES
SCANE
8 9 10 11 12 13 14
28 27 26 25 24 23 22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
ATA5278

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ATA5278
Table 2-1. Pin Description
Pin Symbol Function
1 PGND1 Boost transistor ground
2 PGND2 Boost transistor ground
3 PGND3 Boost transistor ground
4 VDS Driver voltage supply input
5 DRV1 Antenna driver stage output
6 CBOOST External bootstrap capacitor connection
7 QSC QSC transistor-gate driver-stage output
8 VSHUNT Antenna current-shunt resistor connection
9 AGND Analog ground (sensoric/antenna driver)
10 DGND Digital ground (logic)
11 CINT External integrator-capacitor connection
12 MODACTIVE Modulator status pin output
13 NRES Reset input (inverted)
14 SCANE For factory test purposes only (connect to ground)
15 TEST For factory test purposes only (connect to ground)
16 CLKO Clock signal output
17 VIF Logic interface voltage supply
18 OSCO Oscillator output (for resonator/crystal connection)
19 OSCI Oscillator input (for external clock source or resonator/crystal connection)
20 S_CS Chip select for serial interface
21 S_CLK Clock input for serial interface
22 S_DI Data input for serial interface
23 S_DO Data output of serial interface
24 VDD Internal 5 V stabilizing capacitor connection
25 VBATT Battery supply
26 VL1 Coil connection for the boost converter low-side switch
27 VL2 Coil connection for the boost converter low-side switch
28 VL3 Coil connection for the boost converter low-side switch

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ATA5278
3. Functional Description
3.1 General Description
The IC contains a half-bridge coil driver stage with a special driver voltage regulator and control
logic with diagnosis circuitry. It is controllable by a serial programming interface (SPI).
In combination with an LC antenna circuitry, the IC generates an electromagnetic LF field. The
carrier frequency for the antenna is generated by the oscillator and a pre-scaler logic.
The LF field can be modulated to transmit data to a suitable receiver. Two modulation modes
are available: Amplitude Shift Keying (ASK) and 180° Phase Shift Keying (PSK). The transmis-
sion data has to be stored in the internal data buffer.
The IC consists of two main functional blocks:
• The SPI with the data buffer, the control registers and the oscillator
• The driver stage with its control logic and the power supply stage
A boost converter is used to supply the driver half-bridge with a high voltage and a regulated
current even if the battery voltage is low. The antenna current is programmable in 16 steps to
support a transmission with various field strengths.
The driver circuitry is protected against short-circuits and overload.
3.2 Operational States
After power-on-reset, the ATA5278 is in power-down mode. To achieve minimum power con-
sumption, only the internal 5-V supply and the control registers are active. The IC can only be
activated by the external control unit via the serial interface (i.e., the chip select line is enabled).
Once activated, the chip keeps the oscillator active and waits for commands on the serial bus.
This state can be described as standby mode. Only upon an external reset or on command fol-
lowed by disabling the chip select line, the power-down mode is re-invoked.
The modulator stage, together with the antenna driver and the power supply, is activated as
soon as LF data is written into the buffer and remains in this state until all data has been sent, a
stop command has been given via the SPI or a fault occurred. The data modulation is running
independently of the SPI activity and can be monitored with the MODACTIVE pin.
3.3 Power-down Mode
The ATA5278 should be kept in power-down mode as long as the LF channel is not used,
because not only is the current consumption minimal, but the internal logic is also reset. The
antenna driver stage is in high impedance mode. To power-up the chip, the chip-select line
(S_CS) has to be activated for an appropriate time. The SPI then starts the internal oscillator
which is necessary for proper operation. Only after a certain oscillation build-up time, is full func-
tionality available. The microcontroller can check out the state of the IC with two state bits
automatically returned by any SPI command.

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ATA5278
Figure 3-1. Power-up Timing
The startup time, tstartup, in Figure 3-1 depends on the clock source used in the application. Typi-
cal oscillation build-up times are below 100 µs for ceramic and about 1 ms for crystal resonators.
When using an active clock source, the startup time can be neglected. The internal logic
debounces the first clock signals until it finally powers-up the IC for the time tdeb. Note that during
this time, the chip select signal S_CS has to be permanently active.
The normal way to bring the chip back into power-down mode is to use an SPI command. Deac-
tivating the chip-select line right after the power-down command, an internal standby timer is
started and will run for ttimeout = (2048/fOSCI). In this time, the antenna driver stage is stopped to
discharge any energies possibly remaining in the antenna circuit. If the chip-select line is reacti-
vated during this time, the sequence is interrupted and the IC remains in standby mode.
Otherwise, the power-down mode is engaged after the timeout, the oscillator is stopped and the
driver stages are switched to high impedance. Figure 3-2 illustrates this behavior.
Figure 3-2. Power-down Timing
Note that if command 4 is omitted and only the chip-select line is disabled, the ATA5278 stays
operational (i.e., the oscillator keeps running, an eventually running LF data modulation is not
interrupted). Here, only the SPI itself is disabled and the serial bus can be used for other devices
connected to it.
Z
t
startup
Legend: Z = high impedance
S_CS
QSC
DRV1
OSCI/OSCO Oscillation build-up Steady oscillation
t
deb
S_CS
S_CLK
S_DI
DRV1
OSC
X
8 CLK
cmd 4
f = 8 MHz
Z
t
timeout
Legend: X = do not care
Z = high impedance

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ATA5278
In case the microcontroller is not able to communicate properly with the ATA5278 or any other
disturbance has occurred, it can trigger a reset (like a power-on-reset, POR) in the chip by pull-
ing the NRES pin to ground, which will bring the logic back to the startup state, i.e., all
configurations are at default and the IC is in power-down mode.
Figure 3-3. External Reset
3.4 Oscillator
The ATA5278 is equipped with an internal oscillator circuitry that provides the system clock sig-
nal needed for operation. It is intended to work with an externally applied passive reference
device such as a ceramic resonator or a crystal. Active clock sources like microcontrollers or
crystal oscillators, however, can also be used. Figure 3-4 shows the internal structure of the
oscillator circuitry.
Figure 3-4. Internal Oscillator Circuitry
OSC
S_CS
Int. state
NRES
t
NRES
X
X
f = 8 MHz
POR Power-down
S1
OSCOOSCI
R
fb
= 250 kΩtyp.
R
d
= 420 Ω
C
in
= 12 pF typ. C
out
= 12 pF typ.
Clock signal
judging
To internal
logic
Pull-down
Enable signal
from SPI

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ATA5278
The main element of this circuit is the parallel inverting stage which generates the clock signal in
conjunction with the external reference device. During power-down mode, these inverters are
shut down and the pull-down structure on the OSCI pin is active. As soon as the SPI enables the
oscillator, the pull-down is disabled and the inverters are powered up. Now, the clock signal
assessment stage monitors the signal on the OSCI pin. As soon as the amplitude and the period
reach acceptable values, one of the two inverters (i.e., the drivers) is shut down in order to
reduce power dissipation in the external reference device. Figure 3-5 illustrates the period
assessment.
Figure 3-5. Oscillator Signal Assessment
3.5 I/O Voltage Interface
All digital I/O pins, including the reset input pin NRES, are passed through the internal voltage
interface before they reach their concerning blocks. This interface prevents possible compensa-
tion currents, as the control logic of the ATA5278 is supplied by the internal 5V regulator. It is
capable of handling I/O voltages between 3.15V and 5.5V, determined by the voltage applied to
the VIF pin.
The pins NRES and S_CS are additionally equipped with a pull-up and a pull-down structure
respectively in order to ensure a defined behavior of the ATA5278 in case of a broken connec-
tion. If the NRES line is broken, the pull-up structure keeps the input in passive state and normal
operation is possible. A broken S_CS line will cause a permanently disabled SPI and S_DO pin,
so communication between the microcontroller and other SPI bus members is still possible. For
further details on the voltage interface, please refer to the table “Electrical Characteristics” on
page 27.
Oscillator
enable signal
OSCO signal
Second inverter
enable signal
Clock signal for
internal logic
Clock signal for
internal logic
t > t
LOW,max
t < t
LOW,max

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ATA5278
3.6 SPI
The control interface of the ATA5278 consists of an eight-bit synchronous SPI. It has a clock
input (S_CLK) which supports frequencies up to 1 MHz, a chip select line (S_CS) which enables
the interface, a serial data input (S_DI) and a serial data output (S_DO). The output pin is of a
tristate type, which will be set to high-impedance state as soon as the chip-select line is dis-
abled. The interface is in slave mode configuration. This means that an SPI master (e.g. a
microcontroller) is required for communication with the ATA5278, as the IC will neither start a
communication by itself nor is it able to provide the serial clock signal. Figure 3-6 sketches the
internal structure.
Figure 3-6. SPI Structure
Once enabled by the chip-select line, the data at the S_DI pin is shifted into the input register
with every rising edge of the input clock signal. At the pin S_DO, the actual data of the LSB of
the output register is available. The output register is shifted on every falling edge of the input
clock signal. Two timing schemes for SPI data communication are supported, which are shown
in Figure 3-7 on page 9.
S_CLK
S_DO
S_DI
S_CS
MSB 6 5 4 3 2 1 LSB
tri
MSB 6 5 4 3 2 1 LSB
8
Internal data bus
8
Control logic/internal data bus
Output register
Input register

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ATA5278
Figure 3-7. SPI Timing Diagram
3.7 SPI Commands
The microcontroller can access the following functions of the ATA5278 via the SPI:
• Read from/write to configuration register 1
• Read from/write to configuration register 2
• Read from the status register
• Write LF transmission data to the buffer and start the transmission
• Verify the state of the data buffer
• Clear the fault memory
• Stop the modulator
• Enable the power-down mode
Table 3-1 on page 10 lists all functions and their definitions.
S_DI
S_DO
X
Z
LSB Input bit 1 Input bit 2
LSB Output bit 1
t
S_CLK,h
t
S_CLK,per
t
DO,enable
t
DI,hold
t
DO,delay
Second Possible Serial Timing, S_CLK Polarity 1, Phase 1
X
t
DI,setup
S_CS
S_CLK
out
MSB X
MSB Z
t
DO,disable
XX
t
S_CLK,l
S_CS
S_CLK
S_DI
S_DO
X
Z
LSB Input bit 1 Input bit 2
LSB Output bit 1 Output bit 2
t
S_CLK,h
t
S_CLK,per
t
DO,enable
t
DI,hold
t
DO,delay
First Possible Serial Timing, S_CLK Polarity 0, Phase 0
t
DI,setup
MSB X
MSB X Z
t
DO,disable
XX
t
S_CLK,l

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ATA5278
Table 3-1. SPI Commands
No.I/OMSB654321LSBDescription
1I1
O1
0
SR
0
0
0
0
0
0
0
0
0
0
0
RTS
0
0
Check status of IC
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
2I1
O1
0
SR
0
0
0
0
1
0
0
0
0
0
0
RTS
1
0
Reset fault memory
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
3I1
O1
0
SR
0
0
1
0
0
0
0
0
0
0
0
RTS
1
0
Stop modulator
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
4I1 0
SR
1
0
0
0
0
0
0
0
0
0
0
RTS
1
0
Enable power-down mode
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
5
I1
O1
I2
O2
0
SR
0
0
0
0
0
0
0
0
IC3
0
0
0
IC2
0
0
0
IC1
0
1
0
IC0
1
0
RTS
0
0
0
0
AP
0
Write configuration register 1
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
IC3..0: antenna coil current selector
AP: 0 ASK modulation mode, 1 PSK modulation mode
6
I1
O1
I2
O2
0
SR
X
0
0
0
X
0
0
0
X
IC3
0
0
X
IC2
0
0
X
IC1
1
0
X
IC0
1
RTS
X
0
0
0
X
AP
Read configuration register 1
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
IC3..0: antenna coil current selector
AP: 0 ASK modulation mode, 1 PSK modulation mode
7
I1
O1
I2
O2
0
SR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
BR1
0
0
RTS
BR0
0
0
0
PS
0
Write configuration register 2
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
BR1..0: LF data baud rate selector
PS: 0 CLKO prescaler disabled, 1 prescaler enabled
8
I1
O1
I2
O2
0
SR
X
0
0
0
X
0
0
0
X
0
0
0
X
0
1
0
X
0
0
0
X
BR1
1
RTS
X
BR0
0
0
X
PS
Read configuration register 2
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
BR1..0: LF data baud rate selector
PS: 0 CLKO prescaler disabled, 1 prescaler enabled
9
I1
O1
I2
O2
0
SR
X
0
0
0
X
0
0
0
X
IC
0
0
X
CH
1
0
X
OL
1
0
X
SH
1
RTS
X
SL
0
0
X
OT
Read status register
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
IC: illegal command received
CH: overcurrent in antenna footpoint detected
OL: open load detected
SH: overcurrent to VBATT detected at driver output
SL: overcurrent to GND detected at driver output
OT: overtemperature detected
10
I1
O1
I2
O2
0
SR
X
0
0
0
X
D6
0
0
X
D5
0
0
X
D4
0
0
X
D3
0
0
X
D2
1
RTS
X
D1
0
0
X
D0
Check free LF data buffer space
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
D6..0: free logical LF data bits in buffer
11
I1
O1
Ix
Ox
1
SR
HB7
B7
D6
0
HB6
B6
D5
0
HB5
B5
D4
0
HB4
B4
D3
0
HB3
B3
D2
0
HB2
B2
D1
RTS
HB1
B1
D0
0
HB0
B0
Write LF data to buffer and start modulator
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
D6..0: number of logical LF bits to be written into buffer
HB7..0: LF half bits (2 for one logical bit)
B7..0: input bit from the previous controller data word