Atmel ATA5278 User manual

Features
•SPI for Microcontroller Connection with Up to 1 Mbit/s
•Internal Data Buffer for Timing-independent Data Transmission
•Programmable Driver Current Regulation
•One-chip Antenna Driver Stage for 1A Peak Current
•LF Baud Rates Between 1 kbaud and 4 kbaud
•Quick Start Control (QSC) for Fast Oscillation Build-up and Decay Timing
•Integrated Oscillator for Ceramic Resonators
•Power Supply Range from 7.5V to 16V Direct Battery Input
(Up to 28V With Limited Function Range)
•Amplitude Shift Keying (ASK) Modulation
•Phase Shift Keying (PSK) Modulation
•Carrier Frequency Range from 100 kHz to 150 kHz
•Operational Temperature –40°C to +105°C
•EMI and ESD According to Automotive Requirements
•Highly Integrated — Less External Components Required
Applications
•Hands-free Car Access (Passive Entry/Go)
•Tire Pressure Measurement
•Home Access Control
•Care Watch Systems
Benefits
•Diagnosis Function and Overtemperature Protection
•Load Dump Protection Up to 45V for 12V Boards
•Power-down Mode for Minimum Power Consumption
1. Description
The ATA5278 device is an integrated BCDMOS antenna driver IC dedicated as a
transmitter for Passive Entry/Go (PEG) car applications and for other hands-free
access control applications.
It includes the full functionality of generating a magnetic LF field in conjunction with an
antenna coil to transmit data to a receiver in a key fob, card or transponder. A micro-
controller can access the chip via a bi-directional serial interface.
Stand-alone
Antenna Driver
ATA5278
Rev. 4832C–RKE–02/06

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ATA5278
Figure 1-1. Block Diagram
2. Pin Configuration
Figure 2-1. Pinning QFN28
5-V
regulator Oscillator
SPI
ATA5278
Boost
converter
control
Driver control
logic
Control
and
status
register
Current and
zero crossing
sensing
TESTDGND SCANE
AGND
VSHUNT
QSC
DRV1
CBOOST
PGND1
PGND2
VDS
VL1 VL2 VL3 VBATT VDD OSCI OSCO CLKO
PGND3
CINT
S_CS
S_CLK
S_DI
S_DO
LF data buffer
LS driver
HS driver
MODACTIVE
NRES
Voltage
interface
VIF
PGND1
PGND2
PGND3
VDS
DRV1
CBOOST
QSC
S_CLK
S_CS
OSCI
OSCO
VIF
CLKO
TEST
VL3 VL2 VL1 VBATT VDD S_DO S_DI
VSHUNT
AGND
DGND
CINT
MODACTIVE
NRES
SCANE
8 9 10 11 12 13 14
28 27 26 25 24 23 22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
ATA5278

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ATA5278
Table 2-1. Pin Description
Pin Symbol Function
1 PGND1 Boost transistor ground
2 PGND2 Boost transistor ground
3 PGND3 Boost transistor ground
4 VDS Driver voltage supply input
5 DRV1 Antenna driver stage output
6 CBOOST External bootstrap capacitor connection
7 QSC QSC transistor-gate driver-stage output
8 VSHUNT Antenna current-shunt resistor connection
9 AGND Analog ground (sensoric/antenna driver)
10 DGND Digital ground (logic)
11 CINT External integrator-capacitor connection
12 MODACTIVE Modulator status pin output
13 NRES Reset input (inverted)
14 SCANE For factory test purposes only (connect to ground)
15 TEST For factory test purposes only (connect to ground)
16 CLKO Clock signal output
17 VIF Logic interface voltage supply
18 OSCO Oscillator output (for resonator/crystal connection)
19 OSCI Oscillator input (for external clock source or resonator/crystal connection)
20 S_CS Chip select for serial interface
21 S_CLK Clock input for serial interface
22 S_DI Data input for serial interface
23 S_DO Data output of serial interface
24 VDD Internal 5 V stabilizing capacitor connection
25 VBATT Battery supply
26 VL1 Coil connection for the boost converter low-side switch
27 VL2 Coil connection for the boost converter low-side switch
28 VL3 Coil connection for the boost converter low-side switch

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ATA5278
3. Functional Description
3.1 General Description
The IC contains a half-bridge coil driver stage with a special driver voltage regulator and control
logic with diagnosis circuitry. It is controllable by a serial programming interface (SPI).
In combination with an LC antenna circuitry, the IC generates an electromagnetic LF field. The
carrier frequency for the antenna is generated by the oscillator and a pre-scaler logic.
The LF field can be modulated to transmit data to a suitable receiver. Two modulation modes
are available: Amplitude Shift Keying (ASK) and 180° Phase Shift Keying (PSK). The transmis-
sion data has to be stored in the internal data buffer.
The IC consists of two main functional blocks:
• The SPI with the data buffer, the control registers and the oscillator
• The driver stage with its control logic and the power supply stage
A boost converter is used to supply the driver half-bridge with a high voltage and a regulated
current even if the battery voltage is low. The antenna current is programmable in 16 steps to
support a transmission with various field strengths.
The driver circuitry is protected against short-circuits and overload.
3.2 Operational States
After power-on-reset, the ATA5278 is in power-down mode. To achieve minimum power con-
sumption, only the internal 5-V supply and the control registers are active. The IC can only be
activated by the external control unit via the serial interface (i.e., the chip select line is enabled).
Once activated, the chip keeps the oscillator active and waits for commands on the serial bus.
This state can be described as standby mode. Only upon an external reset or on command fol-
lowed by disabling the chip select line, the power-down mode is re-invoked.
The modulator stage, together with the antenna driver and the power supply, is activated as
soon as LF data is written into the buffer and remains in this state until all data has been sent, a
stop command has been given via the SPI or a fault occurred. The data modulation is running
independently of the SPI activity and can be monitored with the MODACTIVE pin.
3.3 Power-down Mode
The ATA5278 should be kept in power-down mode as long as the LF channel is not used,
because not only is the current consumption minimal, but the internal logic is also reset. The
antenna driver stage is in high impedance mode. To power-up the chip, the chip-select line
(S_CS) has to be activated for an appropriate time. The SPI then starts the internal oscillator
which is necessary for proper operation. Only after a certain oscillation build-up time, is full func-
tionality available. The microcontroller can check out the state of the IC with two state bits
automatically returned by any SPI command.

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ATA5278
Figure 3-1. Power-up Timing
The startup time, tstartup, in Figure 3-1 depends on the clock source used in the application. Typi-
cal oscillation build-up times are below 100 µs for ceramic and about 1 ms for crystal resonators.
When using an active clock source, the startup time can be neglected. The internal logic
debounces the first clock signals until it finally powers-up the IC for the time tdeb. Note that during
this time, the chip select signal S_CS has to be permanently active.
The normal way to bring the chip back into power-down mode is to use an SPI command. Deac-
tivating the chip-select line right after the power-down command, an internal standby timer is
started and will run for ttimeout = (2048/fOSCI). In this time, the antenna driver stage is stopped to
discharge any energies possibly remaining in the antenna circuit. If the chip-select line is reacti-
vated during this time, the sequence is interrupted and the IC remains in standby mode.
Otherwise, the power-down mode is engaged after the timeout, the oscillator is stopped and the
driver stages are switched to high impedance. Figure 3-2 illustrates this behavior.
Figure 3-2. Power-down Timing
Note that if command 4 is omitted and only the chip-select line is disabled, the ATA5278 stays
operational (i.e., the oscillator keeps running, an eventually running LF data modulation is not
interrupted). Here, only the SPI itself is disabled and the serial bus can be used for other devices
connected to it.
Z
t
startup
Legend: Z = high impedance
S_CS
QSC
DRV1
OSCI/OSCO Oscillation build-up Steady oscillation
t
deb
S_CS
S_CLK
S_DI
DRV1
OSC
X
8 CLK
cmd 4
f = 8 MHz
Z
t
timeout
Legend: X = do not care
Z = high impedance

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ATA5278
In case the microcontroller is not able to communicate properly with the ATA5278 or any other
disturbance has occurred, it can trigger a reset (like a power-on-reset, POR) in the chip by pull-
ing the NRES pin to ground, which will bring the logic back to the startup state, i.e., all
configurations are at default and the IC is in power-down mode.
Figure 3-3. External Reset
3.4 Oscillator
The ATA5278 is equipped with an internal oscillator circuitry that provides the system clock sig-
nal needed for operation. It is intended to work with an externally applied passive reference
device such as a ceramic resonator or a crystal. Active clock sources like microcontrollers or
crystal oscillators, however, can also be used. Figure 3-4 shows the internal structure of the
oscillator circuitry.
Figure 3-4. Internal Oscillator Circuitry
OSC
S_CS
Int. state
NRES
t
NRES
X
X
f = 8 MHz
POR Power-down
S1
OSCOOSCI
R
fb
= 250 kΩtyp.
R
d
= 420 Ω
C
in
= 12 pF typ. C
out
= 12 pF typ.
Clock signal
judging
To internal
logic
Pull-down
Enable signal
from SPI

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ATA5278
The main element of this circuit is the parallel inverting stage which generates the clock signal in
conjunction with the external reference device. During power-down mode, these inverters are
shut down and the pull-down structure on the OSCI pin is active. As soon as the SPI enables the
oscillator, the pull-down is disabled and the inverters are powered up. Now, the clock signal
assessment stage monitors the signal on the OSCI pin. As soon as the amplitude and the period
reach acceptable values, one of the two inverters (i.e., the drivers) is shut down in order to
reduce power dissipation in the external reference device. Figure 3-5 illustrates the period
assessment.
Figure 3-5. Oscillator Signal Assessment
3.5 I/O Voltage Interface
All digital I/O pins, including the reset input pin NRES, are passed through the internal voltage
interface before they reach their concerning blocks. This interface prevents possible compensa-
tion currents, as the control logic of the ATA5278 is supplied by the internal 5V regulator. It is
capable of handling I/O voltages between 3.15V and 5.5V, determined by the voltage applied to
the VIF pin.
The pins NRES and S_CS are additionally equipped with a pull-up and a pull-down structure
respectively in order to ensure a defined behavior of the ATA5278 in case of a broken connec-
tion. If the NRES line is broken, the pull-up structure keeps the input in passive state and normal
operation is possible. A broken S_CS line will cause a permanently disabled SPI and S_DO pin,
so communication between the microcontroller and other SPI bus members is still possible. For
further details on the voltage interface, please refer to the table “Electrical Characteristics” on
page 27.
Oscillator
enable signal
OSCO signal
Second inverter
enable signal
Clock signal for
internal logic
Clock signal for
internal logic
t > t
LOW,max
t < t
LOW,max

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ATA5278
3.6 SPI
The control interface of the ATA5278 consists of an eight-bit synchronous SPI. It has a clock
input (S_CLK) which supports frequencies up to 1 MHz, a chip select line (S_CS) which enables
the interface, a serial data input (S_DI) and a serial data output (S_DO). The output pin is of a
tristate type, which will be set to high-impedance state as soon as the chip-select line is dis-
abled. The interface is in slave mode configuration. This means that an SPI master (e.g. a
microcontroller) is required for communication with the ATA5278, as the IC will neither start a
communication by itself nor is it able to provide the serial clock signal. Figure 3-6 sketches the
internal structure.
Figure 3-6. SPI Structure
Once enabled by the chip-select line, the data at the S_DI pin is shifted into the input register
with every rising edge of the input clock signal. At the pin S_DO, the actual data of the LSB of
the output register is available. The output register is shifted on every falling edge of the input
clock signal. Two timing schemes for SPI data communication are supported, which are shown
in Figure 3-7 on page 9.
S_CLK
S_DO
S_DI
S_CS
MSB 6 5 4 3 2 1 LSB
tri
MSB 6 5 4 3 2 1 LSB
8
Internal data bus
8
Control logic/internal data bus
Output register
Input register

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ATA5278
Figure 3-7. SPI Timing Diagram
3.7 SPI Commands
The microcontroller can access the following functions of the ATA5278 via the SPI:
• Read from/write to configuration register 1
• Read from/write to configuration register 2
• Read from the status register
• Write LF transmission data to the buffer and start the transmission
• Verify the state of the data buffer
• Clear the fault memory
• Stop the modulator
• Enable the power-down mode
Table 3-1 on page 10 lists all functions and their definitions.
S_DI
S_DO
X
Z
LSB Input bit 1 Input bit 2
LSB Output bit 1
t
S_CLK,h
t
S_CLK,per
t
DO,enable
t
DI,hold
t
DO,delay
Second Possible Serial Timing, S_CLK Polarity 1, Phase 1
X
t
DI,setup
S_CS
S_CLK
out
MSB X
MSB Z
t
DO,disable
XX
t
S_CLK,l
S_CS
S_CLK
S_DI
S_DO
X
Z
LSB Input bit 1 Input bit 2
LSB Output bit 1 Output bit 2
t
S_CLK,h
t
S_CLK,per
t
DO,enable
t
DI,hold
t
DO,delay
First Possible Serial Timing, S_CLK Polarity 0, Phase 0
t
DI,setup
MSB X
MSB X Z
t
DO,disable
XX
t
S_CLK,l

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ATA5278
Table 3-1. SPI Commands
No.I/OMSB654321LSBDescription
1I1
O1
0
SR
0
0
0
0
0
0
0
0
0
0
0
RTS
0
0
Check status of IC
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
2I1
O1
0
SR
0
0
0
0
1
0
0
0
0
0
0
RTS
1
0
Reset fault memory
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
3I1
O1
0
SR
0
0
1
0
0
0
0
0
0
0
0
RTS
1
0
Stop modulator
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
4I1 0
SR
1
0
0
0
0
0
0
0
0
0
0
RTS
1
0
Enable power-down mode
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
5
I1
O1
I2
O2
0
SR
0
0
0
0
0
0
0
0
IC3
0
0
0
IC2
0
0
0
IC1
0
1
0
IC0
1
0
RTS
0
0
0
0
AP
0
Write configuration register 1
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
IC3..0: antenna coil current selector
AP: 0 ASK modulation mode, 1 PSK modulation mode
6
I1
O1
I2
O2
0
SR
X
0
0
0
X
0
0
0
X
IC3
0
0
X
IC2
0
0
X
IC1
1
0
X
IC0
1
RTS
X
0
0
0
X
AP
Read configuration register 1
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
IC3..0: antenna coil current selector
AP: 0 ASK modulation mode, 1 PSK modulation mode
7
I1
O1
I2
O2
0
SR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
BR1
0
0
RTS
BR0
0
0
0
PS
0
Write configuration register 2
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
BR1..0: LF data baud rate selector
PS: 0 CLKO prescaler disabled, 1 prescaler enabled
8
I1
O1
I2
O2
0
SR
X
0
0
0
X
0
0
0
X
0
0
0
X
0
1
0
X
0
0
0
X
BR1
1
RTS
X
BR0
0
0
X
PS
Read configuration register 2
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
BR1..0: LF data baud rate selector
PS: 0 CLKO prescaler disabled, 1 prescaler enabled
9
I1
O1
I2
O2
0
SR
X
0
0
0
X
0
0
0
X
IC
0
0
X
CH
1
0
X
OL
1
0
X
SH
1
RTS
X
SL
0
0
X
OT
Read status register
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
IC: illegal command received
CH: overcurrent in antenna footpoint detected
OL: open load detected
SH: overcurrent to VBATT detected at driver output
SL: overcurrent to GND detected at driver output
OT: overtemperature detected
10
I1
O1
I2
O2
0
SR
X
0
0
0
X
D6
0
0
X
D5
0
0
X
D4
0
0
X
D3
0
0
X
D2
1
RTS
X
D1
0
0
X
D0
Check free LF data buffer space
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
D6..0: free logical LF data bits in buffer
11
I1
O1
Ix
Ox
1
SR
HB7
B7
D6
0
HB6
B6
D5
0
HB5
B5
D4
0
HB4
B4
D3
0
HB3
B3
D2
0
HB2
B2
D1
RTS
HB1
B1
D0
0
HB0
B0
Write LF data to buffer and start modulator
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
D6..0: number of logical LF bits to be written into buffer
HB7..0: LF half bits (2 for one logical bit)
B7..0: input bit from the previous controller data word

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ATA5278
3.8 Command Description
Table 3-1 on page 10 summarizes the commands interpreted by the SPI control logic of the
ATA5278. Each command consists of one or more data words which the controller has to trans-
fer to the SPI of the ATA5278. An SPI data word is always eight bits in width and has to be
transferred starting with the least significant bit (LSB).
The following list contains detailed information on every command of the chip.
• The main purpose of command 1 is to check the operational status of the chip. Only if the
System-Ready bit (SR) and the Ready-To-Send bit (RTS) have been received as 1, the
ATA5278 is fully functional. In special cases, only the SR bit will be received as 1. This is
when the LF data buffer is full or when the power stages have been shut down due to a fault.
This command can be used at any time to check the status of the chip.
•Command 2 is the first out of three special function commands. It is used to reset the
internal fault memory. Once a fault is detected by the internal diagnosis stage, it is stored in
the fault memory (i.e., the status register) and the power stages are shut down to protect
them from damage. In order to enable the chip again, this command has to be sent to the IC.
•Command 3 can be used to stop the LF data transmission immediately. Regularly, the
modulator stage works as long as new (i.e., unsent) LF data is in the data buffer. When using
this command, all data in the buffer will be deleted and the antenna driver stage is switched
to idle mode.
•Command 4 has to be used to shut down the IC. In order to start the power-down sequence
properly, no further command must be transmitted to the chip and the chip-select line (S_CS)
has to be disabled afterwards.
•Command 5 is used to write configuration data into register 1, which is used for LF data
modulation control. All register access commands are of a 16-bit structure (i.e., two data
words). The first data word defines the access itself (i.e., read or write, and the register
number). The second data word is the configuration data, which is to be sent to the ATA5278.
Note that in return for the second data word, the first input data word is sent back to the
controller. This can be used to validate the SPI transmission. Register 1 contains the four-bit-
wide antenna coil current selector (IC3..IC0) and the modulation type selector bit
(NASK_PSK). For further details, please refer to the section “Current Adjustment” on page
19.
•Command 6 can be used to validate a change in register 1 (i.e., a prior command 5
operation) or to check its actual state after a power-down period. Like all register access
commands, it consists of two data words. The return data in the second data word has the
same bit sequence as in command 5.
•Command 7 writes configuration data to register 2, which handles timing relevant setup
information. Like all register access commands, it consists of two data words, where the
second one is the configuration data itself. Note that in return for the second data word, the
first input data word is sent back to the controller. This can be used to validate the SPI
transmission. Register 2 contains the two-bit-wide LF data baud-rate selector (BR1..BR0)
and the pin CLKO prescaler bit. For further details, please refer to the sections “LF Data
Modulation” on page 13 and “Clock Supply”.
•Command 8 can be used to validate a change of register 2 (i.e., a prior command 7
operation) or to check its actual state after a power-down period. Like all register access
commands, it consists of two data words. The return data in the second data word has the
same bit sequence as in command 7.

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ATA5278
• The status register of the ATA5278 can be read out with command 9. As soon as the internal
diagnosis stage detects a fault, it is stored in the status register until a fault reset command is
given or a power-on-reset occurs. Note that the power stages of the chip are disabled as long
as a power stage fault (i.e., a short-circuit at the driver stage output pin, open load,
overcurrent at the current sense pin or over temperature) is present in the status register.
Like all register access commands, it consists of two data words, where the return data in the
second data word contains the fault bits. For further details, please refer to the section “Fault
Diagnosis” on page 20.
•Command 10 accesses a special register, where the actual amount of free logical bits in the
data buffer is stored. This value decreases with each logical bit that is transferred to the
buffer, and increases with each logical bit the modulator stage fetches from the buffer in order
to transmit it via the LF channel. It can be used to determine the amount of data which can be
transferred to the buffer or to determine the actual modulation process. Like all register
access commands, it consists of two data words, where the second one contains the
six-bit-wide value.
•Command 11 is used to write LF data to the on-chip data buffer and to start the modulator
stage. This command is indicated by the most significant bit (MSB) of the first data word from
the controller, which is, in contrast to all other commands, 1. The other seven bits of this word
determine the amount of logical LF data to be written to the buffer. This amount of data has
then to be transferred from the controller to the ATA5278. As one logical bit consists of two
half bits, a maximum of four logical bits can be transferred per one SPI data word. With the
data buffer being able to store up to 96 logical bits, command 11 may reach a maximum
length of 25 SPI data words (i.e., the first word with the amount of data, followed by up to 24
words with the data itself). Note that the input data from the SPI input register is always read
out starting from the least significant bit (LSB), working towards the MSB. So if less than four
logical bits are transferred to the buffer, they have to be stored in the lower area of the SPI
data word (i.e., starting with the LSB). It is important that the number of actually transferred
LF data matches the amount given in the first word of this command, because there are no
consistency checks. This is even then the case if the data buffer was already full at the
beginning of the transmission, or got full during the transmission of LF data, or if the driver
stages are disabled due to a present fault. Data which is transferred under such
circumstances is not stored and therefore lost.
The SPI control logic checks the incoming data for valid commands. If the first data word trans-
mitted by the microcontroller does not match any of the above listed functions, an illegal
command fault is detected and written into the fault register. It can be read out with command 9,
bit 5 (IC). Note that this fault does not cause a shut down of the power stages.
3.9 LF Data Buffer
The ATA5278 features an 192-bit wide data storage intended to buffer LF data between the
microcontroller and the modulator stage. It can be filled with data via the SPI and therefore at
high speeds (i.e., up to 1 Mbit/s). The modulator stage then accesses this buffer with the
selected LF baud rate and controls the connected LF antenna accordingly. Hence the controller
can handle other tasks during the comparatively slow LF data transmission.
The data buffer is structured as a First-In-First-Out (FIFO) system, as can be seen in Figure 3-8
on page 13.

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ATA5278
Figure 3-8. Structure Of Internal Data Buffer
The buffer is structured into two parallel blocks with the same storage capacity. The reason for
this is that the LF data is handled as logical (e.g., Manchester coded) bits, where each data is
encoded by two so-called half bits. The minimum amount of data which can be written to or read
from the buffer is one logical bit, hence two half bits.
After activating the IC from power-down mode or any fault, the data pointer in Figure 3-8 is at the
lowest point of the buffer (i.e., bit 190/191). Any write operation will store the data to the position
the pointer is pointing at, and moves it upwards one position. The data is always read from the
lowest point of the buffer by the modulator stage. Any read operation will cause the data in the
buffer to drop down one position, including the data pointer. Any further writes are ignored if the
data pointer reaches the upper border of the buffer, and the LF modulator stage stops operation
after the pointer has reached the lower border.
3.10 LF Data Modulation
The LF modulator stage of the ATA5278 is fed with data from the LF data buffer. It is started
after a successfully received SPI command 11. Two half bits are loaded at a time and brought
sequentially to the driver control logic, starting with the half bit labeled lower in Figure 3-8. It is
applied for half the period time selected by the LF baud rate selector. Then the half bit labeled
upper is applied for the same time. The driver control stage generates a control signal for the
power output stages according to the input and the selected modulation mode. The IC has two
modulation modes, ASK and PSK. They are selected by the NASK_PSK bit (i.e., bit 0) in control
register 1. In ASK modulation mode (NASK_PSK = 0), the IC switches the carrier on and off
depending on the value of the half bit applied by the modulator stage, where 1 activates the car-
rier and 0 deactivates it. So if the carrier is to be activated for a certain time (i.e., continuous
wave), a corresponding amount of half bits have to be set to 1 in the LF data buffer. Figure 3-9
on page 14 illustrates this behavior.
Bit 0 Bit 1
Bit 2 Bit 3
Input register
4-1
MUX
MSB
6
5
4
3
2
1
LSB
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Bit 188 Bit 189
Bit 190 Bit 191
LF
modulator
stage
Data buffer
Lower
Upper
Upper
Lower
Data pointer

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ATA5278
Figure 3-9. LF Data Modulation with ASK
The LF data stream in Figure 3-9 has a length of four logical bits and therefore eight half bits. To
get this result, a hex value of 0F6h has to be written into the data buffer via the SPI. The time
value tBitrate is the period of one logical bit, which is defined by the selected data baud rate in
configuration register 2. Note that the MODACTIVE pin is active even if the half bit at the modu-
lator stage is “0”.
In PSK mode (NASK_PSK = 1), the phase of the carrier signal is shifted by 180° on any change
of the LF data in the buffer. Taking the same data sequence as in the previous example, the dia-
gram changes shown in Figure 3-10.
Figure 3-10. LF Data Modulation with PSK
Half bit
values
Driver control
input
Driver control
signal
Resulting
antenna
signal
MODACTIVE pin
X01101111
t
Bitlength
/2
t
Bitlength
Start of modulation
X
End of modulation
Half bit
values
Driver control
input
Driver control
signal
Resulting
antenna
signal
MODACTIVE pin
X01101111
t
Bitlength
/2
t
Bitlength
Start of modulation
X
End of modulation

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ATA5278
The carrier signal is now always on as long as the LF data is in the buffer. It is only at the change
of the LF data values that the phase of the antenna current is shifted by 180°. For further details,
please refer to the section “Driver Stage” on page 16.
An internal timer, derived from the system clock generates the modulation times for the half bits
applied to the driver stage. These times depend on the selected LF baud rate in configuration
register 2 (i.e., the bits BR0 and BR1). Table 3-2 lists the bit settings and their corresponding
timings.
Note that due to synchronization issues, the time for which the LF field is really active in ASK
mode when transmitting one half bit might vary by ±8 µs. This is a non-accumulating effect,
which means, the transmission time for the complete LF data stream may also vary by ±8 µs,
independent of the total amount of logical bits. The same is true for the distance of two phase
shifts when transmitting LF data in PSK mode.
If data rates above 2 kbauds are demanded or the PSK modulation mode is selected, the use of
an external antenna current loop switch is mandatory. This switch has to be controlled in a
defined way which is supported by the ATA5278. For further details on this topic, please refer to
the section “QSC Feature” .
3.11 QSC Feature
The Quick Start Control (QSC) feature supports a short oscillation build up and decay time dur-
ing LF data modulation. An external high-voltage MOS transistor is used as a switch to close
and open the current loop of the antenna. By synchronizing this switch to the zero-crossing
events of the antenna current, very short build-up and decay times for the LF field, and therefore
high data rates can be achieved.
Figure 3-11. QSC Operation
Table 3-2. LF Baud Rate Time Values
BR0 Bit
Setting
BR1 Bit
Setting
Selected
Baud Rate
Time for One
Half Bit
tBitlength/2
Time for One Logical Bit
tBitlength
0 0 1 kbaud 512 µs 1024 µs
1 0 2 kbaud 256 µs 512 µs
0 1 3 kbaud 160 µs 320 µs
1 1 4 kbaud 128 µs 256 µs
Half-bit from
data buffer
Voltage at
QSC pin
Current
through
antenna
Modulation in ASK mode Modulation in PSK mode

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ATA5278
The gate of the external transistor is driven by the QSC pin of the ATA5278. The signal provided
here is suited to drive standard MOSFETs (i.e., no logic-level FETs). During power-down mode
or a fault shutdown, the external transistor is switched off. Otherwise, this would lead to a con-
ducting state as long as no data modulation takes place. For further information on this pin,
please refer to the table “Electrical Characteristics” on page 27.
3.12 Driver Stage
The driver stage of the ATA5278 consists of following blocks:
• DMOS half-bridge antenna driver
• Switched Mode Power Supply (SMPS) in boost configuration
• Antenna current sensor for peak value and zero-crossing detection
All these blocks are controlled by the internal driver control logic. The antenna driver stage itself
is supplied by the boost converter output voltage, which is applied at the VDS pin. It consists of
two power NMOS transistors in half-bridge configuration. As the high-side transistor requires a
control voltage above the output voltage (i.e., a voltage above the supply voltage VDS), a boot-
strap configuration is implemented. This circuitry requires an external capacitor of 10 nF to
22 nF, connected between the driver output and the CBOOST pin. This capacitor is charged
during the time when the low-side transistor is active. As soon as the low-side transistor is
switched off and the high-side transistor starts conducting, both the voltage at the DRV1 pin and
the CBOOST pin rises, but always with CBOOST being higher than DRV1 and hence being able
to provide an appropriate control voltage for the transistor. Figure 3-12 illustrates this boot strap-
ping configuration.
Figure 3-12. Bootstrap Configuration Circuitry
The output signal of the antenna driver stage is of a square wave shape. The duty cycle of this
signal is dependant on the selected antenna current. For further details, please refer to the sec-
tion “Current Adjustment” on page 19.
VDS
HS transistor
LS transistor
AGND
DRV1
CBOOST
Charge supply
voltage
High side driver
control signal
Low side driver
control signal

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ATA5278
The antenna driver stage and the boost converter are thermally monitored in order to protect
them from overheating, and the output pin DRV1 is short-circuit protected by means of current
limitation. For further details, please refer to the section “Fault Diagnosis” on page 20.
The current sensor system is equipped with a zero-crossing detector and a sample and hold
stage. The zero-crossing detector provides the synchronization signal for the driver control logic,
which then calculates the phase shift between the antenna driver output signal and the current
flowing through the antenna. Based on this phase information, the sample and hold stage is con-
trolled in order to sample the top point of the input signal, hence the peak current value.
3.13 Current Regulation
A main feature of the ATA5278 is its ability to generate a stabilized magnetic field with a con-
nected LC antenna, mainly independent of the battery voltage and the frequency mismatch
between the driver output frequency and the antenna resonance frequency.
Figure 3-13. Antenna Current Regulation Loop
The input signal for the regulation loop in Figure 3-13 is the selected antenna current, which is
defined in configuration register 1. An external shunt resistor of 1Ω, which has to be connected
to the VSHUNT pin, is used to measure the current in the LC antenna. As the peak voltage over
this resistor is directly linked with the peak current in the antenna and hence the magnetic field
strength, this value can be seen as output. This signal is sampled and held by an internal stage
controlled by the control logic. The difference of the input signal and the sampled signal then
controls an integrator. The parameter of this stage can be influenced with an externally applied
charging capacitor connected to the CINT pin. The charging/discharging behavior of the integra-
tor stage is described in Figure 3-14 on page 18.
Selected
current
CINT
+Boost
converter
VBAT
T
VSHUN
T
Current
sample
and
hold
-
VDS DRV1
Integrator DMOS half
bridge
LC-antenna

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ATA5278
Figure 3-14. Integrator Output Current on CINT Pin
As can be seen in Figure 3-15 on page 21, a current is charged into, respectively discharged
from the external capacitor depending on the voltage at the VSHUNT pin. Note that the shown
values for VSHUNT are only valid if maximum antenna current (i.e., 1 Apeak when using a shunt
resistor of 1Ω) is selected. When the input voltage reaches the desired value (e.g., 1V), no cur-
rent is flowing through the CINT pin and the voltage over the capacitor is not changing. This
voltage influences the output voltage of the boost converter. Note that the lower the voltage on
the integration capacitor, the higher the output voltage of the boost converter will be. The maxi-
mum output voltage is 40V.
3.14 Boost Converter
The ATA5278 provides the supply current for its driver stage by means of a Switch Mode Power
Supply (SMPS) in boost configuration. A low-side switch that charges the inductor, and the
therefore needed control circuitry is integrated. The other necessary components such as the
inductor, the free-wheeling diode and the charging capacitor have to be applied externally. For
further details, please refer to the section “Application Hints” on page 22.
The SMPS control circuitry is in current-mode configuration. This means that the current through
the coil charging transistor (i.e., the current through the VL1..3 and the PGND1..3 pins) is mea-
sured and compared to a reference current in each switching period. Should the measured value
exceed the reference value, the transistor is switched off and the inductor then discharges its
energy through the free-wheeling diode to the charging capacitor. The reference current is gen-
erated from the voltage on the CINT pin, hence the integrator output voltage.
-30,0
-20,0
-10,0
0,0
10,0
20,0
30,0
0,5 0,6 0,7 0,8 0,9 1,0 1,1 1,2 1,3 1,4
Voltage at VSHUNT pin (V)
Current at CINT pin (µA)

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ATA5278
3.15 Current Adjustment
The maximum reachable output current in the antenna circuit can be calculated as follows:
Here, VDRV is the maximum reachable driver voltage and Z the antenna’s impedance (including
the RDSon of the QSC MOSFET, the shunt resistor and the driver output resistance). Note when
calculating the amount of complex Z, that the antenna driver output frequency (i.e., f = fOSC/64)
has to be taken into account for the complex parts of the impedance.
The antenna coil current can be adjusted in 16 steps by modifying the IC0..IC3 bits in the config-
uration register 1. Dependent on the selected current, the duty cycle of the antenna coil driver
signal is adapted. This improves the possibility to use one and the same antenna over the whole
range of selectable output currents. Table 3-3 provides a list of the current settings for all 16
steps.
Table 3-3. Current Settings
Step Current [mA] IC0 IC1 IC2 IC3 P/P ratio
1I
maximum/3.59700001.25/6.75
2I
maximum/3.22610001.25/6.75
3I
maximum/2.97601001.25/6.75
4I
maximum/2.60411001.25/6.75
5I
maximum/2.35300101.75/6.25
6I
maximum/2.13210101.750/6.25
7I
maximum/1.98401101.75/6.25
8I
maximum/1.82511101.75/6.25
9I
maximum/1.7090001 2.5/5.5
10 Imaximum/1.57 1001 2.5/5.5
11 Imaximum/1.4560101 2.5/5.5
12 Imaximum/1.3611101 2.5/5.5
13 Imaximum/1.2560011 4/4
14 Imaximum/1.1631011 4/4
15 Imaximum/1.0810111 4/4
16(1) Imaximum 1111 4/4
Note: 1. Default
I
ant,eff
VDRV 2×
πZ×
-----------------------------
A
=

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ATA5278
3.16 Fault Diagnosis
The IC contains several fault diagnosis systems to protect itself from destruction and to provide
diagnosis information. If a fault at the power stages is detected for a certain debounce time, both
the switch mode power supply and the antenna driver stage including the external NMOS tran-
sistor (if present) are switched off and the corresponding fault information is written into the
status register. Also the LF data buffer is cleared. The fault information can be read out with SPI
command 9. In order to restart the operation of the power stages, the status register has to be
cleared by transmitting SPI command 2.
The following protection and diagnosis mechanisms are defined:
• A temperature monitoring system detects critical junction temperatures. Once detected, the
debounce timer is started. If the temperature is still above the critical limit after the
debouncing time has passed, a fault shutdown is performed.
• A short-circuit protection of the antenna driver output is realized by means of internal
shunt-voltage monitoring. Both the high-side and the low-side transistors are equipped with a
shunt resistor which provides information about the current flowing through them. If the
current through one of the transistors surpasses the internally defined overcurrent level, a
current limitation is invoked immediately and the debounce timer is started. Should this
condition persist for the whole debouncing time, a fault shutdown is performed.
• The current through the external high-voltage MOSFET is monitored in order to detect short-
circuits on the return line of the antenna. Like for the other faults, a debounce timer is started
as soon as an overcurrent situation is detected and a fault shutdown is performed after this
time has passed.
• The signal at the VSHUNT pin is monitored while the driver stage is active in order to detect
a broken antenna connection (i.e., an open load failure). The monitor searches for polarity
changes in the signal and starts the fault debouncing timer if it fails to find such changes. A
fault shutdown is performed if this fault persists for the whole debouncing time.
• The input register of the SPI is scanned for illegal commands. Note that this kind of fault will
cause neither a shutdown of the power stages nor a clearing of the LF data buffer. This
diagnosis function is just to provide information about problems on the SPI bus. Also, no
debouncing time is applied for this fault.
Some faults, like open load or a short-circuit of the antenna output pin to ground, can only be
detected while the driver stage is active (i.e., in modulation mode). As the low-side antenna
driver transistor and the QSC transistor are also both active in standby mode, faults concerning
these devices are also monitored then. Only during power-down, no fault monitoring is active.
Figure 3-15 on page 21 illustrates the fault shutdown timing sequence.