Atmel AViiVA SC2 User manual

1
Features
•High Sensitivity and High SNR Performance Linear CCD Sensor
•Monoline 1365 RGB Patterns (Total of 4096 Active Pixels)
•Built-in Anti-blooming, No Lag
•CameraLink™Data Format (Base Configuration)
•High Data Rate up to 60 Mpixels/s
•Flexible and Easy to Operate via Serial Control Lines:
– Exposure Time: 1 to 32,000 µs
– Gain: -2 dB to 22 dB by Steps of 0.035 dB
– Color Correction
– Trigger Mode: Free Run or External Trigger Modes
– Output Format: Serial (8/10/12 Bits) or Parallel RGB
– Digital Offset and Gain (For Contrast Expansion)
•Flat-field Correction (Lens and Light Non-uniformity, FPN and PRNU Correction)
•Multi-camera Synchronization
•Single Power Supply: DC 12 to 24V
•Very Compact Design: 56 x 60 x 39.4 mm (w, h, l)
•High Reliability – CE and FCC Compliant
•F (Nikon), T2 or M42 x 1 Mount Adapter (Lens Not Supplied)
Description
This smarter C2 is the perfect alternative for users looking for a cost-effective color
linescan camera. The Aviiva SC2 takes advantage of all the features that made the
success of the Aviiva family: accuracy, versatility and easy implementation:
• Flat-field correction and contrast expansion functions.
• Embedded white balance and color space correction.
• A very compact mechanical design that incorporates a 4k color linear sensor.
• Atmel manages the entire manufacturing process from the sensor to the camera.
The result is a camera able to operate in 8, 10 or 12 bits with dedicated
electronics offering an excellent signal-to-noise ratio.
• Programmable settings let the user work at different integration times, gains and
offsets. The external clock and trigger allow synchronization of several cameras.
Applications
The performance and reliability of this camera make it suitable for machine vision
applications requiring low-cost color capture. Such applications can include print,
packaging inspection or part sorting. With this camera, one avoids the usual problems
observed with tri-linear sensors on optical alignment and object synchronization.
CameraLink™
Color Linescan
Camera
AViiVA™SC2
Preliminary
5373A–IMAGE–03/04

2AViiVATM SC2 [Preliminary] 5373A–IMAGE–03/04
Typical Performances
Notes: 1. LSBs are given for a 12-bit configuration (available in serial RGB)
2. nJ/cm² measured on the sensor with 2 mm BG38
3. Camera’s front face temperature
Table 1. Typical Performances
Parameter Value Unit
Sensor Characteristics at Maximum Pixel Rate
Resolution 1365 RGB patterns or 4096 pixels pixels
Pixel pitch 10 µm
Maximum line rate 14 kHz
Anti-blooming x 150 –
Radiometric Performances (Maximum Pixel Rate, Tamb = 25°C)
Dynamic range 12 (also configurable in 8 or 10) bit
Spectral range 250 – 1100 nm
Linearity (G = 0) < 2 %
Gain range (steps of 0.035 dB) Gmin
-2 Gnom 0Gmax 22 dB
Peak response(1)(2)
Blue
Green
Red
16.6
24.2
31.3
21.5
31.5
41
263
383
496
LSB/(nJ/cm2)
LSB/(nJ/cm2)
LSB/(nJ/cm2)
Output RMS noise
SNR 66 64 42 dB
PRNU (Photo Response Non Uniformity ± 4 (± 15 max) %
Mechanical and Electrical Interface
Size (w x h x l) 56 x 60 x 39.4 mm
Lens mount F, T2, M42 x 1 –
Sensor alignment (See “Sensor Alignment” on page 20) ∆x,y = ±50 – ∆z = ±30 – ∆tiltz= 0-35
∆θx,y = ±0.2 µm °
Power supply DC, single 12 to 24 V
Power dissipation < 6.5 W
Operating temperature(3) 0 to 65 (non-condensing) °C
Storage temperature -40 to 75 (non-condensing) °C
Spectral Response(1)(2)
0
5
10
15
20
25
30
35
400 450 500 550 600 650 700
Responsivity LSB/(nJ/cm²)
Wavelength (nm)
R
G
B

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AViiVATM SC2 [Preliminary]
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Color Principle
CCD Description The color CCD sensor is based on a 2 taps, 4096 pixels linear sensor with an RGB color filter.
It outputs 1365 RGB patterns (plus 1 extra red pixel).
Figure 1. Color CCD Sensor Synoptic
IR Cut-off Filter For calibrated color response, the AViiVA SC2 sensor should not be exposed to IR wave-
lengths (> 700 nm). Therefore, depending on the light source, one should decide whether or
not to place an IR cut-off filter in front of the sensor. The AViiVA SC2 sensor has been cali-
brated with a 2 mm BG38. The AViiVA SC2 is available with or without a 2 mm BG38 (refer to
“Ordering Codes” on page 21).
White Balance A white balance function is implemented in the camera. White balance can be performed auto-
matically (white balance calibration) or manually.
The color filters are balanced for a typical 5500°K light source with a 2 mm BG38. White bal-
ance should be performed for each light source. For example, with a 3200°K light source and
with a 2 mm GB38, the following typical gains must be applied to white balance the image.
Color Space
Correction A color space correction function is also implemented in the camera. The nine coefficients can
be input manually or chosen in a typical matrix.
After white balance, the color space correction should be done to improve color response.
This correction consists of a linear operation to convert the RGB triplet from the camera’s color
space to the RGB triplet of the final color space. The final color space can be a monitor, a
printer or another application’s specific color space. For some specific applications where an
"absolute" color value is not mandatory, the color space correction can be bypassed.
At 3200K with a 2 mm BG38 and for a standard PC screen, the following typical matrix must
be applied to correct the colors.
G1R1 B1 R2 G2 B2 B1364R1365 G1365B1365 R1366R3 RGB color pixels
R1
G1
B1 G2 R1
R2 B2 B1364 G1365 R1366
R1365 B1365Storage area
Storage area
EVEN pixels CCD shift register
ODD pixels CCD shift register
VOS1
VOS2
R′
G′
B′
1
1.64
2.89
RGB
×=
R″
G″
B″
1.14 0.26 0.4–
0.19–1.71 0.52–
0.45–0.65–2.1
R′
G′
B′
×=

4AViiVATM SC2 [Preliminary] 5373A–IMAGE–03/04
Camera Description
Figure 2. Camera Synoptic
The camera is based on a two-tap linear CCD. Therefore, two analog chains process the odd
and even pixel outputs of the linear sensor. The CCD signal processing encompasses the cor-
related double sampling (CDS), the dark level correction (dark pixel clamping), gain (PGA)
and offset correction and finally the analog-to-digital conversion in 12 bits. An FPGA has been
implemented for image processing (flat-field correction, dynamic selection, test pattern gener-
ation and color correction).
Note: PGA stands for Programmable Gain Array.
The camera is powered by a single DC power supply from 12 to 24V.
The functional interface (data and control) is provided with the CameraLink™interface. The
camera uses the base configuration of the CameraLink standard.
Note: FVAL = 0
In RGB serial mode, the data format can be configured in 8, 10 or 12 bits. See “Output Timing
Data” on page 10.
In RGB parallel mode, data is provided on three channels corresponding to red, green and
blue information. The data format is output in 8 bits only.
The camera can be used with external triggers (TRIG1 and TRIG2 signals) in different trigger
modes (see “Synchronization Mode” on page 8). The camera can also be clocked externally,
enabling system synchronization and/or multi-camera synchronization.
The following configurations and settings are done via a serial line.
• Gain and offset
• Dynamic range, data rate setting and RGB mode
• Trigger mode setting: free-run or external trigger modes
• Integration time setting: in free-run and external trigger modes
Linear CCD
2 taps
CCD drivers
Even pixels analog chain
PGA, CDS, ADC
12-bit at 30 Mpixels/s
Odd pixels analog chain
PGA, CDS, ADC
12-bit at 30 Mpixels/s
Microcontroller
CameraLink
transceiver
TX
RX
Power supplies
DC power
CameraLink
I/F
Sequencer
controller
DATA
Serial line
TRIG1,
TRIG2
STROBE,
LVAL
CLOCK_IN
Image
processing

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AViiVATM SC2 [Preliminary]
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Standard
Conformity The Aviiva cameras have been tested using the following equipment:
• A shielded power supply cable
• A CameraLink data transfer cable ref. 14B26-SZLB-500-OLC (3M™)
• A linear AC-DC power supply
Atmel recommends using the same configuration to ensure compliance with the standards
described hereafter.
CE Conformity All AViiVA cameras comply with the requirements of the EMC (European) directive
89/336/CEE (EN 50081-2, EN 61000-6-2)
FCC Conformity All AViiVA cameras further comply with part 15 of the FCC rules, which state that:
Operation is subject to the following two conditions:
• This device may not cause harmful interference, and
• This device must accept any interference received, including interference that may cause
undesired operation.
This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable
protection against harmful interference when the equipment is operated in a commercial envi-
ronment. This equipment generates, uses and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference
to radio communications. Operation of this equipment in a residential area is likely to cause
harmful interference, in which case the user will be required to correct the interference at his
own expense.
Warning: Changes or modifications to this unit not expressly approved by the party responsi-
ble for compliance could void the user's authority to operate this equipment.

6AViiVATM SC2 [Preliminary] 5373A–IMAGE–03/04
Camera Command and Control
The camera is configured through the serial interface. Please refer to “Serial Communication”
on page 15 for the serial line’s detailed protocol.
Table 2. Camera Command and Control
Setting Command Parameter Description
Gain(1) G= -65 to 643 Gain setting from -2 to 22 dB (~0.035 dB steps)
Even gain(1) A= 0 to 56 Even pixels gain adjustment (odd – even mismatch adjustment)
Odd gain(1) B= 0 to 56 Odd pixels gain adjustment (odd – even mismatch adjustment)
Red gain J 0 to 63 Red gain setting from 0 to 12 dB (~0.19 dB steps)
Green gain K 0 to 63 Green gain setting from 0 to 12 dB (~0.19 dB steps)
Blue gain L 0 to 63 Blue gain setting from 0 to 12 dB (~0.19 dB steps)
Data transfer(2) H=
0
1
2
3
4
5
6
External clock (data rate = 2 x external clock)(7)
External clock (data rate = external clock)
External clock (data rate = external clock/2)
20 MHz data rate
30 MHz data rate
40 MHz data rate
60 MHz data rate
Output format(3) S=
0
1
2
3
RGB parallel mode (3 x 8 bits)
RGB serial mode/8 bits
RGB serial mode/10 bits
RGB serial mode/12 bits
Image source(4) T= 0
1
2
Sensor raw image
Test pattern
Sensor corrected image (flat-field correction enabled)
Color matrix(8)
CRR=
CRG=
CRB=
CGR=
CGG=
CGB=
CBR=
CBG=
CBB=
-512 to +511
-512 to +511
-512 to +511
-512 to +511
-512 to +511
-512 to +511
-512 to +511
-512 to +511
-512 to +511
Correspond to a -4 - +4 gain coefficient
(gain coefficient = parameter/128)
Color matrix storage -M= 1 to 4 Stores the active matrix in the “user matrix 1 to 4”
Configuration recall +C= 0
1 to 4 Restores the default configuration Restores the user configuration 1 to 4
Configuration storage -C= 1 to 4 Stores the user configuration 1 to 4
FPN recall +F= 1 to 4 Restores the FPN factors from the FPN banks 1 to 4
FPN storage -F= 1 to 4 Stores the active FPN factors in FPN banks 1 to 4
PRNU recall +P= 1 to 4 Restores the PRNU factors from the PRNU banks 1 to 4
PRNU storage -P= 1 to 4 Stores the active PRNU factors in the PRNU banks 1 to 4

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AViiVATM SC2 [Preliminary]
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Notes: 1. The camera gain (dB) = G x 0.0353. A and B gain values are set during manufacturing but can be adjusted if necessary.
2. The CameraLink standard does not allow working below a 20 MHz clock frequency..
3. The pinout corresponding to this option is fully compatible with the CameraLink standard (See “Electrical Interface” on page 14.).
4. The test pattern is useful for checking if the device is correctly interfaced. The user should see a jagged image of 256 pixels steps.
5. The offset is set during manufacturing to balance both channels. The initial setting is about 13 LSB. In some cases, the user may have to
change this setting (for example if the ambient temperature is very high).
6. LSBsare given for 12-bit configurations (available in serial RGB).
7. To be used for multi-camera synchronization. Refer to the “Output Timing Data” on page 10 for details.
WB recall +W= 1 to 4 Restores the white balance factors from WB banks 1 to 4
WB storage -W= 1 to 4 Stores the active white balance factors in WB banks 1 to 4
Color matrix recall +M=
1 to 4
5
6
7
8
Apply “user matrix 1 to 4”
Apply typical matrix for 3200K light
Apply typical matrix for 5500K light
Apply typical matrix for 6400K light
Apply typical matrix for “white LED” light
Color space correction
matrix N= 0
1Disable Enable
Integration time I= 1 to 32768 Integration time (µs) in free-run or external triggered mode
Trigger mode M=
1
2
3
4
Free run with integration time setting (see Figure 3 on page 8)
External trigger with integration time setting
Trigger and integration time controlled
Trigger and integration time controlled by two inputs
Even data offset(5) O= 0 to 255 Even offset setting from 0 to 255 LSB(6)
Odd data offset(5) P= 0 to 255 Odd offset setting from 0 to 255 LSB(6)
Contrast expansion Q=
R= -4096 to 4095
0 to 255 Digital offset in LSB/12 bits Digital gain x1 to x33 (0.125 steps)
Write FPN(12) WFP= Send FPN valuess
Read FPN(13) RFP= Read FPN values
Write PRNU(12) WPR= Send PRNU values
Read PRNU(13) RPR= Read PRNU values
Special commands !=
0
1
2
3
4
5
6
7
8
9
Camera identification readout
User camera identification readout
Software version readout
Camera configuration readout
Status readout
Start FPN calibration(9)
Start PRNU calibration(10)
Start “white balance” calibration(11)
Software version readout
Abort calibration
User camera ID $= String of Char. Write user camera identification (50 characters maximum)
Table 2. Camera Command and Control (Continued)
Setting Command Parameter Description

8AViiVATM SC2 [Preliminary] 5373A–IMAGE–03/04
8. Matrix coefficients
9. Switch off all lights before starting the FPN (dark) calibration. This calibration must be done before the PRNU calibration.
10. Place a white reference in front of the camera before starting the PRNU (white light) calibration. The light level must be between half and full
dynamic range.
11. Place a white reference in front of the camera before starting the white balance calibration. This calibration must be done before FPN and
PRNU calibrations.
12. Parameter format: <addr><size><value><value>...
<addr> = pixel number
<size> = amount of data sent
<value> = parameter value (0 to 255 for FPN [0 to 255 LSB]; 0 to 16383 for PRNU [x1 to x2 gain])
Parameters are sent from <addr> to <addr> + 5 pixels maximum
13. Parameter format: <addr><size>
Timing
Synchronization
Mode Four different modes may be defined by the user. The TRIG1 and TRIG2 signals may be used
to trigger external events and control the integration time. The master clock is either an exter-
nal or internal clock. The timing is given for maximum frequency settings.
Free-run Mode with Integration Time Setting
The integration and readout periods start automatically and immediately after the previous
period. The readout time depends on the number of pixels and the pixel rate.
Note: 1. The integration time is set by the serial line and should be higher than the readout time (oth-
erwise it is adjusted to the readout time).
Figure 3. Timing Diagram
R″
G″
B″
CRR CRG CRB
CGR CGG CGB
CBR CBG CBB
R′
G′
B′
×=
Table 3. Free Run Mode with Integration Time Setting
Label Description Min Typ Max
ti Integration time duration (1) – 32 ms
tg Consecutive integration period gap (at maximum
frequency) –6µs–
tt Integration period stop to readout start delay – 1 µs –
Integration N
Readout N-1 Readout N
Integration N+1
tt
ti
tg

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AViiVATM SC2 [Preliminary]
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Triggered Mode with Integration Time Setting
The integration period starts immediately after the rising edge of the TRIG1 input signal and is
set by the serial line. This period is immediately followed by a readout period. The readout
time depends on the number of pixels and the pixel rate.
Figure 4. Timing Diagram
Trigger and Integration Time Controlled by One Input
The integration period starts immediately after the falling edge of the TRIG1 input signal, stops
immediately after the rising edge of the TRIG1 input signal, and is immediately followed by a
readout period. The readout time depends on the pixel rate.
Figure 5. Timing Diagram
Table 4. Triggered Mode with Integration Time Setting
Label Description Min Typ Max
ti Integration time duration 1 µs – 32 ms
td TRIG1 rise to integration period start delay – <1 µs –
tt Integration period stop to readout start delay – 1 µs –
ts Integration period stop to TRIG1 rise setup time 4 µs – –
th TRIG1 hold time (high pulse duration) 0.1 µs – –
Integration N Integration N+1
Readout N
TRIG1
td th
ts
tt
ti
Table 5. Trigger and Integration Time Controlled by One Input
Label Description Min Typ Max
ti Integration time duration 1 µs – –
td1 TRIG1 falling to integration period start delay – 100 ns –
td2 TRIG1 rising to integration period stop delay – 1.3 µs –
tt Integration period stop to readout start delay – 1 µs –
th TRIG1 hold time (high pulse duration) 0.1 µs – –
Integration N
Readout N-1 Readout N
Integration N+1
th ti
tt
td1 td2
TRIG1

10 AViiVATM SC2 [Preliminary] 5373A–IMAGE–03/04
Trigger and Integration Time Controlled by Two Inputs
The TRIG2 signal’s rising edge starts the integration period and the TRIG1 signal’s rising edge
stops the integration period. This period is immediately followed by a readout period.
Figure 6. Timing Diagram
Output Timing
Data This timing data corresponds to the input data of the “Channel Link” interface. The camera’s
output data is not detailed here as it is fully compliant with the CameraLink standard (serial
high-speed interface).
Serial RGB Mode In this mode, the pixels are output on a single tap as they are implemented on the sensor. The
data format can be configured in 12, 10 or 8 bits (Y command) and the test pattern can replace
the CCD data (T command).
Note: The CLK_IN frequency must be in the range of 5 to 60 MHz. Outside this range, performances
may be degraded.
In this mode, the STROBE frequency is equal to CLK_IN or to the internal clock frequency and
DLVAL is always set to 1.
Table 6. Trigger and Integration Time Controlled by Two Inputs
Label Description Min Typ Max
ti Integration time duration 1 µs – –
td1 TRIG2 rise to integration period start delay – 100 ns –
td2 TRIG1 rise to integration period stop delay – 1.3 µs –
tt Integration period stop to readout start delay – 1 µs –
th TRIG1 and TRG2 hold time (high pulse duration) 0.1 µs – –
td1 td2
ti
tt
Integration N Integration N+1
Readout N-1 Readout N
TRIG1
TRIG2
Table 7. Serial RGB Mode
Label Description Min Typ Max
tp Input falling edge to output clock propagation delay – 7 ns –
td STROBE to synchronized signal delay -5 ns – +5 ns