Atmel ATPL250A User manual

ATPL250A
PANCoordinator-EK Kit User Manual
USER GUIDE
Atmel-43106C-ATPL- PANCoordinator-EK Kit User Manual-UserGuide_06-Oct-16

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Introduction
This PANCoordinator Evaluation Kit (EK) comprises all necessary resources to develop a complete
G3-PLC PANCoordinator. It implements an Atmel®Cortex™-M7 device acting as MCU host, combined with
ATPL250A modem for PLC (Power Line Communication). ATPL250A is a power line communications base
band transceiver, compliant with the PHY layer of G3-PLC specification.
G3-PLC is a mature, consolidated and worldwide accepted standard for OFDM-based power line
communications, with focus on providing Smart Grid services over electricity distribution networks.
This guide describes how to use the kit and get start with it.
Contents
Welcome letter introducing the evaluation kit and
its contents.
Boards:
One ATPL250ABNv2 board.
One ATPLCOUP007v2.5 coupling
board (CEN-A frequency band).
One ATPLCOUP002v2 coupling
board (ARIB frequency band).
One ATPLCOUP006v2 coupling
board (FCC frequency band).
Cables:
One micro A/B-type USB cable.
One power cord cable IEC320-C8.
Jumpers:
One voltage jumper with pitch 5.08
mm.
One erase jumper with pitch
2.54mm.
Features
ATPL250A is a compact and high-efficient device for a wide range of Smart Grid applications such as
Smart Metering (Smart Meters and Data Concentrators), Lighting, Industrial/Home Automation,
Home and Building Energy Management Systems, Solar Energy and Plug-in Hybrid Electric Vehicle
(PHEV) Charging Stations.
ATPL250A G3-PLC device includes enhanced features such as additional robust modes and
frequency band extension.
ATPL250A has been conceived to be bundled with an external Atmel MCU. ATPL250ABN PAN
Coordinator board mounts the ATPL250A transceiver and a SAME70 ARM Cortex M7
microcontroller. This development board provides a full featured platform to develop a complete
communications system based on Power Line Communication technology, providing support for:
–PLC band characterization.
–Noise level measurement.
–Sensitivity level measurement.
–Maximum reachable distance.
–Power consumption.
–Check PLC performance in different bands (CENELEC, FCC, ARIB) setting different PLC
coupling boards (provided with this evaluation kit).
–The EK board can be supplied with universal 115-230 VAC 50-60 Hz power input.
–The EK boards include a JTAG interface for MCU debugging and programming purposes, a
UART for debugging purposes, as well as Ethernet connectivity.

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Software application examples available based on G3-PLC Stack:
–Atmel provides an Atmel G3-PLC PHY layer library which is used by the external MCU to take
control of ATPL250A PHY layer device. Three G3-PLC PHY layer example projects are
provided with the kit.
–Atmel G3 Stack (ADP + MAC + PHY) for PAN Coordinator with some user applications is
provided with the EK.

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Table of Contents
1. Evaluation Kit Specifications......................................................................................7
1.1 Safety recommendations.......................................................................................................................7
1.2Electrical characteristics........................................................................................................................7
2. Evaluation Kit Overview..............................................................................................9
2.1 Design support......................................................................................................................................9
2.2 PANCoordinator-EK contents................................................................................................................9
3. ATPL250ABN Hardware.............................................................................................13
3.1 Overview .............................................................................................................................................13
3.2 Features..............................................................................................................................................13
3.3 Block diagram......................................................................................................................................16
3.4 Mechanical and user considerations ...................................................................................................16
3.5 Hardware description ..........................................................................................................................17
3.5.1 Power supply..........................................................................................................................17
3.5.2 Zero crossing detector............................................................................................................18
3.5.3 SAME70Q21 Flash microcontroller.........................................................................................18
3.5.4 ATPL250A PLC Transceiver...................................................................................................19
3.5.5 PLC Coupling..........................................................................................................................20
3.5.6 Peripherals..............................................................................................................................22
3.5.7 Interface Ports ........................................................................................................................23
4. ATPLCOUP007 Hardware..........................................................................................26
4.1 Overview .............................................................................................................................................26
4.2 Features..............................................................................................................................................26
4.3 Mechanical and user considerations ...................................................................................................27
4.4 Hardware description ..........................................................................................................................27
5. ATPLCOUP002 Hardware..........................................................................................28
5.1 Overview .............................................................................................................................................28
5.2 Features..............................................................................................................................................28
5.3 Mechanical and user considerations ...................................................................................................29
5.4 Hardware description ..........................................................................................................................29
6. ATPLCOUP006 Hardware..........................................................................................30
6.1 Overview .............................................................................................................................................30
6.2 Features..............................................................................................................................................30
6.3 Mechanical and user considerations ...................................................................................................31
6.4 Hardware description ..........................................................................................................................31
7. PAN Coordinator Evaluation Kit: Getting started....................................................32
7.1 Introduction to the embedded system .................................................................................................32
7.1.1 IAR Embedded Workbench ....................................................................................................32
7.1.2 Keil µVision.............................................................................................................................32
7.1.3 Atmel Studio 6 ........................................................................................................................32
7.1.4 Atmel SAM-ICE JTAG Probe..................................................................................................33
7.1.5 J-Link / SAM-ICE JTAG Probe Software & Documentation Pack...........................................33
7.1.6 Atmel Software Framework (ASF)..........................................................................................35
7.2 PLC application example 1 –PHY Tester ...........................................................................................36

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7.2.1 Atmel PLC PHY Tester tool Installation ..................................................................................37
7.2.2 Supplying the boards..............................................................................................................39
7.2.3 USB connection......................................................................................................................40
7.2.4 Programming the embedded file.............................................................................................41
7.2.5 Running the PLC application example 1.................................................................................43
7.3 PLC application example 2 –PHY TX Test Console...........................................................................55
7.3.1 Supplying the boards..............................................................................................................56
7.3.2 USB connection......................................................................................................................56
7.3.3 Programming the embedded file.............................................................................................56
7.3.4 Running the PLC application example 2.................................................................................57
7.4 PLC application example 3 –PHY Sniffer...........................................................................................61
7.4.1 ATPL Multiprotocol Sniffer tool Installation.............................................................................62
7.4.2 Supplying the boards..............................................................................................................64
7.4.3 USB connection......................................................................................................................64
7.4.4 Programming the embedded files...........................................................................................65
7.4.5 Running the PLC application example 3.................................................................................65
7.5 Introduction to G3 Stack......................................................................................................................68
7.5.1 FreeRTOS ..............................................................................................................................68
7.5.2 ASF Integration.......................................................................................................................69
7.5.3 Atmel G3-PLC Stack Structure...............................................................................................70
7.6 PLC application 4 –PLC Network.......................................................................................................72
7.6.1 Supplying the boards..............................................................................................................72
7.6.2 USB connection......................................................................................................................72
7.6.3 Programming the embedded files...........................................................................................72
7.6.4 Running the PLC application example 4.................................................................................74
8. References .................................................................................................................77
Appendix A Board schemes.........................................................................................78
A.1 ATPL250ABNv2 Schemes ..................................................................................................................78
A.2 ATPLCOUP007v2.5 schemes.............................................................................................................85
Revision History................................................................................................................88

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Icon Key Identifiers
Useful Tips and Techniques
Delivers Contextual Information About a Specific Topic
Note to Quality and Performance
Objectives to be Completed
Actions to be Executed Out of the Target
The Expected Result of an Assignment Step
Procedure Which Can Result in Minor Equipment Damage
Procedure With Potential Equipment Damage
Procedure With Imminent Equipment Destruction

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1. Evaluation Kit Specifications
1.1 Safety recommendations
These development boards must be only used by expert technicians. ATPL250ABN is directly powered
from mains grid, so hazardous voltage (100/230VAC) is present on the board. To avoid user access to
dangerous parts, ATPL250ABN must always be used within its enclosure. All required connectors and
configuration jumpers are easily accessible without electrical shock risk.
A normal use of ATPL250ABN does not require removing the enclosure
cover. If this action is necessary, it must be performed by qualified staff
after being sure that mains connection has been previously removed.
Be careful it is only for indoor use.
This development board does not have any switch on mains connection to switch on or off it. It must always
be connected to an easy accessible mains socket.
Do not connect any probe to high voltage sections if the board is not isolated from the mains supply to avoid
damaging of measurement instruments.
Coupling boards’ kits are shipped in a protective anti-static package.
The boards system must not be subjected to high electrostatic
discharge.
We strongly recommend using a grounding strap or similar ESD
protective device when handling the board in hostile ESD
environments (offices with synthetic carpet, for example) without
enclosure. Avoid touching the component pins or any other metallic
element on the board.
ATPL250ABN is a CE mark product which passes EN60950-1 safety standard, EN50065-1, EN50065-2-3,
EN50065-7 EMC and FCC (as current carrier system) standards. It also satisfies Pb-Free and ROHS
directive.
ATMEL does not assume responsibility for the consequences arising
from any improper use of this board.
Boards’ kits are intended for further engineering, development, demonstration, or evaluation purposes only.
It is not a finished product except as may be otherwise noted on the board/kit.
1.2 Electrical characteristics
This section shows the electrical characteristics of the kit’s boards. See the following tables:
Table 1-1. Power Supply Requirements.
Parameter
Condition
Min.
Typ.
Max.
Unit
AC mains Voltage Range
100
115/230
250
VAC
Mains Frequency
50/60
Hz
Maximum Input Current
200(1)
mA
Isolation Voltage
ACDC power supply and PLC coupling transformer
3000
VAC

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Note that the ATPL250ABN can be supplied either with 100VAC or 230VAC by setting the proper jumpers
(pitch = 5.08mm) in the voltage selector, J2, as depicted in the Figure 7-10. By default, voltage jumper is set
for 230VAC. For more information about power supply, see section 3.5.1.
Note: 1. This maximum input current is measured in the worst case situation, so that, when board is supplied with
a minimum input voltage,100VAC, and the worst consumption conditions. That is when it emits against
very low impedance in higher frequency band and it is supplying an extra board through the DC jack J15.
Table 1-2. Power Supply Requirements.
Parameter
Condition
Min.
Typ.
Max.
Unit
TX Power Consumption
FW: PHY TX Test Console Application
Low Impedance Load (PRIME LISN).
Measured on VDD (16V) DCDC output.
3523(1)
mW
FW: PHY TX Test Console Application
High Impedance Load (CISPR LISN).
Measured on VDD (16V) DCDC output.
2280(1)
mW
RX Power Consumption
Measured on 3.3V LDO output
664(1)
mW
Note: 1. These measurements were taken with a non-optimized FW (the PHY TX Test Console project included in
the kit with a default configuration in TX mode and RX mode) from a power consumption point of view and
they highly depend on the architecture and efficiency of the power supplies. These measurements
correspond to the whole PCBA design and not only to ATPL250A and ATSAME70 devices. All PCB
peripherals are supplied, i.e. ATPLCOUP007 coupling board emitting in CENELEC-A band. Refer to
Atmel ATPL250A and ATSAME70 datasheets for an optimized power consumption measurement result.

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2. Evaluation Kit Overview
ATPL250ABN is the name of the development board included in this PAN Coordinator EK. It implements an
ATPL250A analog front end for PLC, supporting G3-PLC, which has been designed to be controlled by an
external Atmel MCU. In this case, Atmel | Smart SAME70 is the device driving ATPL250A PLC analog front
end.
This document describes how to start working with the Atmel PANCoordinator-EK. A complete description
of PC tools, software examples and hardware are provided in this EK.
2.1 Design support
To make it faster and easier for you to evaluate, prototype, develop and program with Atmelproducts, we
offer a variety of design resources, including development tools, software, boards, kits and documentation.
For any technical support request, please refer to our Design Support webpage:
http://www.atmel.com/design-support/.
There any user can search the Atmel knowledge base to find tips, help topics, and answers to common
questions. In case that the obtained information is not helpful any user can Open a Support Case indicating
a description of the case, product information, etc.
2.2 PANCoordinator-EK contents
PANCoordinator-EK contents –documentation, software and tools- are available online in
https://secure.atmel.com/. To download this information you need a myAtmel account, please access to
www.atmel.com/myAtmel and create your own account After that, please contact with [e-mail],
specifying your myAtmel user name, your company name and email, and request access to the specific
evaluation kit you have acquired. Please do not hesitate to visit our web site to get the last kit updates.
myAtmel EK contents are:
1. A welcome letter, PANCoordinator-EK_WL, introducing the EK and its contents.
2. PANCoordinator-EK Kit User Manual, doc43106.
3. Hardware folder:
a. ATPL250A datasheet, doc43079.
b. Hardware application notes: PLC coupling reference designs, crystal selection guidelines,
layout recommendations, critical design guidelines, etc.
c. EK schemes, PCB layouts, gerbers and BOM files of ATPL250ABN, ATPLCOUP002,
ATPLCOUP006 and ATPLCOUP007 boards.
4. Software folder:
a. G3_va.b.c folder, contains five projects for several IDE tools, IAR, Atmel Studio and Keil
µVision to work in both frequency bands, CENELEC-A, ARIB and FCC bands, see
g3.workspace.same70q21_atpl250abn_v2.zip file:
Apps_Phy_Tester_Tool. This application configures G3-PLC PHY layer and its serial
interface to communicate with Atmel PLC PHY Tester Tool to send and receive PLC
messages from/to the PLC line and check the PLC transmission/reception processes
between ATPL250ABN boards. Atmel PLC PHY Tester tool for PC is available in the
PCTools folder.
Apps_Phy_Tx_Test_Console. This application lets the user to configure a proper set up
to perform both EMC emissions and immunity tests on ATPL250ABN board. These tests
are based on the use of G3 PHY layer with a terminal console firmware that eases the
configuration of several transmission parameters such as modulation, frame data length
and time interval between frames.

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Apps_Phy_Sniffer_Tool. This application configures G3 PHY layer to monitor the PLC
data traffic on ATPL250ABN board and sends via serial communication this traffic to the
ATPL Multiprotocol Sniffer tool. This tool can be downloaded from the PCTools folder.
Every coupling board is intended to be used in their corresponding frequency bands only.
By default, sniffer project is compiled for ATPLCOUP007 board. This means that only G3
CENELEC band-A is supported.
APPS_DLMS_EMU_COORD_APP. The DLMS Emulator application is an example
using the Atmel G3-PLC stack and show how the G3 API should be used. This
application is provided for Coordinator. Application configure the ATPL250ABN board as
G3 Coordinator. A Device node is required, it is configured with DLMS Emulation
capabilities and simulate the data exchange between the G3 Coordinator and the
Device(s). The Device responds dummy DLMS messages after receiving data requests
from the Coordinator.
APPS_ADP_MAC_SERIALIZED_APP. The ADP and MAC serialization is an application
example that bring you access to the ADP, MAC and Bootstrap API through a serial
connection. This application could be useful for users that want to make intensive test for
the stack or want to run the upper layers in other CPU.
b. Common software documentation folder. It contains some user guides as the description of the
Atmel G3 firmware stack, doc43081. Document describes in detail all layers from the Atmel G3
implementation as well as configuration options provided, target platforms, default architecture
and the provided solutions by Atmel.
c. Evaluation License Agreement document.
5. PCTools folder:
a. Atmel PLC PHY Tester, PC tool used to monitor point to point PLC transmissions between
Atmel boards.
b. ATPL Multiprotocol Sniffer, PC tool to monitor data traffic in G3-PLC networks using an Atmel
board as sniffer.
c. SAM-ICE™ Drivers. Users may need to install this driver the first time the SAM-ICE is
connected to the PC.
d. USB Drivers (Silicon USB drivers). Users may need to install these drivers the first time the
ATPL250ABN board is connected to the host PC by means of a serial USB connection.
We recommend installing the evaluation kit contents in the root C:\ to avoid problems
with very long paths.
Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have any issues
concerning the contents of the kit.
The ATPL250ABN board with the ATPLCOUP007 are encapsulated with methacrylate enclosures and
shipped in protective anti-static foam. The two coupling boards, ATPLCOUP002 and ATPLCOUP006, are
shipped in shielded bags.
The boards must not be subject to high electrostatic discharge. We recommend using a
grounding strap or similar ESD protective device when handling the board in hostile ESD
environments. Avoid touching the components pins or any other metallic elements on the
board.

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Figure 2-1. Packed Atmel PANCoordinator-EK.
Figure 2-2. ATPL250ABN PAN Coordinator board and with ATPLCOUP007.
ATPL250ABN board is provided with an example application preprogrammed, the G3-PLC PHY Tester
project for SAM4E70Q21. After installing the Atmel PLC PHY Tester PC Tool in your PC, users can
interface with the device and start exploring its capabilities, for example, checking the point to point PLC
transmissions between the two Atmel boards. Please refer to chapter 7.2 for further information.
Take into account that the PANCoordinator-EK provides one coupling board for CENELEC-A band, Figure
2-3, set over the ATPL250ABN board. In addition to the ATPLCOUP007 board, evaluation kit adds one
coupling boards for FCC bands, Figure 2-4. And another coupling board for ARIB bands, Figure 2-5.
Depending on the coupling board set in ATPL250ABN board and the PHY configuration parameters
selected in the software project you will send and receive PLC messages in the proper PLC band. So that,
with ATPLCOUP007 board only lets you send and receive PLC messages in CENELEC-A band. And with
ATPLCOUP002 and ATPLCOUP006 board in ARIB or FCC bands respectively.

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Figure 2-3. ATPLCOUP007 Coupling board.
Figure 2-4. ATPLCOUP002 Coupling board.
Figure 2-5. ATPLCOUP006 Coupling board.

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3. ATPL250ABN Hardware
3.1 Overview
This section summarizes the Atmel ATPL250ABN board design. It introduces system-level concepts, such
as power supply, MCU, PLC coupling, memories, peripherals and interface board.
ATPL250ABN is a PAN Coordinator development board based on the ATPL250A, G3-PLC transceiver, and
on the SAME70 ARM Cortex M7 microcontroller. ATPL250ABN PAN Coordinator board provides a platform
to develop a complete communications system over G3-PLC technology.
Figure 3-1. ATPL250ABNv2 PAN Coordinator board.
3.2 Features
The ATPL250ABNv2 board includes the following features:
Power supply:
–Non switched ACDC isolated power supply: 100-230VAC, 50-60Hz.
–5 volts rail is accessible by means of a DC Jack connector (J15).
–Selectable 12/16 VDD power supply.
ATPL250A G3-PLC Transceiver:
–Implements G3 CENELEC-A, FCC and ARIB profiles (ITU-T G.9903, June 2014).
–Power Line Carrier modem for 50 and 60 Hz mains.

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–G3-PLC coherent and continuous amplitude tracking in signal reception.
–Automatic Gain Control (AGC).
–Zero cross detection.
–Embedded PLC Analog Front End (AFE), requires only external discrete high efficient Class D
Line Driver for signal injection.
Support to G3-PLC coupling boards ATPLCOUPxxx.
Mains zero-crossing detector circuit.
SAME70Q21 MCU ARM Cortex-M7:
–Core
ARM Cortex-M7 at up to 300 MHz.
16 Kbytes of ICache and 16 Kbytes of DCache with Error Code Correction (ECC).
Memory Protection Unit (MPU) with 16 zones.
Simple- and double-precision HW Floating Point Unit (FPU).
DSP Instructions, Thumb®-2 Instruction Set.
Embedded Trace Module (ETM) with instruction trace stream, including Trace Port
Interface Unit (TPIU).
–Memories
2048 Kbytes Embedded Flash.
384 Kbytes Embedded SRAM.
Tightly Coupled Memory (TCM) interface with four configurations (disabled, 2 x 32
Kbytes, 2 x 64 Kbytes, and 2 x 128 Kbytes).
16 Kbytes ROM with embedded Boot Loader routines (UART0, USB) and IAP routines.
16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, NOR and NAND
Flash.
16-bit SDRAM Controller.
–Cryptography
True Random Number Generator (TRNG).
AES: 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications.
Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and
SHA256.
External Memories:
–4Mx16-bit SDRAM.
–32-Mbit SPI Data Flash.
–TWI EEPROM (do not populate).
–microSD card connector.
Peripherals:
–MCU 24 MHz crystal oscillator.
–MCU 32.768 kHz crystal oscillator.
–VDD and 5V Voltage monitor.
–Reset button.
–User’s LEDs.
–Chip erase.
Interface:
–JTAG debugging port.
–Embedded Trace Module (ETM).

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–High Speed USB 2.0 Device.
–Xplained PRO Master/Slave Interface.
–UARTs over USB and CMOS levels.
–Ethernet 10/100 Mbps.
–Poly-phase Base Node extension header.
–Data Concentrator extension header.
–GPIOs extension header.
Figure 3-2. ATPL250ABNv2 PAN Coordinator board overview.

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3.3 Block diagram
Figure 3-3. ATPL250ABNv2 Block diagram.
3.4 Mechanical and user considerations
This development board is directly powered from mains grid, so hazardous voltage is present on the board.
To avoid user access to dangerous parts, ATPL250ABN must always be used in its enclosure. All required
connectors and configuration jumpers are easily accessible without removing the enclosure cover.
A normal use of the ATPL250ABN does not require removing the enclosure cover. If this
action is necessary, it must be performed by qualified staff being sure that mains
connection has been previously removed.
ATPL250ABN is a CE mark product which passes EN60950-1 safety standard and EN50065-1,
EN50065-2-3, EN50065-7 EMC and FCC (as current carrier system) standards. It also satisfies Pb-Free
and ROHS directive.
ATPL250ABN supply voltage is taken from mains grid (100/230VAC, 50-60Hz), J1 connector.
ATPL250ABN dimensions are 178mm x 124mm x 30mm (LxWxH) and the enclosure dimensions are
191mm x 140mm x 48mm (LxWxH).
The operating temperature range is about -10 to 85ºC.
ATSAME70Q21
115/230 VAC
DC/DC
ATPLCOUPxxx Board
MAINS
PLC
RECTIFIER
Zero Crossing
VDD
3V3
2Kb EEPROM TWI0
SPI + INT ATPL250A
3V3
User LED’s
Timer Counter Input
PP Exp Header
USART1
USB 2.0 Device
UDP
JTAG / TRACE
JTAG & SWD & TRACE
UARTs CMOS
UART0 & UART1
32Mb SPI
DataFlash SPI (USART0)
B Micro USB Port
UART
To
USB
24MHz Crystal
RESET
Slow Clock Crystal
12MHz Crystal
Voltage Monitor
10MHz CLK
GPIOs
4Mx16 bit
SDRAM EBI
AFE
Ethernet
MAC MII
micro SD
Connector HSMCI
DC Exp Header
UART1
GPIOs Exp Header
GPIOs

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3.5 Hardware description
In this section the modules of the ATPL250ABNv2 board are described. Take into account that the board’s
BOM; is not a final design, so they include devices that could be no necessary in the customer designs once
the design has been optimized.
Hardware files are contained in the Hardware folder: “.\Hardware\HW_SCH&PCB\ATPL250ABNv2”.
3.5.1 Power supply
ATPL250ABN board can be powered either with 100VAC or 230VAC by setting the proper jumpers in the
voltage selector (J2, Figure A-2). J1 IEC-320-C8 connector allows cable connection to mains grid. This
design uses an encapsulated transformer (T1, Figure A-2) plus a full bridge rectifier (D1, Figure A-2) to
obtain a DC voltage without increasing noise in PLC frequency bands (42 to 472 kHz), as may occur with
switched ACDC power supplies. F1 and VR1 are used as protective devices in the equipment input and F2
protects the transformer output against over current situations.
By default, the voltage jumpers’ configuration is for 230VAC. See Figure 7-10.
The maximum transformer output power of 14VA is oversized compared to the maximum current
consumption of ATPL250ABN when it is used as a G3-PLC PAN Coordinator. However, this design is
intended to power up other development kits which may have considerable power consumption if they
include components such TFT displays.
The “VDC” voltage rail is used as input power of a high switching frequency buck converter (U11, Figure A-2)
to generate the regulated DC voltage “VDD”, which is used to power the class D amplifier of the PLC coupling
circuit. The output level of the buck converter is selectable between 12V and 16V by means of jumper J16.
Refer to the application note “PLC Coupling Reference Designs” doc43052 to know how the jumper J16
must be configured depending on the PLC coupling board which is being used.
A second buck converter (U12, Figure A-2) also with switching frequency above the highest PLC frequency
band is used to generate a regulated 5V voltage rail. Despite 5V is not used by any device on ATPL250ABN
board, it may be useful to power other Atmel evaluation kits to form more complex PLC reference designs,
such as data concentrators. The DC Jack connector J15 (J15, Figure A-10) can be used to connect other
board to 5V.
Finally on the power supply chain scheme, a low dropout (LDO) regulator (U13, Figure A-2) is used to
generate the 3V3 voltage rail required by ATPL250A and the MCU. The current consumption from 3V3
voltage rail can be measured connecting an ammeter in the placeholder of jumper J17.
Other 1.2V voltage levels are generated by the embedded LDOs on ATPL250A and ATSAME70Q21
respectively. For a more detailed information about these LDOs, refer to ATPL250A and ATSAME70Q21
datasheets.
Figure 3-4. Power supply diagram.
Switching frequencyof DCDC buck converters used in this evaluation kit has been chosen to be higher than
maximum PLC frequency band supported by ATPL250A device.

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We recommend characterizing the potential impact of the selected SMPS for customer
designs on the G3-PLC frequency band transmission.
VDD could be two different voltages, 16 volts or 12 volts, depending on the jumper position. If the jumper is
not placed, the voltage VDD is 16 volts. If the jumper is placed in J16, VDD is 12 volts. By default, the board
has a jumper, so board provides 12 volts. These different voltages are used to supply the PLC coupling
driver board.
Be careful with the VDD voltage selected, because the PLC coupling driver board
ATPLCOUPXXX could be damaged. Please check the features of these boards to select
the operation voltage.
Figure 3-5. VDD selection in ATPL250ABN board.
The following test points and LEDs allow to check that these power supplies are operating properly (see
Figure A-2):
VDD: TP6 and green LED D17.
5V: TP5 and green LED D3.
3V3: TP13 and green LED D13.
GND: TP3 & TP4.
3.5.2 Zero crossing detector
Phase identification is an important feature of devices that are connected to a smart grid network, such as
smart meters. A typical implementation is based on measuring the time difference between a specific PLC
frame reception and the last zero crossing event of the mains single-phase to which the device is
connected.
Figure A-2 shows the zero crossing detection circuit, U10, used in ATPL250ABN board, which allows
discerning between rising and falling edges of the mains voltage. The output signal of the detection circuit
“VNR” is connected to a specific input of the ATPL250A and a synchronization algorithm is applied in order
to obtain an accurate measurement of the time between PLC frame reception and zero crossing events.
The “VNR” signal is also connected to a timer counter input pin of the ATSAME70Q21 in order to have also
information about zero crossing events on the microcontroller side.
It is important to note that in products that do not require galvanic isolation between primary and secondary
circuits and the digital reference ground is connected to either line or neutral, a simple zenner diode with
proper current limiting resistors, which considerablyreduce the BOM cost, can be used instead of the circuit
mounted in ATPL250ABN.
3.5.3 SAME70Q21 Flash microcontroller
3.5.3.1 SAME70Q21 Overview
The Atmel SAME70Q21 Flash microcontroller is based on the high-performance 32-bit ARM Cortex-M7
RISC processor and includes a floating point unit (FPU). It operates at a maximum speed of 300 MHz and
Jumper
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features 2048 Kbytes of Flash and 384 Kbytes of multiport SRAM, which guarantees a minimum access
latency. The on-chip SRAM can be configured as Tightly Coupled Memory (TCM) or system memory.
The SAME70 offers a rich set of advanced connectivity peripherals including a 10/100 Mbps Ethernet MAC
supporting IEEE 1588, 802.1Qbb, 802.3az, 802.1AS and 802.1Qav. With a simple- and double-precision
HW FPU, advanced analog features, as well as a full set of timing and control functions, the SAME70 is the
ideal solution for industrial automation, home and building control, machine-to-machine communications,
automotive aftermarket and energy management applications.
Furthermore, the peripheral set of SAME70 includes a high-speed USB device port with embedded
transceiver, a high-speed MCI for SDIO/SD/MMC, 16-bit SDRAM interface, 16-bit external bus interface
featuring a static memory controller providing connection to SRAM, PSRAM, NOR Flash, LCD Module and
NAND Flash, 12-bit ITU-R BT.601/656 Image Sensor Interface (ISI), hardware acceleration for AES256,
three USARTs, five UARTs, three TWIs, three SPIs, as well as two 4-channel PWM, four three-channel
16-bit Timers with quadrature decoder logic support, one RTC, Analog Front End interfaces (12-bit ADC,
DAC, MUX and PGA), one 12-bit DAC (2-ch) and an analog comparator.
3.5.3.2 SAME70Q21 Clocking
Besides the embedded RC oscillators of ATSAME70Q21, two crystal oscillators are assembled on
ATPL250ABN board to obtain a more precise and stable system clock reference, Y1 of 12 MHz and Y2,
(Figure A-3). Furthermore, a 24MHz clock signal generated by the PLC transceiver ATPL250A is used by
default as clock input by configuring the high frequency oscillator of ATSAME70Q21 in bypass mode. This
configuration allows reducing the overall BOM cost(12MHz crystal oscillator is not required) while keeping a
stable clock input signal.
A slow clock crystal oscillator of 32.768 kHz (Y2, Figure A-3) is used as SAME70 can be used as calendar
and time base counter.
3.5.4 ATPL250A PLC Transceiver
3.5.4.1 ATPL250A Overview
Atmel ATPL250A (U1, Figure A-7) is a power line communications modem, compliant with the PHY layer of
G3-PLC specification. G3-PLC is an open standard technology used for Smart Grid applications like Smart
Metering, Industrial Lighting and Automation, Home Automation, Street Lighting, Solar Energy and PHEV
Charging Stations.
ATPL250A G3-PLC device includes enhanced features such as additional robust modes and frequency
band extension. ATPL250A is able to operate in independently selectable transmission bands up to 472
kHz.
ATPL250A has been conceived to be bundled with an ATMEL MCU running the Physical Layer API and
being controlled by means of a serial synchronous communication interface (SPI).
Please refer to ATPL250A datasheet on the Atmel website or in doc43079 for a detailed description.
3.5.4.2 ATPL250A Clocking
ATPL250A requires a 24MHz crystal oscillator (Y3, Figure A-7). And SAME70Q21 requires a 12 MHz
crystal oscillator (Y1, Figure A-7).
The 24MHz clock signal could be used as internal reference time of the PLC modem, ATPL250A, and also
to generate a 12MHz. So, it could be connected the output clock signal (CLKOUT) of ATPL250A like an
input clock (CLKIN) of SAME70Q21 when ATPL250A is configured in bypass mode. In this way, only one
high frequency crystal oscillator is required. For this option that is mounted by default in the board, R85 is
soldered but R67 and R68 are not populated, and remember that ATPL250A must be configured properly.
Clocking item is widely detailed in the datasheet, doc43079.

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3.5.5 PLC Coupling
Atmel PLC technologyis purelydigital and does not require external DAC/ADC, thus simplifying the external
required circuitry. Generally Atmel PLC coupling reference designs make use of few passive components
plus a Class D amplification stage for transmission.
Figure A-8 and Figure A-9 show external components required by ATPL250A for PLC reception and
transmission respectively.
PLC coupling reference design is composed by the same sub-circuits:
Coupling Stage.
Reception Stage.
Transmission Stage.
Filtering Stage.
Figure 3-6. PLC Coupling example.
3.5.5.1 Coupling stage
The coupling stage blocks the DC component of the line to/from which the signal is injected / received (i.e.:
50/60 Hz of the mains). This is carried out by a high voltage capacitor (C26, Figure A-8). Coupling stage
could also voltage isolate the coupling circuitry from the external world by means of a 1:1 PLC transformer.
Capacitor is laying out in ATPL250ABN. The optional PLC transformer is included in ATPLCOUP007 board
(voltage isolated), see section 4.
Footprint of BNC connector (J11, Figure A-8) is included in the board, but is not mounted by default.
Removing the R12 and R13 and soldering R88 and R89 resistors, the PLC coupling signal can be isolated
from the mains grid and that connector allows performing measurements of transmitted and received PLC
signal without side effects (noise) coming from the grid.
3.5.5.2 Reception stage
The reception stage adapts the received analog signal to be properly captured by the internal reception
chain. Reception circuit is independent of the PLC frequency band which is being used. It basically consists
on:
Single-pole low pass filter (RC Filter), R49 & C43, Figure A-9.