Caen N6724 User manual

User Manual UM3247
N6724
2/4 Channel 14bit 100 MS/s Waveform Digitizer
Rev. 10 - January 27th, 2017

Purpose of this Manual
This document contains the full hardware descripon of the N6724 CAEN digizer and their principle of operang as
Waveform Recording Digizer (basing on the hereaer called ”waveform recording firmware”).
The reference firmware revision is: 4.12_0.14.
For any reference to registers in this user manual, please refer to document [RD1] on the digizer web page.
For any reference to DPP firmware in this user manual, please refer to documents [RD2] and [RD3] present on the
firmware web page.
Change Document Record
Date Revision Changes
- 00-09 Old manuals are available on request (see
Chap. Technical Support).
April 18th, 2017 10 Revised layout and improved text. Added new Sec.
Decimaon and Sec. TRG-IN as Gate.
Symbols, Abbreviated Terms and Notation
ADC Analog-to-Digital Converter
AMC ADC & Memory Controller
DAQ Data Acquision
DAC Digital-to-Analog Converter
DC Direct Current
LVDS Low-Voltage Differenal Signal
PLL Phase-Locked Loop
ROC ReadOut Controller
TTT Trigger Time Tag
USB Universal Serial Bus
Reference Documents
[RD1] UM5918 – 724 Registers Descripon.
[RD2] UM5954 – DPP-DAW User Manual.
[RD3] UM3182 – DPP-PHA and MC2Analyzer User Manual.
[RD4] GD2512 – CAENUpgrader QuickStart Guide.
[RD5] GD2817 – How to make coincidences with CAEN digizers.
[RD6] UM1935 – CAENDigizer User & Reference Manual.
[RD7] AN2472 – CONET1 to CONET2 migraon.
[RD8] GD2783 – First Installaon Guide to Desktop Digizers & MCA.
[RD9] UM2091 – CAEN WaveDump User Manual.
[RD10] GD2484 – CAENScope Quick Start Guide.
[RD11] UM5960 – CoMPASS User Manual.
All CAEN documents can be downloaded at: hp://www.caen.it/csite/LibrarySearch.jsp

CAEN S.pA.
Via Vetraia, 11 55049 Viareggio (LU) - ITALY
Tel. [phone] Fax [phone]
[e-mail]
www.caen.it
©CAEN SpA – 2017
Disclaimer
No part of this manual may be reproduced in any form or by any means, electronic, mechanical, recording, or
otherwise, without the prior wrien permission of CAEN SpA.
The informaon contained herein has been carefully checked and is believed to be accurate; however, no responsi-
bility is assumed for inaccuracies. CAEN SpA reserves the right to modify its products specificaons without giving
any noce; for up to date informaon please visit www.caen.it.
MADE IN ITALY: We stress the fact that all the boards are made in Italy because in this globalized world, where geng
the lowest possible price for products somemes translates into poor pay and working condions for the people who
make them, at least you know that who made your board was reasonably paid and worked in a safe environment.
(this obviously applies only to the boards marked ”MADE IN ITALY”, we cannot aest to the manufacturing process
of ”third party” boards).
UM3247 - N6724 User Manual rev. 10 3

Index
Purpose of this Manual ............................................... 2
Change document record .............................................. 2
Symbols, abbreviated terms and notaon ..................................... 2
Reference Documents ............................................... 2
Safety Noces .................................................... 7
1 Introducon ................................................... 8
2 Block Diagram .................................................. 10
3 Technical Specificaons ............................................. 11
4 Packaging and Compliancy ........................................... 13
5 Power Requirements .............................................. 15
6 Panels Descripon ............................................... 16
FrontPanel................................................. 17
7 Funconal Descripon ............................................. 20
AnalogInputStage............................................. 20
DCOffsetIndividualSeng ..................................... 20
ClockDistribuon ............................................. 21
PLLMode ................................................. 22
ReducingtheSamplingFrequency .................................... 22
Decimaon................................................. 23
TriggerClock................................................ 23
AcquisionModes............................................. 24
AcquisionRun/Stop......................................... 24
Acquision Triggering: Samples and Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mul-EventMemoryOrganizaon.................................. 26
Customsizeevents ....................................... 26
Eventstructure............................................ 27
Header.............................................. 27
Data ............................................... 28
EventFormatExamples ..................................... 28
AcquisionSynchronizaon ..................................... 30
ZeroSuppression ............................................. 31
Full Suppression based on the Integral of the Signal . . . . . . . . . . . . . . . . . . . . . . . . . 32
Full Suppression based on the Amplitude of the Signal . . . . . . . . . . . . . . . . . . . . . . . 33
ZeroLengthEncodingZLE ...................................... 34
ZLEExamples .......................................... 36
TriggerManagement ........................................... 38
SowareTrigger ........................................... 38
ExternalTrigger............................................ 38
Self-Trigger .............................................. 39
Triggercoincidencelevel....................................... 40
TRG-INasGate............................................ 43
Triggerdistribuon.......................................... 43
Example ............................................. 44
4 UM3247 - N6724 User Manual rev. 10

TestPaernGenerator........................................... 45
Reset, Clear and Default Configuraon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
GlobalReset ............................................. 45
MemoryReset ............................................ 45
TimerReset.............................................. 45
Data Transfer Capabilies and Events Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
BlockTransfer............................................. 46
SingleDataTransfer ......................................... 46
OpcalLinkandUSBAccess........................................ 47
8 Drivers &Libraries ............................................... 48
Drivers................................................... 48
Libraries .................................................. 48
9 Soware Tools ................................................. 50
CAENUpgrader............................................... 50
CAENCommDemo............................................. 51
CAENWaveDump ............................................. 52
CAENScope ................................................ 53
CAEN MC2Analyzer ............................................ 54
CoMPASS.................................................. 55
10 HW Installaon ................................................. 56
Power-onSequence ............................................ 57
Power-onStatus.............................................. 57
11 Firmware and Upgrades ............................................ 58
FirmwareUpgrade............................................. 58
FirmwareFileDescripon ...................................... 59
Troubleshoong .............................................. 59
12 Technical Support ................................................ 60
ReturnsandRepairs............................................ 60
TechnicalSupportService ......................................... 60
List of Figures
Fig. 2.1 BlockDiagram............................................. 10
Fig. 4.1 Frontview............................................... 13
Fig. 4.2 Sideview................................................ 13
Fig. 6.1 Frontpanelview............................................ 16
Fig. 7.1 Analoginputdiagram ......................................... 20
Fig. 7.2 Clockdistribuondiagram ...................................... 21
Fig. 7.3 TriggerOverlap ............................................ 25
Fig. 7.4 EventFormat ............................................. 29
Fig. 7.5 Zero Suppression based on the integral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Fig. 7.6 Zero Suppression based on the amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Fig. 7.7 ControlWordformat. ......................................... 34
Fig. 7.8 Zero Suppression based on the Zero Length Encoding. . . . . . . . . . . . . . . . . . . . . . . . . 35
UM3247 - N6724 User Manual rev. 10 5

Fig. 7.9 Example of non-overlapping NLBK and NLFWD in case of posive logic (le) and negave logic (right). 36
Fig. 7.10 Event format for non-overlapping NLBK and NLFWD.in case of posive logic (le) and negave logic
(right). ................................................. 36
Fig. 7.11 Example with posive logic, NLBK overlapping with N1, and NLFWD =0................ 36
Fig. 7.12 Example with posive logic and NLBK overlapping with N3. ..................... 37
Fig. 7.13 Block diagram of Trigger management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Fig. 7.14 Self-triggergeneraon. ........................................ 39
Fig. 7.15 Self-trigger relaonship with Majority level = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Fig. 7.16 Self-trigger relaonship with Majority level = 1 and TTVAW =0. ................... 41
Fig. 7.17 Self-trigger relaonship with Majority level = 1 and TTVAW =0. ................... 42
Fig. 7.18 Trigger configuraon of TRG-OUT front panel connector. . . . . . . . . . . . . . . . . . . . . . . . 43
Fig. 8.1 Driversandsowarelayers....................................... 49
Fig. 9.1 CAENUpgrader Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Fig. 9.2 CAENComm Demo Java and LabVIEW graphical interface . . . . . . . . . . . . . . . . . . . . . . 51
Fig. 9.3 CAENWaveDump ........................................... 52
Fig. 9.4 CAENScopemainframe......................................... 53
Fig. 9.5 CAEN MC2Analyzer (MC2A)sowaretool. .............................. 54
Fig. 9.6 CoMPASSsowaretool......................................... 55
Fig. 10.1 Front panel LEDs status at power-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
List of Tables
Tab. 1.1 Tableofmodelsandrelateditems .................................. 9
Tab. 3.1 Specificaontable........................................... 12
Tab. 5.1 Powerrequirementstable....................................... 15
Tab. 7.1 Buffer organizaon of 724 family series. For each value of buffer size it is reported the memory
size and the number of samples of one buffer, where k = 1024 and M = 1024 ·1024. . . . . . . . . 26
Tab. 7.2 Reserved/Trg Opons configuraon table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 UM3247 - N6724 User Manual rev. 10

Safety Noces
CAUTION: this product needs proper cooling.
USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE
OVERHEATING THE BOARD MAY DEGRADE ITS PERFORMANCES!
CAUTION: this product needs proper handling.
N6724 DOES NOT SUPPORT LIVE INSERTION (HOT SWAP)!
REMOVE OR INSERT THE BOARD WHEN THE NIM CRATE IS POWERED
OFF!
ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE
EXTRACTING THE BOARD FROM THE CRATE!
UM3247 - N6724 User Manual rev. 10 7

1 Introducon
The Mod. N6724 is a 1-unit wide NIM module housing a 2/4 Channel 14 bit 100 MS/s Desktop Waveform
Digizer with 2.25 Vpp input dynamic range on single ended MCX coaxial connectors. Customized versions
of 10 Vpp and 500 mVpp input range are available (see Tab. 1.1). The DC offset is adjustable via a 16-bit DAC
on each channel in the ±1.125 V (@2.25 Vpp), ±5 V (@10 Vpp), or ±250 mV (@500 mVpp).
Considering the sampling frequency and bit number, these digizers are well suited for high resoluon
detectors as Silicon, HPGe coupled to Charger Sensive Preamplifiers or inorganic scinllators like Nal or
Csl.
Each channel has a SRAM digital memory (see Tab. 1.1 for the available memory size opons) divided into
buffers of programmable size (1 ÷1024). The readout (from USB or Opcal link) of a frozen buffer is
independent from the write operaons in the acve circular buffer (ADC data storage).
A common acquision trigger signal (common to all the channels) can be fed externally via the front panel
TRG-IN input connector or via soware. Alternavely, each channel is able to generate a self-trigger when
the input signal goes under/over a programmable threshold. The trigger from one board can be propagated
out of the board through the front panel GPO .
During the acquision, data stream is connuously wrien in a circular memory buffer. When the trigger
occurs, the digizer writes further samples for the post trigger and freezes the buffer that can be read by
one of the provided readout links.
N6724 features front panel CLK-IN connector as well as an internal PLL for clock synthesis (50 MHz oscillator)
from internal/external references.
The board houses USB 2.0 and opcal link interfaces. USB 2.0 allows data transfers up to 30 MB/s. The
Opcal Link interface (CAEN proprietary CONET protocol) is capable of transfer rate up to 80 MB/s and
offers daisy chain capability. Therefore, it is possible to connect up to 8 ADC modules to a single A2818
Opcal Link Controller, or up to 32 using a 4-link A3818 version (Mod. A2818/A3818, see Tab. 1.1).
In addion to the waveform recording firmware, CAEN provides for this digizer the Digital Pulse Processing
firmware (DPP) for the Pulse Hight Analysis (DPP-PHA) [RD3] and the Dynamic Acquision Windows (DPP-
DAW) [RD2]. These special firmware make the digizer an enhanced system for Physics Applicaons.
8 UM3247 - N6724 User Manual rev. 10

Board Model Descripon
N6724B 4 Ch. 14 bit 100 MS/s Waveform Digizer: 512 kS/ch, C20, SE
N6724C 2 Ch. 14 bit 100 MS/s Waveform Digizer: 512 kS/ch, C20, SE
N6724F 4 Ch. 14 bit 100 MS/s Waveform Digizer: 4 MS/ch, C20, SE
N6724G 2 Ch. 14 bit 100 MS/s Waveform Digizer: 4 MS/ch, C20, SE
PERS0172401 724 Customizaon - 10 Vpp Input Range, SE
PERS0172402 724 Customizaon - 500 mVpp Input Range, SE
DPP Firmware Descripon
DDP-PHA 2/4ch DDP-PHA Digital Pulse Processing for Pulse Height Analysis (2/4ch x724)
DDP-DAW 2/4ch DDP-DAW Digital Pulse Processing with Dynamic Acquision Window (2/4ch x724)
Related Products Descripon
A2818 A2818 – PCI Opcal Link (Rhos compliant)
A3818A A3818A – PCIe 1 Opcal Link
A3818B A3818B – PCIe 2 Opcal Link
A3818C A3818C – PCIe 4 Opcal Link
Accessories Descripon
A318 SE to Differenal Clock Adapter
A654 Single Channel MCX to LEMO Cable Adapter
A654 KIT4 4 MCX TO LEMO Cable Adapter
A654 KIT8 8 MCX TO LEMO Cable Adapter
A659 Single Channel MCX to BNC Cable Adapter
A659 KIT4 4 MCX TO BNC Cable Adapter
A659 KIT8 8 MCX TO BNC Cable Adapter
AI2730 Opcal Fibre 30 m simplex
AI2720 Opcal Fibre 20 m simplex
AI2705 Opcal Fibre 5 m simplex
AI2703 Opcal Fibre 30 cm simplex
AY2730 Opcal Fibre 30 m duplex
AY2720 Opcal Fibre 20 m duplex
AY2705 Opcal Fibre 5 m duplex
Tab. 1.1: Table of models and related items
UM3247 - N6724 User Manual rev. 10 9

2 Block Diagram
DAC
AMC [FPGA]
ADC &
MEMORY
CONTROLLER
ADC
BUFFERS
x4 (4 channels)
ROC [FPGA]
- Readout control
- Optical link control
- USB interface
control
- Trigger control
- External interface
control
MUX
OSC
CLOCK
MANAGER
(AD9520)
LOCAL BUS
CLK IN
TRG IN
GPI
USB
INPUTS
FRONT PANEL
GPO
OPTICAL LINK
Fig. 2.1: Block Diagram
10 UM3247 - N6724 User Manual rev. 10