Caen V1724 Series Technical document

Technical
Information
Manual
MOD. V1724
6 November 2007
Revision n. 7
8 CHANNEL 14 BIT
100 MS/S DIGITIZER
MANUAL REV.7
NPO:
00103/05:V1724x.MUTx/07

CAEN will repair or replace any product within the guarantee period if the Guarantor declares
that the product is defective due to workmanship or materials and has not been caused by
mishandling, negligence on behalf of the User, accident or any abnormal conditions or
operations.
CAEN declines all responsibility for damages or
injuries caused by an improper use of the Modules due
to negligence on behalf of the User. It is strongly
recommended to read thoroughly the CAEN User's
Manual before any kind of operation.
CAEN reserves the right to change partially or entirely the contents of this Manual at any time
and without giving any notice.
Disposal of the Product
The product must never be dumped in the Municipal Waste. Please check your local
regulations for disposal of electronics products.

Document type: Title: Revision date: Revision:
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TABLE OF CONTENTS
1. GENERAL DESCRIPTION.........................................................................................................................8
1.1. OVERVIEW ...............................................................................................................................................8
1.2. BLOCK DIAGRAM.....................................................................................................................................9
2. TECHNICAL SPECIFICATIONS............................................................................................................10
2.1. PACKAGING............................................................................................................................................10
2.2. POWER REQUIREMENTS ..........................................................................................................................10
2.3. FRONT PANEL.........................................................................................................................................11
2.4. EXTERNAL CONNECTORS........................................................................................................................12
2.4.1. ANALOG INPUT connectors.........................................................................................................12
2.4.2. CONTROL connectors...................................................................................................................12
2.4.3. ADC REFERENCE CLOCK connectors .......................................................................................12
2.4.4. Digital I/O connectors...................................................................................................................13
2.4.5. Optical LINK connector ................................................................................................................13
2.5. OTHER FRONT PANEL COMPONENTS .......................................................................................................13
2.5.1. Displays.........................................................................................................................................13
2.6. INTERNAL COMPONENTS ........................................................................................................................13
2.7. TECHNICAL SPECIFICATIONS TABLE .......................................................................................................15
3. FUNCTIONAL DESCRIPTION................................................................................................................16
3.1. ANALOG INPUT.......................................................................................................................................16
3.1.1. Single ended input .........................................................................................................................16
3.1.2. Differential input...........................................................................................................................16
3.2. CLOCK DISTRIBUTION............................................................................................................................17
3.2.1. Direct Drive Mode.........................................................................................................................17
3.2.2. PLL Mode......................................................................................................................................18
3.2.3. Trigger Clock.................................................................................................................................18
3.2.4. Output Clock..................................................................................................................................18
3.2.5. AD9510 programming...................................................................................................................18
3.2.6. PLL programming.........................................................................................................................19
3.2.7. Direct Drive programming............................................................................................................19
3.2.8. Configuration file ..........................................................................................................................19
3.2.9. Multiboard synchronisation...........................................................................................................20
3.2.10. Internal clock.................................................................................................................................20
3.2.11. External clock and multiboard synchronisation............................................................................20
3.3. ACQUISITION MODES .............................................................................................................................20
3.3.1. Acquisition run/stop.......................................................................................................................20
3.3.2. Gate and Sample mode acquisition ...............................................................................................21
3.3.2.1. Gate mode .................................................................................................................................................21
3.3.3. Sample mode..................................................................................................................................22
3.3.4. Acquisition Triggering: Samples and Events.................................................................................22
3.3.4.1. Custom size events....................................................................................................................................23
3.3.5. Event structure...............................................................................................................................24
3.3.6. Memory FULL management..........................................................................................................25

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3.4. ZERO SUPPRESSION ................................................................................................................................25
3.4.1. Zero Suppression Algorithm..........................................................................................................25
3.4.1.1. Full Suppression based on the integral of the signal..................................................................................25
3.4.1.2. Full Suppression based on the amplitude of the signal..............................................................................25
3.4.1.3. Zero Length Encoding ZLE.......................................................................................................................25
3.5. TRIGGER MANAGEMENT.........................................................................................................................30
3.5.1. External trigger .............................................................................................................................30
3.5.2. Software trigger.............................................................................................................................30
3.5.3. Local channel auto-trigger............................................................................................................31
3.5.4. Trigger distribution .......................................................................................................................31
3.6. FRONT PANEL I/OS.................................................................................................................................31
3.7. ANALOG MONITOR.................................................................................................................................32
3.7.1. Trigger Majority Mode (Monitor Mode = 0).................................................................................32
3.7.2. Test Mode (Monitor Mode = 1).....................................................................................................33
3.7.3. Analog Monitor/Inspection Mode (Monitor Mode = 2) ................................................................33
3.7.3.1. Procedure to enable “Analog Monitor” mode ...........................................................................................34
3.7.3.2. Applications examples ..............................................................................................................................34
3.7.4. Buffer Occupancy Mode (Monitor Mode = 3)...............................................................................35
3.7.5. Voltage Level Mode (Monitor Mode = 4)......................................................................................35
3.8. TEST PATTERN GENERATOR....................................................................................................................36
3.9. RESET,CLEAR AND DEFAULT CONFIGURATION.....................................................................................36
3.9.1. Global Reset ..................................................................................................................................36
3.9.2. Memory Reset................................................................................................................................36
3.9.3. Timer Reset....................................................................................................................................36
3.10. VMEBUS INTERFACE .........................................................................................................................36
3.10.1. Addressing capabilities..................................................................................................................36
3.10.1.1. Base address..........................................................................................................................................36
3.10.1.2. CR/CSR address ...................................................................................................................................37
3.10.1.3. Address relocation ................................................................................................................................37
3.11. DATA TRANSFER CAPABILITIES ..........................................................................................................38
3.12. EVENTS READOUT ..............................................................................................................................38
3.12.1. Sequential readout.........................................................................................................................38
3.12.1.1. SINGLE D32 ........................................................................................................................................38
3.12.1.2. BLOCK TRANSFER D32/D64, 2eVME .............................................................................................38
3.12.1.3. CHAINED BLOCK TRANSFER D32/D64.........................................................................................39
3.12.2. Random readout (to be implemented)............................................................................................39
3.12.3. Event Polling.................................................................................................................................40
3.13. OPTICAL LINK ....................................................................................................................................40
3.13.1. CAENVME_Init.............................................................................................................................41
3.13.2. CAENVME_End ............................................................................................................................41
3.13.3. CAENVME_ReadCycle .................................................................................................................42
3.13.4. CAENVME_WriteCycle.................................................................................................................42
3.13.5. CAENVME_MultiRead..................................................................................................................42
3.13.6. CAENVME_MultiWrite .................................................................................................................43
3.13.7. CAENVME_BLTReadCycle...........................................................................................................43

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3.13.8. CAENVME_FIFOBLTReadCycle..................................................................................................44
3.13.9. CAENVME_MBLTReadCycle .......................................................................................................44
3.13.10. CAENVME_FIFOMBLTReadCycle ..........................................................................................44
3.13.11. CAENVME_IRQCheck..............................................................................................................45
3.13.12. CAENVME_IRQEnable.............................................................................................................45
3.13.13. CAENVME_IRQDisable............................................................................................................45
3.13.14. CAENVME_IRQWait.................................................................................................................46
4. VME INTERFACE.....................................................................................................................................47
4.1. REGISTERS ADDRESS MAP ......................................................................................................................47
4.2. CONFIGURATION ROM (0XF000-0XF084; R).........................................................................................48
4.3. CHANNEL N ZS_THRES (0X1N24; R/W)................................................................................................49
4.4. CHANNEL N ZS_NSAMP (0X1N28; R/W)...............................................................................................50
4.5. CHANNEL N THRESHOLD (0X1N80; R/W)................................................................................................50
4.6. CHANNEL N OVER/UNDER THRESHOLD (0X1N84; R/W) .........................................................................50
4.7. CHANNEL N STATUS (0X1N88; R)...........................................................................................................50
4.8. CHANNEL N AMC FPGA FIRMWARE (0X1N8C; R) ................................................................................50
4.9. CHANNEL N BUFFER OCCUPANCY (0X1N94; R)......................................................................................51
4.10. CHANNEL N DAC REGISTER (0X1N98; R/W) ......................................................................................51
4.11. CHANNEL N ADC CONFIGURATION (0X1N9C; R/W)...........................................................................51
4.12. CHANNEL CONFIGURATION (0X8000; R/W)........................................................................................51
4.13. CHANNEL CONFIGURATION BIT SET (0X8004; W)..............................................................................52
4.14. CHANNEL CONFIGURATION BIT CLEAR (0X8008; W).........................................................................52
4.15. BUFFER ORGANIZATION (0X800C; R/W) ............................................................................................52
4.16. BUFFER FREE (0X8010; R/W)..............................................................................................................52
4.17. CUSTOM SIZE (0X8020; R/W) .............................................................................................................52
4.18. ACQUISITION CONTROL (0X8100; R/W)..............................................................................................53
4.19. ACQUISITION STATUS (0X8104; R).....................................................................................................53
4.20. SOFTWARE TRIGGER (0X8108; W)......................................................................................................54
4.21. TRIGGER SOURCE ENABLE MASK (0X810C; R/W)..............................................................................54
4.22. FRONT PANEL TRIGGER OUT ENABLE MASK (0X8110; R/W) .............................................................54
4.23. POST TRIGGER SETTING (0X8114; R/W) .............................................................................................55
4.24. FRONT PANEL I/O DATA (0X8118; R/W).............................................................................................55
4.25. FRONT PANEL I/O CONTROL (0X811C; R/W)......................................................................................55
4.26. CHANNEL ENABLE MASK (0X8120; R/W)...........................................................................................56
4.27. ROC FPGA FIRMWARE REVISION (0X8124; R)..................................................................................56
4.28. DOWNSAMPLE FACTOR (0X8128; R/W) ..............................................................................................56
4.29. EVENT STORED (0X812C; R)..............................................................................................................56
4.30. SET MONITOR DAC (0X8138; R/W)....................................................................................................57

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4.31. BOARD INFO (0X8140; R)...................................................................................................................57
4.32. MONITOR MODE (0X8144; R/W).........................................................................................................57
4.33. EVENT SIZE (0X814C; R)....................................................................................................................57
4.34. ANALOG MONITOR (0X8150; R/W).....................................................................................................57
4.35. VME CONTROL (0XEF00; R/W) .........................................................................................................58
4.36. VME STATUS (0XEF04; R).................................................................................................................58
4.37. BOARD ID (0XEF08; R/W)..................................................................................................................58
4.38. MCST BASE ADDRESS AND CONTROL (0XEF0C; R/W)......................................................................58
4.39. RELOCATION ADDRESS (0XEF10; R/W)..............................................................................................59
4.40. INTERRUPT STATUS ID (0XEF14; R/W)...............................................................................................59
4.41. INTERRUPT EVENT NUMBER (0XEF18; R/W)......................................................................................59
4.42. BLT EVENT NUMBER (0XEF1C; R/W)................................................................................................59
4.43. SCRATCH (0XEF20; R/W) ...................................................................................................................59
4.44. SOFTWARE RESET (0XEF24; W).........................................................................................................59
4.45. SOFTWARE CLEAR (0XEF28; W) ........................................................................................................59
4.46. FLASH ENABLE (0XEF2C; R/W)..........................................................................................................59
4.47. FLASH DATA (0XEF30; R/W)..............................................................................................................60
5. INSTALLATION ........................................................................................................................................61
5.1. POWER ON SEQUENCE ...........................................................................................................................61
5.2. POWER ON STATUS................................................................................................................................61
5.3. FIRMWARE UPGRADE..............................................................................................................................61
5.3.1. V1724 Upgrade files description...................................................................................................62
LIST OF FIGURES
FIG.1.1: MOD.V1724 BLOCK DIAGRAM .................................................................................................................9
FIG.2.1: MOD.V1724 FRONT PANEL......................................................................................................................11
FIG.2.2: AMP CLK IN/OUT CONNECTOR ............................................................................................................12
FIG.2.3: ROTARY AND DIP SWITCHES LOCATION....................................................................................................14
FIG.3.1: SINGLE ENDED INPUT DIAGRAM ...............................................................................................................16
FIG.3.2: DIFFERENTIAL INPUT DIAGRAM ...............................................................................................................16
FIG.3.3: CLOCK DISTRIBUTION DIAGRAM ..............................................................................................................17
FIG.3.4: CAENPLLCONFIG MAIN MENU ..............................................................................................................19
FIG.3.5: DATA STORAGE IN GATE MODE ...............................................................................................................21
FIG.3.6: DATA STORAGE IN SAMPLE MODE...........................................................................................................22
FIG.3.7: TRIGGER OVERLAP ..................................................................................................................................23
FIG.3.8: ZERO SUPPRESSION EXAMPLE..................................................................................................................26

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FIG.3.9: EXAMPLE WITH POSITIVE LOGIC AND NON-OVERLAPPING NLBK /NLFWD ..................................................27
FIG.3.10: EXAMPLE WITH NEGATIVE LOGIC AND NON-OVERLAPPING NLBK /NLFWD ..............................................27
FIG.3.11: EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING NLBK..............................................................28
FIG.3.12: EXAMPLE WITH POSITIVE LOGIC AND OVERLAPPING NLBK .....................................................................29
FIG.3.13: BLOCK DIAGRAM OF TRIGGER MANAGEMENT........................................................................................30
FIG.3.14: LOCAL TRIGGER GENERATION................................................................................................................31
FIG.3.15: MAJORITY LOGIC (2 CHANNELS OVER THRESHOLD;BIT[6] OF CH.CONFIG.REGISTER =0) ....................33
FIG.3.16: INSPECTION MODE DIAGRAM.................................................................................................................33
FIG.3.17: EXAMPLE OF MAGNIFY PARAMETER USE ON SINGLE CHANNEL..............................................................34
FIG.3.18: EXAMPLE OF MAGNIFY AND OFFSET PARAMETERS USE ON SINGLE CHANNEL .......................................35
FIG.3.19: A24 ADDRESSING...................................................................................................................................37
FIG.3.20: A32 ADDRESSING...................................................................................................................................37
FIG.3.21: CR/CSR ADDRESSING............................................................................................................................37
FIG.3.22: SOFTWARE RELOCATION OF BASE ADDRESS...........................................................................................37
FIG.3.23: EXAMPLE OF BLT READOUT..................................................................................................................39
FIG.3.24: EXAMPLE OF RANDOM READOUT ...........................................................................................................40
FIG.3.25: OPTICAL LINK DAISY CHAIN ..................................................................................................................41
LIST OF TABLES
TABLE 1.1: MOD.V1724 VERSIONS .........................................................................................................................8
TABLE 2.1: MODEL V1724 POWER REQUIREMENTS................................................................................................10
TABLE 2.2 :FRONT PANEL LEDS...........................................................................................................................13
TABLE 2.3 :MOD.V1724 TECHNICAL SPECIFICATIONS ..........................................................................................15
TABLE 3.1: BUFFER ORGANIZATION ......................................................................................................................22
TABLE 3.2 :EVENT ORGANIZATION .......................................................................................................................24
TABLE 3.3 :FRONT PANEL I/OS DEFAULT SETTING ................................................................................................32
TABLE 4.1: ADDRESS MAP FOR THE MODEL V1724...............................................................................................47
TABLE 4.2: ROM ADDRESS MAP FOR THE MODEL V1724.....................................................................................49
TABLE 4.3: OUTPUT BUFFER MEMORY BLOCK DIVISION........................................................................................52

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1.General description
1.1. Overview
The Mod. V1724 is a 1-unit wide VME 6U module housing a 8 Channel 14 bit 100 MS/s
Flash ADC Waveform Digitizer with threshold Auto-Trigger capabilities.
The board is available with different input range, memory and connector configuration, as
summarised by the following table:
Table 1.1: Mod. V1724 versions
Model Input type SRAM Memory Optical link AMC FPGA(*) Form factor
V1724LC Single ended 512 Ksamples / ch No EP1C4 6U-VME64
V1724 Single ended 512 Ksamples / ch Yes EP1C4 6U-VME64
V1724B Single ended 4 Msamples / ch Yes EP1C4 6U-VME64
V1724C Differential 512 Ksamples / ch Yes EP1C4 6U-VME64
V1724D Differential 4 Msamples / ch Yes EP1C4 6U-VME64
V1724E Single ended 4 Msamples / ch Yes EP1C20 6U-VME64
V1724F Differential 4 Msamples / ch Yes EP1C20 6U-VME64
VX1724 Single ended 512 Ksamples / ch Yes EP1C4 6U-VME64X
VX1724B Single ended 4 Msamples / ch Yes EP1C4 6U-VME64X
VX1724C Differential 512 Ksamples / ch Yes EP1C4 6U-VME64X
VX1724D Differential 4 Msamples / ch Yes EP1C4 6U-VME64X
VX1724E Single ended 4 Msamples / ch Yes EP1C20 6U-VME64X
VX1724F Differential 4 Msamples / ch Yes EP1C20 6U-VME64X
(*) AMC: ADC e Memory controller FPGA. Models available: ALTERA Cyclone EP1C4 (4000 Logic elements)
or ALTERA Cyclone EP1C20 (20000 Logic elements).
Single ended input versions, optionally, are available with 10 Vpp dynamic range (default
range: 2.25 Vpp).
The DC offset of the signal can be adjusted channel per channel by means of a
programmable 16bit DAC.
The board features a front panel clock/reference In/Out and a PLL for clock synthesis
from internal/external references. This allows multi board phase synchronisations to an
external clock source or to a V1724 clock master board.
The data stream is continuously written in a circular memory buffer; when the trigger
occurs the FPGA writes further N samples for the post trigger and freezes the buffer that
then can be read either via VME or via Optical Link; the acquisition can continue without
dead-time in a new buffer. Each channel has a SRAM memory, divided in buffers of
programmable size.
The trigger signal can be provided via the front panel input as well as via the VMEbus,
but it can also be generated internally, as soon as a programmable voltage threshold is
reached. The individual Auto-Trigger of one channel can be propagated to the other
channels and onto the front panel Trigger Output.
The VME interface is VME64X compliant and the data readout can be performed in

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Single Data Transfer (D32), 32/64 bit Block Transfer (BLT/MBLT), 2eVME, 2eSST and
32/64 bit Chained Block Transfer (CBLT).
The board houses a daisy chainable Optical Link able to transfer data at 80 MB/s, thus it
is possible to connect up to eight V1724 (64 ADC channels) to a single Optical Link
Controller (Mod. A2818, see Accessories/Controller).
The V1724 can be controlled and readout through the Optical Link in parallel to the VME
interface.
The Mod. V1724LC is also available, a simplified version of the Mod. V1724, without
Optical Link and Analog Monitor features.
1.2. Block Diagram
DAC
AMC [FPGA]
ADC &
MEMORY
CONTROLLER
ADC
BUFFERS
x8 channels
ROC [FPGA]
- Readout control
- VME interface control
- Optical link control
- Trigger control
- External interface control
VME
MUX
OSC
CLOCK
MANAGER
(AD9510)
VCXO
TRIGGERS & SYNC
LOCAL BUS
CLK IN
CLK OUT
TRG IN
TRG OUT
S IN
DIGITAL I/Os
MON DAC
OPTICAL LINK
INPUTS
FRONT PANEL
1GHz
Fig. 1.1: Mod. V1724 Block Diagram
The function of each block will be explained in detail in the subsequent sections.

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2.Technical specifications
2.1. Packaging
The module is housed in a 6U-high, 1U-wide VME unit. The board hosts the VME P1,
and P2 connectors and fits into both VME/VME64 standard and V430 backplanes.
VX1724 versions require VME64X compliant crates.
2.2. Power requirements
The power requirements of the module are as follows:
Table 2.1: Model V1724 power requirements
+5 V 4.50 A
+12 V 0.2 A
-12 V 0.2 A