Caen DT5740 Technical document

Technical
Information
Manual
MOD. DT5740
04 May 2016
Revision n. 12
32 CHANNEL 12 BIT
65 MS/S DIGITIZER
MANUAL REV.12
NPO:
00100/09:5740x.MUTx/12

CAEN S.p.A.
Via Vetraia, 11 55049 Viareggio (LU) - ITALY
Tel. [phone] Fax [phone]
[email protected]
www.caen.it
© CAEN SpA –2016
Disclaimer
No part of this manual may be reproduced in any form or by any means, electronic, mechanical, recording, or
otherwise, without the prior written permission of CAEN SpA.
The information contained herein has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. CAEN SpA reserves the right to modify its products specifications without
giving any notice; for up to date information please visit www.caen.it.
MADE IN ITALY: We stress the fact that all the boards are made in Italy because in this globalized world, where
getting the lowest possible price for products sometimes translates into poor pay and working conditions for the
people who make them, at least you know that who made your board was reasonably paid and worked in a safe
environment. (this obviously applies only to the boards marked "MADE IN ITALY", we cannot attest to the
manufacturing process of "third party" boards).

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User's Manual (MUT)
Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer
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TABLE OF CONTENTS
1INTRODUCTION........................................................................................................................................6
1.1 OVERVIEW ..................................................................................................................................................6
1.2 BLOCK DIAGRAM..........................................................................................................................................8
2TECHNICAL SPECIFICATIONS..................................................................................................................... 9
2.1 PACKAGING AND COMPLIANCY........................................................................................................................9
2.2 POWER REQUIREMENTS.................................................................................................................................9
2.3 COOLING MANAGEMENT .............................................................................................................................10
2.4 FRONT AND BACK PANEL..............................................................................................................................11
2.5 EXTERNAL CONNECTORS ..............................................................................................................................12
2.5.1 ANALOG INPUT connectors............................................................................................................12
2.5.2 CONTROL Connectors ....................................................................................................................13
2.5.3 ADC REFERENCE CLOCK Connectors ..............................................................................................14
2.5.4 OPTICAL LINK Connector................................................................................................................14
2.5.5 USB Port.........................................................................................................................................14
2.5.6 12V DC Input ..................................................................................................................................15
2.5.7 SPARE Link .....................................................................................................................................15
2.6 OTHER FRONT PANEL COMPONENTS..............................................................................................................15
2.6.1 Diagnostic LEDs..............................................................................................................................15
2.7 TECHNICAL SPECIFICATIONS TABLE.................................................................................................................16
3FUNCTIONAL DESCRIPTION .................................................................................................................... 18
3.1 ANALOG INPUT ..........................................................................................................................................18
3.1.1 DC Offset Common Setting ............................................................................................................18
3.1.2 DC Offset Individual Setting...........................................................................................................18
3.2 CLOCK DISTRIBUTION ..................................................................................................................................19
3.2.1 PLL Mode .......................................................................................................................................20
3.2.2 Reducing the Sampling Frequency.................................................................................................21
3.2.3 Decimation.....................................................................................................................................21
3.2.4 Trigger Clock ..................................................................................................................................21
3.3 ACQUISITION MODES ..................................................................................................................................22
3.3.1 Acquisition Run/Stop .....................................................................................................................22
3.3.2 Acquisition Triggering: Samples and Events ..................................................................................22
3.3.3 Multi-Event Memory Organization................................................................................................24
3.3.3.1 Custom Size Events....................................................................................................................................24
3.3.4 Event Structure ..............................................................................................................................25
3.3.4.1 Header....................................................................................................................................................... 25
3.3.4.2 Data........................................................................................................................................................... 26
3.3.4.3 Event Format Examples.............................................................................................................................27
3.3.5 Acquisition Synchronization...........................................................................................................28

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3.4 TRIGGER MANAGEMENT..............................................................................................................................29
3.4.1 Software Trigger ............................................................................................................................30
3.4.2 External Trigger .............................................................................................................................30
3.4.3 Self-Trigger ....................................................................................................................................30
3.4.4 Trigger Coincidence Level ..............................................................................................................31
3.4.5 Trigger Distribution........................................................................................................................34
3.4.5.1 Example.....................................................................................................................................................35
3.5 RESET,CLEAR AND DEFAULT CONFIGURATION..................................................................................................36
3.5.1 Global Reset...................................................................................................................................36
3.5.2 Memory Reset................................................................................................................................36
3.5.3 Timer Reset ....................................................................................................................................36
3.6 DATA TRANSFER CAPABILITIES.......................................................................................................................37
3.6.1 Block Transfer ................................................................................................................................37
3.6.2 Single Data Transfer ......................................................................................................................37
3.7 OPTICAL LINK AND USB ACCESS....................................................................................................................38
4DRIVERS & LIBRARIES............................................................................................................................. 39
4.1 DRIVERS ...................................................................................................................................................39
4.2 LIBRARIES..................................................................................................................................................39
5SOFTWARE TOOLS.................................................................................................................................. 41
5.1 CAENUPGRADER .......................................................................................................................................41
5.2 CAENCOMM DEMO...................................................................................................................................42
5.3 CAEN WAVEDUMP....................................................................................................................................43
5.4 DPP-QDC DEMO SOFTWARE.......................................................................................................................44
6HW INSTALLATION ................................................................................................................................. 45
6.1 POWER-ON SEQUENCE ................................................................................................................................45
6.2 POWER-ON STATUS ....................................................................................................................................45
7FIRMWARE AND UPGRADES................................................................................................................... 46
7.1 DEFAULT FIRMWARE UPGRADE .....................................................................................................................47
7.1.1 Default Firmware File Description .................................................................................................47
7.2 DPP FIRMWARE UPGRADE...........................................................................................................................48
7.2.1 DPP Firmware File Description.......................................................................................................48
7.3 TROUBLESHOOTING ....................................................................................................................................49
7.3.1 PCB revision 0 ................................................................................................................................49
8TECHNICAL SUPPORT ............................................................................................................................. 50
8.1 RETURNS AND REPAIRS................................................................................................................................50
8.2 TECHNICAL SUPPORT SERVICE .......................................................................................................................50

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LIST OF FIGURES
FIG.1.1: MOD.DT5740 BLOCK DIAGRAM ......................................................................................................................8
FIG.2.1: AC/DC POWER SUPPLY PROVIDED WITH THE MODULE............................................................................................9
FIG.2.2: MOD.DT5740 FRONT PANEL .........................................................................................................................11
FIG.2.3: MOD.DT5740 BACK PANEL ...........................................................................................................................11
FIG.2.4: ERNI SMC CONNECTORS...............................................................................................................................12
FIG.2.5: FLAT CABLE PUG FOR ERNI TO MCX INPUT CHANNELS .........................................................................................12
FIG.2.6: A746E PLUG TO ADAPT FROM ERNI TO LEMO INPUT CHANNELS ..........................................................................12
FIG.2.7: MCX CONNECTOR.........................................................................................................................................13
FIG.2.8: AMP CLK IN CONNECTOR .............................................................................................................................14
FIG.2.9: LC OPTICAL CONNECTOR ................................................................................................................................14
FIG.3.1: INPUT DIAGRAM............................................................................................................................................18
FIG.3.2: CLOCK DISTRIBUTION DIAGRAM........................................................................................................................19
FIG.3.3: TRIGGER OVERLAP.........................................................................................................................................23
FIG.3.4: EVENT ORGANIZATION ...................................................................................................................................27
FIG.3.5: BLOCK DIAGRAM OF TRIGGER MANAGEMENT ......................................................................................................29
FIG.3.6: SELF-TRIGGER GENERATION .............................................................................................................................30
FIG.3.7: TRIGGER REQUESTS RELATIONSHIP WITH MAJORITY LEVEL =0................................................................................31
FIG.3.8: TRIGGER REQUESTS RELATIONSHIP WITH MAJORITY LEVEL =1AND TTVAW ≠0...........................................................32
FIG.3.9: TRIGGER REQUESTS RELATIONSHIP WITH MAJORITY LEVEL =1AND TTVAW =0...........................................................33
FIG.3.10: TRIGGER CONFIGURATION ON GPO FRONT PANEL OUTPUT CONNECTOR.................................................................34
FIG.4.1: BLOCK DIAGRAM OF THE SOFTWARE LAYERS........................................................................................................40
FIG.5.1: CAENUPGRADER GRAPHICAL USER INTERFACE...................................................................................................41
FIG.5.2: CAENCOMM DEMO JAVA AND LABVIEW GRAPHICAL INTERFACE ..........................................................................42
FIG.5.3: CAEN WAVEDUMP ......................................................................................................................................43
FIG.6.1: FRONT PANEL LEDS STATUS AT POWER-ON ........................................................................................................45
LIST OF TABLES
TABLE 1.1: AVAILABLE ITEMS..........................................................................................................................................7
TABLE 2.2: FRONT PANEL LEDS....................................................................................................................................15
TABLE 2.3: MOD.DT5740 TECHNICAL SPECIFICATIONS ....................................................................................................16
TABLE 3.1: BUFFER ORGANIZATION...............................................................................................................................24
TABLE 3.2: PATTERN CONFIGURATION TABLE...................................................................................................................25

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Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer
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6
1Introduction
This document contains the full hardware description of the DT5740 module, and the principle of
operating as Waveform Digitizer basing on the default firmware for the waveform recording
(hereafter called default firmware).
Referred firmware version: 4.10_0.11.
For any reference to registers in this user manual, please refer to the UM5483 - 740 Family
Waveform Recording Firmware Registers document, free downloadable at the digitizer web
page.
1.1 Overview
The DT5740 is a desktop
module housing a 32 Channel
12 bit 62.5 MS/s desktop
module housing a 32 Channel
(65 MS/s using external clock)
Flash ADC Waveform Digitizer
with 2 Vpp dynamic range (10
Vpp available in the version
DT5740C) on a single ended
ERNI SMC input connector.
16 channels are also available on MCX coaxial connectors, while the A746E Adapter is required
for all the 32 channels to be available on as many single-ended LEMO connectors (see § 2.5.1).
Because of the high channel density, provided by the AD9222 Octal 12-bit 65 MSPS Analog-to-
Digital Converter, most channel settings are performed over “groups” of 8 channels (one group
per ADC chip).
The DC offset is adjustable via a 16-bit DAC on each 8-channel group in the ±1 V (@ 2 Vpp) or ±5 V
(@ 10 Vpp) range.
The ADC resolution and the sampling frequency make this digitizer well suited for mid-slow
detection systems (e.g. inorganic scintillators coupled to PMTs, gaseous detectors).
Each 8-channel group has a SRAM Multi-Event Buffer divisible into 1 ÷ 1024 buffers of
programmable size.
DT5740D version (EP3C40 Altera FPGA) supports special Digital Pulse Processing firmware for
Charge to Digital conversion (DPP-QDC). A x740D module running DPP-QDC firmware becomes
multi-channel data acquisition systems for Nuclear Physics or other applications requiring
radiation detection.
A common acquisition trigger signal (common to all the channels) can be fed externally via the
front panel TRG-IN input connector or via software. Alternatively, in the default firmware, each
8-channel group can generate a trigger request when at least one of the channels goes
under/over a programmable threshold. The requests from the groups are processed by the
board to generate the common trigger causing all the channels to acquire an event
simultaneously (in the DPP firmware, each channel can trigger independently of the others upon
the pulse under/over-threshold; the trigger request is used locally by the channel to acquire the
event).

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During the acquisition, data stream is continuously written in a circular memory buffer. When
the trigger occurs, the digitizer writes further samples for the post trigger and freezes the buffer
that can be read by one of the provided readout links. The acquisition can continue without any
dead time in a new buffer
DT5740 features a front panel CLK-IN connector as well as an internal PLL for clock synthesis
from internal/external references. Multiple DT5740 boards can be synchronized to a common
clock source ensuring Trigger time stamps alignment. The fan-in of an external clock signal to
each CLK-IN is required. Once synchronized, all data will be aligned and coherent across the
multi-board system.
The module houses USB 2.0 and Optical Link interfaces. USB 2.0 allows data transfers up to 30
MB/s. The Optical Link (CAEN proprietary CONET protocol) supports transfer rate of 80 MB/s and
offers Daisy chain capability. Therefore, it is possible to connect up to 8 ADC modules to a single
A2818 Optical Link Controller, or up to 32 using a A3818 (4-link version). Optical Link and USB
accesses are internally arbitrated.
Table 1.1: Available items
Code
Description
WDT5740XAAAA
DT5740 - 32 Ch. 12 bit 65 MS/s Digitizer: 192kS/ch, EP3C16, SE
WDT5740CXAAA
DT5740C - 10Vpp input 32 Ch 12 bit 65MS/s Digitizer: 192kS/ch, EP3C16, SE
WDT5740DXAAA
DT5740D - 32 Ch. 12 bit 62.5 MS/s Digitizer: 192kSch, EP3C40, SE
WFWDPPQDCAAA⁽*⁾
DPP-QDC- Digital Pulse Processing for Time Stamped Digital QDC (x740)
⁽*⁾Multi-license packs are also available. Please, refer to the Digitizer web page for the
relevant ordering options.
WA746EXAAAAA
A746E - 32 Ch. Adapter for Lemo connector
WA654XAAAAAA
A654 - Single Channel MCX to LEMO Cable Adapter
WA654K4AAAAA
A654 KIT4 - 4 MCX TO LEMO Cable Adapter
WA2818XAAAAA
A2818 - PCI Optical Link
WA3818AXAAAA
A3818 - PCIe 1 Optical Link
WA3818BXAAAA
A3818 - PCIe 2 Optical Link
WA3818CXAAAA
A3818 - PCIe 4 Optical Link
WA318XAAAAAA
A318 - Cable Adapter Single Ended to Differential
WAI2730XAAAA
AI2730 - Optical Fibre 30 m. simplex
WAI2720XAAAA
AI2720 - Optical Fibre 20 m. simplex
WAI2705XAAAA
AI2705 - Optical Fibre 5 m. simplex
WAI2703XAAAA
AI2703 - Optical Fibre 30cm. simplex
WAY2730XAAAA
AY2730 - Optical Fibre 30 m. duplex
WAY2720XAAAA
AY2720 - Optical Fibre 20 m. duplex
WAY2705XAAAA
AY2705 - Optical Fibre 5 m. duplex

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1.2 Block Diagram
DAC
AMC [FPGA]
ADC &
MEMORY
CONTROLLER
ADC
BUFFERS
x32 channels
ROC [FPGA]
- Readout control
- Optical link control
- USB interface control
- Trigger control
- External interface
control
MUX
OSC
CLOCK
MANAGER
(AD9520)
LOCAL BUS
CLK IN
TRG IN
GPI
USB
INPUTS
FRONT PANEL
GPO
OPTICAL LINK
Fig. 1.1: Mod. DT5740 Block Diagram
The function of each block will be explained in detail in the subsequent sections.

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2Technical Specifications
2.1 Packaging and Compliancy
The unit is a Desktop module housed in an alloy box (weight: 680 g) with the following
dimensions:
154 W x 50 H x 164 L mm³ (connectors not included)
154 W x 50 H x 171 L mm³ (including connectors).
CAUTION: to manage the product, consult the operating instructions provided.
A POTENTIAL RISK EXISTS IF THE OPERATING INSTRUCTIONS ARE
NOT FOLLOWED!
CAEN provides the specific document “Precautions for Handling, Storage and
Installation” available in the documentation tab of the product web page that
the user is mandatory to read before to operate with CAEN equipment
2.2 Power Requirements
The DT5740 module is powered by the external AC/DC stabilized power supply provided with the
digitizer and included in the delivered kit.
The board’s typical power consumption is 1.9A (@+12V).
NOTE: Using a different power supply source, like battery or linear type, it is recommended the
source to provide +12V and, at least, 2A; the power jack is a 2.1mm type, a suitable cable is the
RS 656-3816 type (or similar).
Fig. 2.1: AC/DC power supply provided with the module

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2.3 Cooling Management
Starting from revision 4 of the hardware (readable at 0xF04C address of the Configuration ROM),
the DT5740 features an automatic fan speed control to guarantee an appropriate cooling in
consequence of internal temperature variations. The automatic control is managed by the ROC
FPGA firmware from revision 4.4 on.
The user can manually set the fan speed through the bit[3] of the Fan Speed Control register:
Hardware revision ≥ 4 and ROC FPGA firmware revision ≥ 4.4
Bit[3] = 0 (default) sets the automatic fan speed control;
Bit[3] = 1 sets HIGH the fan speed.
Hardware revision < 4 and ROC FPGA firmware revision < 4.4
Bit[3] = 0 (default) sets LOW the fan speed;
Bit[3] = 1 sets HIGH the fan speed.
WARNING: It is recommended not to run ROC FPGA firmware revision < 4.4 on DT5740
with hardware revision ≥ 4 as the fans will work always at the maximum speed to prevent from
hardware damages, but with a high noisiness on the other hand.