Caen DT5740 Technical document

Technical
Information
Manual
MOD. DT5740
04 May 2016
Revision n. 12
32 CHANNEL 12 BIT
65 MS/S DIGITIZER
MANUAL REV.12
NPO:
00100/09:5740x.MUTx/12

CAEN S.p.A.
Via Vetraia, 11 55049 Viareggio (LU) - ITALY
Tel. [phone] Fax [phone]
[email protected]
www.caen.it
© CAEN SpA –2016
Disclaimer
No part of this manual may be reproduced in any form or by any means, electronic, mechanical, recording, or
otherwise, without the prior written permission of CAEN SpA.
The information contained herein has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. CAEN SpA reserves the right to modify its products specifications without
giving any notice; for up to date information please visit www.caen.it.
MADE IN ITALY: We stress the fact that all the boards are made in Italy because in this globalized world, where
getting the lowest possible price for products sometimes translates into poor pay and working conditions for the
people who make them, at least you know that who made your board was reasonably paid and worked in a safe
environment. (this obviously applies only to the boards marked "MADE IN ITALY", we cannot attest to the
manufacturing process of "third party" boards).

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TABLE OF CONTENTS
1INTRODUCTION........................................................................................................................................6
1.1 OVERVIEW ..................................................................................................................................................6
1.2 BLOCK DIAGRAM..........................................................................................................................................8
2TECHNICAL SPECIFICATIONS..................................................................................................................... 9
2.1 PACKAGING AND COMPLIANCY........................................................................................................................9
2.2 POWER REQUIREMENTS.................................................................................................................................9
2.3 COOLING MANAGEMENT .............................................................................................................................10
2.4 FRONT AND BACK PANEL..............................................................................................................................11
2.5 EXTERNAL CONNECTORS ..............................................................................................................................12
2.5.1 ANALOG INPUT connectors............................................................................................................12
2.5.2 CONTROL Connectors ....................................................................................................................13
2.5.3 ADC REFERENCE CLOCK Connectors ..............................................................................................14
2.5.4 OPTICAL LINK Connector................................................................................................................14
2.5.5 USB Port.........................................................................................................................................14
2.5.6 12V DC Input ..................................................................................................................................15
2.5.7 SPARE Link .....................................................................................................................................15
2.6 OTHER FRONT PANEL COMPONENTS..............................................................................................................15
2.6.1 Diagnostic LEDs..............................................................................................................................15
2.7 TECHNICAL SPECIFICATIONS TABLE.................................................................................................................16
3FUNCTIONAL DESCRIPTION .................................................................................................................... 18
3.1 ANALOG INPUT ..........................................................................................................................................18
3.1.1 DC Offset Common Setting ............................................................................................................18
3.1.2 DC Offset Individual Setting...........................................................................................................18
3.2 CLOCK DISTRIBUTION ..................................................................................................................................19
3.2.1 PLL Mode .......................................................................................................................................20
3.2.2 Reducing the Sampling Frequency.................................................................................................21
3.2.3 Decimation.....................................................................................................................................21
3.2.4 Trigger Clock ..................................................................................................................................21
3.3 ACQUISITION MODES ..................................................................................................................................22
3.3.1 Acquisition Run/Stop .....................................................................................................................22
3.3.2 Acquisition Triggering: Samples and Events ..................................................................................22
3.3.3 Multi-Event Memory Organization................................................................................................24
3.3.3.1 Custom Size Events....................................................................................................................................24
3.3.4 Event Structure ..............................................................................................................................25
3.3.4.1 Header....................................................................................................................................................... 25
3.3.4.2 Data........................................................................................................................................................... 26
3.3.4.3 Event Format Examples.............................................................................................................................27
3.3.5 Acquisition Synchronization...........................................................................................................28

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3.4 TRIGGER MANAGEMENT..............................................................................................................................29
3.4.1 Software Trigger ............................................................................................................................30
3.4.2 External Trigger .............................................................................................................................30
3.4.3 Self-Trigger ....................................................................................................................................30
3.4.4 Trigger Coincidence Level ..............................................................................................................31
3.4.5 Trigger Distribution........................................................................................................................34
3.4.5.1 Example.....................................................................................................................................................35
3.5 RESET,CLEAR AND DEFAULT CONFIGURATION..................................................................................................36
3.5.1 Global Reset...................................................................................................................................36
3.5.2 Memory Reset................................................................................................................................36
3.5.3 Timer Reset ....................................................................................................................................36
3.6 DATA TRANSFER CAPABILITIES.......................................................................................................................37
3.6.1 Block Transfer ................................................................................................................................37
3.6.2 Single Data Transfer ......................................................................................................................37
3.7 OPTICAL LINK AND USB ACCESS....................................................................................................................38
4DRIVERS & LIBRARIES............................................................................................................................. 39
4.1 DRIVERS ...................................................................................................................................................39
4.2 LIBRARIES..................................................................................................................................................39
5SOFTWARE TOOLS.................................................................................................................................. 41
5.1 CAENUPGRADER .......................................................................................................................................41
5.2 CAENCOMM DEMO...................................................................................................................................42
5.3 CAEN WAVEDUMP....................................................................................................................................43
5.4 DPP-QDC DEMO SOFTWARE.......................................................................................................................44
6HW INSTALLATION ................................................................................................................................. 45
6.1 POWER-ON SEQUENCE ................................................................................................................................45
6.2 POWER-ON STATUS ....................................................................................................................................45
7FIRMWARE AND UPGRADES................................................................................................................... 46
7.1 DEFAULT FIRMWARE UPGRADE .....................................................................................................................47
7.1.1 Default Firmware File Description .................................................................................................47
7.2 DPP FIRMWARE UPGRADE...........................................................................................................................48
7.2.1 DPP Firmware File Description.......................................................................................................48
7.3 TROUBLESHOOTING ....................................................................................................................................49
7.3.1 PCB revision 0 ................................................................................................................................49
8TECHNICAL SUPPORT ............................................................................................................................. 50
8.1 RETURNS AND REPAIRS................................................................................................................................50
8.2 TECHNICAL SUPPORT SERVICE .......................................................................................................................50

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LIST OF FIGURES
FIG.1.1: MOD.DT5740 BLOCK DIAGRAM ......................................................................................................................8
FIG.2.1: AC/DC POWER SUPPLY PROVIDED WITH THE MODULE............................................................................................9
FIG.2.2: MOD.DT5740 FRONT PANEL .........................................................................................................................11
FIG.2.3: MOD.DT5740 BACK PANEL ...........................................................................................................................11
FIG.2.4: ERNI SMC CONNECTORS...............................................................................................................................12
FIG.2.5: FLAT CABLE PUG FOR ERNI TO MCX INPUT CHANNELS .........................................................................................12
FIG.2.6: A746E PLUG TO ADAPT FROM ERNI TO LEMO INPUT CHANNELS ..........................................................................12
FIG.2.7: MCX CONNECTOR.........................................................................................................................................13
FIG.2.8: AMP CLK IN CONNECTOR .............................................................................................................................14
FIG.2.9: LC OPTICAL CONNECTOR ................................................................................................................................14
FIG.3.1: INPUT DIAGRAM............................................................................................................................................18
FIG.3.2: CLOCK DISTRIBUTION DIAGRAM........................................................................................................................19
FIG.3.3: TRIGGER OVERLAP.........................................................................................................................................23
FIG.3.4: EVENT ORGANIZATION ...................................................................................................................................27
FIG.3.5: BLOCK DIAGRAM OF TRIGGER MANAGEMENT ......................................................................................................29
FIG.3.6: SELF-TRIGGER GENERATION .............................................................................................................................30
FIG.3.7: TRIGGER REQUESTS RELATIONSHIP WITH MAJORITY LEVEL =0................................................................................31
FIG.3.8: TRIGGER REQUESTS RELATIONSHIP WITH MAJORITY LEVEL =1AND TTVAW ≠0...........................................................32
FIG.3.9: TRIGGER REQUESTS RELATIONSHIP WITH MAJORITY LEVEL =1AND TTVAW =0...........................................................33
FIG.3.10: TRIGGER CONFIGURATION ON GPO FRONT PANEL OUTPUT CONNECTOR.................................................................34
FIG.4.1: BLOCK DIAGRAM OF THE SOFTWARE LAYERS........................................................................................................40
FIG.5.1: CAENUPGRADER GRAPHICAL USER INTERFACE...................................................................................................41
FIG.5.2: CAENCOMM DEMO JAVA AND LABVIEW GRAPHICAL INTERFACE ..........................................................................42
FIG.5.3: CAEN WAVEDUMP ......................................................................................................................................43
FIG.6.1: FRONT PANEL LEDS STATUS AT POWER-ON ........................................................................................................45
LIST OF TABLES
TABLE 1.1: AVAILABLE ITEMS..........................................................................................................................................7
TABLE 2.2: FRONT PANEL LEDS....................................................................................................................................15
TABLE 2.3: MOD.DT5740 TECHNICAL SPECIFICATIONS ....................................................................................................16
TABLE 3.1: BUFFER ORGANIZATION...............................................................................................................................24
TABLE 3.2: PATTERN CONFIGURATION TABLE...................................................................................................................25

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1Introduction
This document contains the full hardware description of the DT5740 module, and the principle of
operating as Waveform Digitizer basing on the default firmware for the waveform recording
(hereafter called default firmware).
Referred firmware version: 4.10_0.11.
For any reference to registers in this user manual, please refer to the UM5483 - 740 Family
Waveform Recording Firmware Registers document, free downloadable at the digitizer web
page.
1.1 Overview
The DT5740 is a desktop
module housing a 32 Channel
12 bit 62.5 MS/s desktop
module housing a 32 Channel
(65 MS/s using external clock)
Flash ADC Waveform Digitizer
with 2 Vpp dynamic range (10
Vpp available in the version
DT5740C) on a single ended
ERNI SMC input connector.
16 channels are also available on MCX coaxial connectors, while the A746E Adapter is required
for all the 32 channels to be available on as many single-ended LEMO connectors (see § 2.5.1).
Because of the high channel density, provided by the AD9222 Octal 12-bit 65 MSPS Analog-to-
Digital Converter, most channel settings are performed over “groups” of 8 channels (one group
per ADC chip).
The DC offset is adjustable via a 16-bit DAC on each 8-channel group in the ±1 V (@ 2 Vpp) or ±5 V
(@ 10 Vpp) range.
The ADC resolution and the sampling frequency make this digitizer well suited for mid-slow
detection systems (e.g. inorganic scintillators coupled to PMTs, gaseous detectors).
Each 8-channel group has a SRAM Multi-Event Buffer divisible into 1 ÷ 1024 buffers of
programmable size.
DT5740D version (EP3C40 Altera FPGA) supports special Digital Pulse Processing firmware for
Charge to Digital conversion (DPP-QDC). A x740D module running DPP-QDC firmware becomes
multi-channel data acquisition systems for Nuclear Physics or other applications requiring
radiation detection.
A common acquisition trigger signal (common to all the channels) can be fed externally via the
front panel TRG-IN input connector or via software. Alternatively, in the default firmware, each
8-channel group can generate a trigger request when at least one of the channels goes
under/over a programmable threshold. The requests from the groups are processed by the
board to generate the common trigger causing all the channels to acquire an event
simultaneously (in the DPP firmware, each channel can trigger independently of the others upon
the pulse under/over-threshold; the trigger request is used locally by the channel to acquire the
event).

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During the acquisition, data stream is continuously written in a circular memory buffer. When
the trigger occurs, the digitizer writes further samples for the post trigger and freezes the buffer
that can be read by one of the provided readout links. The acquisition can continue without any
dead time in a new buffer
DT5740 features a front panel CLK-IN connector as well as an internal PLL for clock synthesis
from internal/external references. Multiple DT5740 boards can be synchronized to a common
clock source ensuring Trigger time stamps alignment. The fan-in of an external clock signal to
each CLK-IN is required. Once synchronized, all data will be aligned and coherent across the
multi-board system.
The module houses USB 2.0 and Optical Link interfaces. USB 2.0 allows data transfers up to 30
MB/s. The Optical Link (CAEN proprietary CONET protocol) supports transfer rate of 80 MB/s and
offers Daisy chain capability. Therefore, it is possible to connect up to 8 ADC modules to a single
A2818 Optical Link Controller, or up to 32 using a A3818 (4-link version). Optical Link and USB
accesses are internally arbitrated.
Table 1.1: Available items
Code
Description
WDT5740XAAAA
DT5740 - 32 Ch. 12 bit 65 MS/s Digitizer: 192kS/ch, EP3C16, SE
WDT5740CXAAA
DT5740C - 10Vpp input 32 Ch 12 bit 65MS/s Digitizer: 192kS/ch, EP3C16, SE
WDT5740DXAAA
DT5740D - 32 Ch. 12 bit 62.5 MS/s Digitizer: 192kSch, EP3C40, SE
WFWDPPQDCAAA⁽*⁾
DPP-QDC- Digital Pulse Processing for Time Stamped Digital QDC (x740)
⁽*⁾Multi-license packs are also available. Please, refer to the Digitizer web page for the
relevant ordering options.
WA746EXAAAAA
A746E - 32 Ch. Adapter for Lemo connector
WA654XAAAAAA
A654 - Single Channel MCX to LEMO Cable Adapter
WA654K4AAAAA
A654 KIT4 - 4 MCX TO LEMO Cable Adapter
WA2818XAAAAA
A2818 - PCI Optical Link
WA3818AXAAAA
A3818 - PCIe 1 Optical Link
WA3818BXAAAA
A3818 - PCIe 2 Optical Link
WA3818CXAAAA
A3818 - PCIe 4 Optical Link
WA318XAAAAAA
A318 - Cable Adapter Single Ended to Differential
WAI2730XAAAA
AI2730 - Optical Fibre 30 m. simplex
WAI2720XAAAA
AI2720 - Optical Fibre 20 m. simplex
WAI2705XAAAA
AI2705 - Optical Fibre 5 m. simplex
WAI2703XAAAA
AI2703 - Optical Fibre 30cm. simplex
WAY2730XAAAA
AY2730 - Optical Fibre 30 m. duplex
WAY2720XAAAA
AY2720 - Optical Fibre 20 m. duplex
WAY2705XAAAA
AY2705 - Optical Fibre 5 m. duplex

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1.2 Block Diagram
DAC
AMC [FPGA]
ADC &
MEMORY
CONTROLLER
ADC
BUFFERS
x32 channels
ROC [FPGA]
- Readout control
- Optical link control
- USB interface control
- Trigger control
- External interface
control
MUX
OSC
CLOCK
MANAGER
(AD9520)
LOCAL BUS
CLK IN
TRG IN
GPI
USB
INPUTS
FRONT PANEL
GPO
OPTICAL LINK
Fig. 1.1: Mod. DT5740 Block Diagram
The function of each block will be explained in detail in the subsequent sections.

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2Technical Specifications
2.1 Packaging and Compliancy
The unit is a Desktop module housed in an alloy box (weight: 680 g) with the following
dimensions:
154 W x 50 H x 164 L mm³ (connectors not included)
154 W x 50 H x 171 L mm³ (including connectors).
CAUTION: to manage the product, consult the operating instructions provided.
A POTENTIAL RISK EXISTS IF THE OPERATING INSTRUCTIONS ARE
NOT FOLLOWED!
CAEN provides the specific document “Precautions for Handling, Storage and
Installation” available in the documentation tab of the product web page that
the user is mandatory to read before to operate with CAEN equipment
2.2 Power Requirements
The DT5740 module is powered by the external AC/DC stabilized power supply provided with the
digitizer and included in the delivered kit.
The board’s typical power consumption is 1.9A (@+12V).
NOTE: Using a different power supply source, like battery or linear type, it is recommended the
source to provide +12V and, at least, 2A; the power jack is a 2.1mm type, a suitable cable is the
RS 656-3816 type (or similar).
Fig. 2.1: AC/DC power supply provided with the module

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2.3 Cooling Management
Starting from revision 4 of the hardware (readable at 0xF04C address of the Configuration ROM),
the DT5740 features an automatic fan speed control to guarantee an appropriate cooling in
consequence of internal temperature variations. The automatic control is managed by the ROC
FPGA firmware from revision 4.4 on.
The user can manually set the fan speed through the bit[3] of the Fan Speed Control register:
Hardware revision ≥ 4 and ROC FPGA firmware revision ≥ 4.4
Bit[3] = 0 (default) sets the automatic fan speed control;
Bit[3] = 1 sets HIGH the fan speed.
Hardware revision < 4 and ROC FPGA firmware revision < 4.4
Bit[3] = 0 (default) sets LOW the fan speed;
Bit[3] = 1 sets HIGH the fan speed.
WARNING: It is recommended not to run ROC FPGA firmware revision < 4.4 on DT5740
with hardware revision ≥ 4 as the fans will work always at the maximum speed to prevent from
hardware damages, but with a high noisiness on the other hand.

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2.4 Front and Back Panel
Fig. 2.2: Mod. DT5740 front panel
Fig. 2.3: Mod. DT5740 back panel

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2.5 External Connectors
2.5.1 ANALOG INPUT connectors
The module has 32 channels on single ended ERNI SMC input connector (see
Fig. 2.4).
Fig. 2.4: ERNI SMC Connectors
Function: Analog input, single ended, input dynamics: 2Vpp, Zin=50Ω(DT5740C: 10Vpp Zin=1kΩ).
Mechanical specifications:
Two ERNI SMC-114805 Dual Row 68pin connectors.
Even channels (0, 2…30) are also available on MCX coaxial connectors. To use the 16 MCX
channels, the provided flat cable must be plugged between the lower and upper ERNI connectors
(see Fig. 2.5).
Fig. 2.5: Flat cable pug for ERNI to MCX input channels
All 64 channels can be available on as many single-ended LEMO connectors by using the A746E
adapter (see Fig. 2.6).
Fig. 2.6: A746E plug to adapt from ERNI to LEMO input channels

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Fig. 2.7: MCX connector
Function:
Analog input, single ended, input dynamics: 2Vpp Zin = 50Ω(DT5740C: 10Vpp Zin = 1KΩ)
Mechanical specifications:
MCX connector (CS 85MCX-50-0-16 SUHNER)
Absolute max analog input voltage (@2Vpp FSR) = 6Vpp (with Vrail max to +6V or -6V) for any
DAC offset value.
NOTE: ensure that alignment is correct during insertion/extraction operations; incorrect
alignment may lead to connector damage.
2.5.2 CONTROL Connectors
Function:
•GPO:digital output connector (NIM/TTL, on Rt= 50Ω) to propagate
-the internal trigger sources;
-the channel probes (i.e. signals from the mezzanines);
-GPI signal
according to register addresses 0x8110 and 0x811C, or
-the motherboard probes (i.e. signals from the motherboard), like the Run
signal, ClkOut signal, ClockPhase signal, PLL_Unlock signal or Busy signal
according to register address 0x811C.
•TRG-IN: digital input connector (NIM/TTL, Zin = 50Ω) for the external trigger.
•GPI: SYNC/START/STOP digital input connector (NIM/TTL, Zin = 50Ω) configurable as time
stamp reset (see § 3.5.3) or acquisition start/stop (see § 3.3.1).
Mechanical specifications:
00-type LEMO connectors

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2.5.3 ADC REFERENCE CLOCK Connectors
GND
CLK-
CLK+
Fig. 2.8: AMP CLK IN Connector
Function:
CLK IN: External clock/Reference input, AC coupled (diff. LVDS, ECL, PECL, LVPECL, CML), Zdiff =
100Ω. CAEN provides single-ended to differential A318 cable adapter (see Table 1.1).
Mechanical specifications:
AMP 3-102203-4 AMP MODUII
2.5.4 OPTICAL LINK Connector
Fig. 2.9: LC Optical Connector
Function:
Optical LINK connector for data readout and flow control (up to 80 MB/s transfer rate). Daisy
chainable. Compliant to Multimode 62.5/125μm cable featuring LC connectors on both sides.
CAEN provides optical fiber cable selection for A3818 and A2818 Controllers (see Table 1.1) with
duplex connector on the controller side and two simplex connectors on the digitizer side; the
simplex connector with the black wrap is for the RX line (lower) and the one with the red wrap is
for the TX (higher).
Mechanical specifications:
SFF Transceiver series, FTLF8519F-2KNL type (LC connectors).
2.5.5 USB Port
Function:
USB connector for data readout and flow control (up tp 30 MB/s transfer rate). Compliant to USB
2.0 and USB 1.1.
Mechanical specifications:
B-type 787780-2 USB connector.

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2.5.6 12V DC Input
Function:
Input connector for the Desktop digitizer 12V main power supply from the external AC/DC
adapter.
Mechanical specifications:
RAPC722X PCB DC Power Jack.
2.5.7 SPARE Link
Function:
Auxiliary connector reserved for CAEN usage.
Mechanical specifications:
3M-7610-5002 connector.
2.6 Other Front Panel Components
2.6.1 Diagnostic LEDs
The front panel hosts the following LEDs:
Table 2.2: Front panel LEDs
Name:
Colour:
Function:
CLK IN
green
Indicates that the external clock is enabled
TTL
green
Indicates that the standard TTL is set for GPO, TRG-IN and GPI
NIM
green
Indicates that the standard NIM is set for GPO, TRG-IN and GPI
LINK
green/yellow
Network present; Data transfer activity
USB
green
The right green LED indicates the network presence; the left yellow LED signals the data
transfer activity
PLL LOCK
green
Indicates that the PLL is locked to the reference clock
PLL BYPS
green
NOT USED
RUN
green
Indicates that the acquisition is running (data taking)
TRG
green
Indicates that the trigger is accepted
DRDY
green
Indicates that the event/data is present in the Output Buffer
BUSY
red
Indicates that all the buffers are full for at least one channel

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2.7 Technical Specifications Table
Table 2.3: Mod. DT5740 technical specifications
GENERAL
Form Factor
154x50x164 mm3(WxHxD) Desktop
Weight
680 g
ANALOG INPUT
Channels
32 channels
Single-ended
Connector
ERNI SMC Dual
Row 68-pin
Bandwidth
30 MHz
Impedance
Zin = Ω@ 2Vpp
Zin = 1 kΩ@ 10Vpp
Full Scale Range
2 Vpp / 10 Vpp(1)
Offset
Programmable 16-bit DAC for DC
offset adjustment on each channel.
Range: ±1 V (@2Vpp); ±0.5 V (@10Vpp)
⁽¹⁾ “size1 / size2” denotes different model versions
DIGITAL CONVERSION
Resolution
12 bits
Sampling Rate
62.5 MS/s simultaneously on each channel
65 MS/s using external clock
SYSTEM PERFORMANCE
ENOB
11.20
(48 kS Buffer)
SINAD
69.20 dB
(48 kS Buffer, open input)
THD
87.10 dB
SFDR
94.9 dB
SIGMA
0.50 LSB rms
ADC CLOCK GENERATION
Clock source: internal/external; on-board programmable PLL provides generation of the main
board clocks from internal (50 MHz local Oscillator) or external (CLK-IN connector) reference
I/O CONNECTORS
CLK-IN (AMP Modu II)
AC coupled differential input clock
LVDS, ECL, PECL, LVPECL, CML
(single ended NIM/TTL available by
A318 adapter)
Jitter<100ppm requested
GPO (LEMO)
General purpose digital output;
NIM/TTL; Rt= 50 Ω
GPI (LEMO)
General purpose digital input
NIM/TTL
Zin = 50 Ω
TRG-IN (LEMO)
External trigger digital input
NIM/TTL; Zin = 50 Ω
MEMORY
192 kS/ch Multi-event Buffer divisible into 1 ÷ 1024 buffers
Independent read and write access; programmable event size and pre-post trigger
TRIGGER
Trigger Source
Self-trigger channel over/under-
threshold for Common (default
firmware) or Individual (DPP
firmware only) Trigger generation
External-trigger: Common Trigger
by TRG-IN or individual by LVDS
(DPP firmware only) connector
Software-trigger: Common Trigger
by software command
Trigger Propagation
GPO programmable digital output
Trigger Time Stamp
Default FW: 31-bit counter, 16 ns resolution, 17 s range;
48-bit extension available by firmware
DPP-QDC FW: 32-bit counter, 16 ns resolution, 68 s
range; 48-bit extension by firmware; 64-bit extension by
software
SYNCHRONIZATION
Clock Propagation
One-to-many: clock distribution
from an external clock source on
CLK-IN connector
Acquisition Synchronization
Sync, Start/Stop through digital I/O (GPI or TRG-IN input;
GPO output)
Trigger Time Stamps Alignment
By GPI input connector

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ADC & MEMORY
CONTROLLER
Altera Cyclone EP3C16 or EP3C40 (DT5740D only)
One FPGA serves 16 channels
COMMUNICATION
INTERFACE
Optical Link
CAEN CONET proprietary protocol
Up to 80 MB/s transfer rate
Daisy chainable: it is possible to
connect up to 8 or 32 ADC modules
to a single Optical Link Controller
(respectively A2818 or A3818)
USB
USB 2.0 compliant
Up to 30 MB/s transfer rate
DPP FW SUPPORTED
DPP-QDC firmware for the Charge to Digital Conversion supported only by DT5740D version
FIRMWARE UPGRADE
Firmware can be upgraded via USB/Optical Link
SOFTWARE
General purpose C libraries, configuration tools, readout software (Windows and Linux
support)
POWER CONSUMPTIONS
1.9 A @ 12V (Typ.)

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3Functional Description
3.1 Analog Input
Input dynamic is 2Vpp (Zin = 50 Ω). A 10Vpp (Zin = 1 kΩ) dynamic is available on request. By means
of a 16-bit DAC it is possible to add up to a ±1V DC offset (±5V @10Vpp) in order to preserve the
full dynamic range also with unipolar positive or negative input signals.
The input bandwidth ranges from DC to 30 MHz by 2nd order linear phase anti-aliasing low pass
filter.
OpAmp
Rin
DAC
Vref
12 bit
ADC
Input
FPGA
+1
0
+2
-1
-2
Input Dynamic Range: 2 Vpp
Positive Unipolar
DAC = FSR
16 bit Negative Unipolar
DAC = 0
Bipolar
DAC = FSR/2
:
Fig. 3.1: Input diagram
3.1.1 DC Offset Common Setting
Setting the DC offset requires a write access at register addresses 0x1n98. The DC offset value
will be then applied to all the 8 channels of group n.
3.1.2 DC Offset Individual Setting
It is possible to apply a 8-bit positive digital offset individually to each channel inside a group to
finely correct the baseline mismatch.
The two 32-bit registers that encode the eight unsigned values for group n (n = 0..7) are:
0x10C0 + 0x100 * n -> Correction values for channel offset 0..3
0x10C4 + 0x100 * n -> Correction values for channel offset 4..7
Please, see UM5483 - 740 Family Waveform Recording Firmware Registers document for details.
NOTE: DC Offset individual setting is supported from the mezzanine (AMC FPGA) firmware
revision 0.10 on.

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3.2 Clock Distribution
MUX
OSC
CLK-IN
50MHz
REF-CLK
Trigger & Sync
Logic
TRG IN
Local Bus
Interface
Acquisition
& Memory
Control
Logic
MEZZANINE
TRIGGER
SYNC
LOCAL-TRGs
MUX
Phase
Detector
AD9520
CLK1 Sdiv
Sdiv
Rdiv
REFIN
Charge
Pump
INTCLK
CTRL
SPI
Ldiv
Odiv
Ndiv
SAMP-CLK0
FPGA (AMC)
ADC
SYNC
SRAM
256Klocations
FIFO
ADC
CH_IN
Ldel
Odel
Local Bus
Interface
FPGA (ROC)
SYNCB
TRG-CLK
SyncB
OSC-CLK
8
DFF
ADC
ADC
SCLK
DATA/CLKOUT
FANOUT
SCLK
SCLK
SCLK
DATA/CLKOUT
DATA/CLKOUT
DATA/CLKOUT
8CH
8CH
8CH
8CH
Local Bus
Interface
Acquisition
& Memory
Control
Logic
FPGA (AMC)
SYNC
SRAM
256Klocations
FIFO
RAMCLK
DATA
144BIT
DATA
144BIT
RAMCLK
LOCAL BUS
MUX
Phase
Detector
CLK1 Sdiv
Rdiv
REFIN
INTCLK
CTRL
Ldiv
Odiv
Ndiv
Ldel
Odel
SYNCB
VCXO
Fig. 3.2: Clock distribution diagram
The module clock distribution takes place on two domains: OSC-CLK and REF-CLK; the former is a
fixed 50MHz clock provided by an on board oscillator, the latter provides the ADC sampling clock.
OSC-CLK handles Local Bus (communication between motherboard and mezzanine boards; see
red traces in Fig. 3.2).
REF-CLK handles ADC sampling, trigger logic, acquisition logic (samples storage into RAM, buffer
freezing on trigger) through a clock chain. Such domain can use either an external (via front
panel signal) or an internal (via local oscillator) source, in the latter case OSC-CLK and REF-CLK
will be synchronous (the operation mode remains the same anyway).
DT5740 uses an integrated phase-locked-loop (PLL) and clock distribution device (AD9520). It is
used to generate the sampling clock for ADCs and mezzanine FPGA (SAMP-CLK0/SAMP-CLK1), as
well as the trigger logic synchronization clock (TRG-CLK).

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20
Both clocks can be generated from the internal oscillator (50 MHz) or from external clock input
(CLK IN). By default, board uses the internal clock as PLL reference (REF-CLK). External clock can
be selected by register access (bit[6] of 0x8100). The external clock signal must be differential
(LVDS, ECL, PECL, LVPECL, CML) with a jitter lower than 100ppm (see Table 2.3).
AD9520 configuration can be changed and stored into non-volatile memory. AD9520
configuration change is primarly intended to be used for external PLL reference clock frequency
change.
DT5740 locks to an external 50 MHz clock with default AD9520 configuration (see § 3.2.1).
Please contact CAEN technical support (see § 8) for more information and configuration tools.
Refer also to AD9520 data sheet for more details:
http://www.analog.com/static/imported-files/data_sheets/AD9520-3.pdf
(in case the active link above doesn’t work, copy and paste it on the internet browser)
3.2.1 PLL Mode
As introduced in § 3.2, the source of the REF-CLK signal can be external (see Fig. 3.2) on CLK-IN
front panel connector or internal from the 50 MHz local oscillator.
The user can configure the board to sense the external clock by setting bit[6] of the register
address 0x8100.
The following options are allowed:
1. 50 MHz internal clock source –It’s the standard operating mode, where the default AD9520
configuration doesn’t require to be changed. OSC-CLK = REF-CLK.
2. 50 MHz external clock source –In this case, it is not required to reprogram the AD9520
dividers, as the external clock reference is identical to the frequency of the internal oscillator.
CLK-IN = OSC-CLK = REF-CLK.
3. External clock source different from 50 MHz –In this case, it is necessary to re-program the
AD9520.
NOTE: please, contact CAEN (§ 8) for the feasibility of point 3 and to receive the PLL
programming file.
PLL programming files can then be loaded by the user by using the CAENUpgrader software tool.
See § 5.1 for the program description and documentation reference.