Caen N957 Technical document

Technical
Information
Manual
MOD. N957
28 May 2012
Revision n. 6
8K MULTICHANNEL
ANALYZER
NPO:
00105/04:N957x.MUTx/06

CAEN will repair or replace any product within the guarantee period if the Guarantor declares
that the product is defective due to workmanship or materials and has not been caused by
mishandling, negligence on behalf of the User, accident or any abnormal conditions or
operations.
CAEN declines all responsibility for damages or
injuries caused by an improper use of the Modules due
to negligence on behalf of the User. It is strongly
recommended to read thoroughly the CAEN User's
Manual before any kind of operation.
CAEN reserves the right to change partially or entirely the contents of this Manual at any time
and without giving any notice.
Disposal of the Product
The product must never be dumped in the Municipal Waste. Please check your local
regulations for disposal of electronics products.

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 3
TABLE OF CONTENTS
1.GENERAL DESCRIPTION.........................................................................................................................6
1.1OVERVIEW ...............................................................................................................................................6
2.TECHNICAL SPECIFICATIONS..............................................................................................................7
2.1PACKAGING..............................................................................................................................................7
2.2POWER REQUIREMENTS ............................................................................................................................7
2.3FRONT AND BACK PANEL..........................................................................................................................8
2.4INPUT/OUTPUT CONNECTIONS..................................................................................................................9
2.5FRONT PANEL DISPLAYS ...........................................................................................................................9
2.6INTERNAL HARDWARE COMPONENTS .....................................................................................................10
2.6.1Switches.........................................................................................................................................10
2.6.2Firmware jumpers.........................................................................................................................10
2.7TECHNICAL SPECIFICATION TABLE .........................................................................................................11
2.8ANALOG TO DIGITAL CONVERSION .........................................................................................................11
2.8.1Analog to digital conversion timing ..............................................................................................12
2.8.2Pile Up Rejection...........................................................................................................................14
2.9DATA READOUT......................................................................................................................................15
2.10SCALER AND TIMERS..............................................................................................................................16
2.10.1Scaler description..........................................................................................................................16
2.10.2Timers description.........................................................................................................................16
2.11FIRMWARE UPGRADE..............................................................................................................................18
2.11.1N957Upgrade command parameters ............................................................................................18
3.SOFTWARE INTERFACE........................................................................................................................20
3.1REGISTER MAP........................................................................................................................................20
3.2STATUS REGISTER (0X00, R)...................................................................................................................21
3.3CONTROL REGISTER (0X01, R/W)............................................................................................................21
3.4FIRMWARE REVISION REGISTER (0X02, R) ..............................................................................................22
3.5FIRMWARE DOWNLOAD REGISTER (0X03, R/W) ......................................................................................22
3.6FLASH ENABLE REGISTER (0X04, R/W)...................................................................................................22
3.7PULSER REGISTER (0X05, R/W)...............................................................................................................22
3.8DAC REGISTER (0X06, R/W)...................................................................................................................22
3.9BLOCK DIMENSION REGISTER (0X07, R/W).............................................................................................22
3.10POTENTIOMETER CONTROL REGISTER (0X08, R/W) ................................................................................23

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 4
3.11CALIBRATION SET REGISTER (0X09, W)..................................................................................................23
3.12CALIBRATION CLEAR REGISTER (0X0A, W)............................................................................................23
3.13SCRATCH REGISTER (0X0B, R/W)............................................................................................................23
3.14BUFFER OCCUPANCY REGISTER (0X0C, R/W).........................................................................................23
3.15SCALER LOW REGISTER (0X0D, R) .........................................................................................................23
3.16SCALER HIGH REGISTER (0X0E, R).........................................................................................................23
3.17TIMER LOW REGISTER (0X0F, R/W)........................................................................................................24
3.18TIMER HIGH REGISTER (0X10, R)............................................................................................................24
3.19LIVETIME LOW REGISTER (0X11, R) .......................................................................................................24
3.20LIVETIME HIGH REGISTER (0X12, R).......................................................................................................24
3.21SOFTWARE CLEAR REGISTER (0X13, W) .................................................................................................24
3.22SOFTWARE RESET REGISTER (0X14, W)..................................................................................................24
4.SOFTWARE TOOLS .................................................................................................................................25
4.1SOFTWARE INSTALLATION:GETTING STARTED ......................................................................................25
4.1.1Software installation: Windows.....................................................................................................25
4.1.1.1Software installation: Demo folder ...........................................................................................................26
4.1.1.2Software installation: Doc folder ..............................................................................................................26
4.1.1.3Software installation: LabView folder ......................................................................................................26
4.1.1.4Software installation: Lib Folder...............................................................................................................26
4.1.1.5Software installation: Upgrade folder .......................................................................................................26
4.1.2Driver installation.........................................................................................................................27
5.LIBRARY AND DEMO SOFTWARE OVERVIEW..............................................................................29
5.1N957TOOL LIBRARY ..............................................................................................................................29
5.1.1N957Tool library: Overview .........................................................................................................29
5.1.2N957Tool library: typical usage ...................................................................................................30
5.2DEMO SOFTWARE ...................................................................................................................................30
5.2.1Demo software: N957Demo..........................................................................................................30
5.2.1.1N957Demo: overview ...............................................................................................................................30
5.2.1.2N957Demo: settings..................................................................................................................................30
5.2.1.3N957Demo: configuration file format.......................................................................................................31
5.2.1.4N957Demo: output data format.................................................................................................................32
5.2.1.5N957Demo: practical example..................................................................................................................32

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 5
LIST OF FIGURES
FIG.1.1: MOD.N957 BLOCK DIAGRAM ...............................................................................................................6
FIG.3.1: MOD.N957 FRONT PANEL .....................................................................................................................8
FIG.3.2: MOD.N957 PCB BOARDAND COMPONENT LOCATION.........................................................................10
FIG.3.3: SIGNAL CONVERSION TIMING AUTO GATE MODE (NO PILEUP).............................................................13
FIG.3.4: SIGNAL CONVERSION TIMING AUTO GATE MODE (TRAILING EDGE PILEUP).........................................13
FIG.3.5: SIGNAL CONVERSION TIMING EXTERNAL GATE MODE .........................................................................14
FIG.3.6: PUR TIMING FOR EVENT REJECTION (AUTO GATE MODE)....................................................................14
FIG.3.7: MAX DATA RATE VS.DATA BLOCK SIZE SETTING ..............................................................................15
FIG.3.8: LIVETIME STATUS (CONTROL REGISTER <0> =1AND AUTO GATE MODE) ..........................................17
FIG.3.9: LIVETIME STATUS (CONTROL REGISTER <0> =1AND EXTERNAL GATE MODE)...................................17
FIG.5.1: INSTALLATION FOLDER STRUCTURE.....................................................................................................26
FIG.5.2: PROGRAM MENU DEMO ........................................................................................................................27
FIG.5.3: USB DRIVER INSTALLED......................................................................................................................27
FIG.6.1: SOFTWARE LAYERS..............................................................................................................................29
FIG.6.2: N957DEMO PROMPT ............................................................................................................................33
FIG.6.3: N975DEMO IN ACQUISITION MODE ......................................................................................................33
FIG.6.4: HISTOGRAM PLOT OF 60CO SOURCE IN PROGRESS .................................................................................34
FIG.6.5: ACQUISITION REPORT...........................................................................................................................34
LIST OF TABLES
TABLE 2.1: POWER REQUIREMENTS......................................................................................................................7
TABLE 3.2: MOD.N957 TECHNICAL FEATURES .................................................................................................11

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 6
1. General description
1.1 Overview
The Mod. N957 is a 8k Multi-Channel (MCA) with USB port, housed in a 1-unit wide
standard NIM module. The multichannel analyzer performs the essential function of
collecting the data and producing output, in the form of converted value of input peaks.
The input pulses can be those produced by a standard spectroscopy amplifier. They can
be Gaussian, semi-Gaussian or square waves, unipolar (positive) or bipolar, in a range
from 0 to 10 V, with a rise time greater than 0.1 µs.
The trigger can be made “on signal” (Auto Gate mode) or “external” (External Gate
mode). In the first case a discriminator, with a settable threshold, enables the conversion.
In the second case, an external gate is fed to the module, via front panel GATE In
connector.
The input channel has one peak amplitude stretcher, the output of which is digitised by a
13 bit fast (0.8 s) ADC featuring a sliding scale technique, to improve the differential
non-linearity. Converted waveforms are stored into a 64 KSamples buffer memory.
The unit hosts an USB2.0 port (also compatible with USB 1.1), which permits a simple
control and data-acquisition via PC.
Software Libraries, available for both Windows and Linux platforms, are described in § 5.
Future firmware upgrade is possible via USB; only tools developed by CAEN must be
used for the firmware upgrade.
N957 CONTROLLER
(ALTERA CYCLONE EP1C6)
CHANNEL
CONTROLLER
(MAX7032S)
ANALOG FRONT-END
(TRACK-HOLD/PULSE
STRETCHER)
USB
PERIPHERAL
CONTROLLER
ACQUISITION
MEMORY
(SRAM 64Kx16)
USB
CONV
PUR
BUSY
OUTP
ANALOG
IN
GATE
IN
Fig. 1.1: Mod. N957 Block Diagram

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 7
2. Technical specifications
2.1 Packaging
The Model N957 is housed in a single width NIM module.
2.2 Power requirements
Table 2.1: Power requirements
+12 V 220 mA
-12 V 220 mA
+6 V 600 mA
-6 V 50 mA

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 8
2.3 Front and back panel
Mod.
N957
8K
MCA
BUSY
CONV
PUR
OUTP
LINK
IN
GATE
LINK ON
TX/RX
Fig. 2.1: Mod. N957 Front panel

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 9
2.4 Input/Output connections
IN: Type: Input
Function: Unipolar (positive) or bipolar in a range from 0 to +10 V,
with a rise time greater than 0.1 µs, high impedance. BNC connector
(to be connected to Amplifier Analog output); negative inputs are
neglected.
GATE: Type: Input
Function: Temporal window for peak detection (in External Gate
mode); Signal must occur prior to and must extend for at least 0.2-μs
after the peak; NIM/TTL (automatically recognised) signal, high
impedance. BNC connector.
BUSY: Type: Output
Function: Provides NIM/TTL (switch selected, see § 2.6.1) standard
logic level signal to indicate a conversion;. Rise Time 3.5 ns. Fall
Time 3.5 ns. LEMO connector.
CONV: Type: Input
Function: Accepts NIM/TTL (switch selected, see § 2.6.1) signal; it is
an external conversion inhibit (active high), actually it disables the on
going conversions. Input impedance: 50 Ohm; LEMO connector.
PUR: Type: Input
Function: Pile-up rejection input; accepts NIM/TTL (switch selected,
see § 2.6.1) signal; signal must occur before the ADC Conversion
(see § 2.8.2). Input impedance: 50 Ohm; LEMO connector (to be
connected to Amplifier INHIBIT Output1).
OUTP: Type: Output
Function: Provides NIM/TTL (switch selected, see § 2.6.1) standard
logic level signal programmable via USB. (OUTP default signal:
BUFFER_FULL →data loss; it can be turned off by resetting the Full
status flag, see § 3.3).
LINK: B type USB connector; USB 2.0 compliant
2.5 Front panel displays
BUSY: red LED; light up during the ADC conversion
PUR, OUTP: green LEDs (1 per connector); light up as the relevant signal is active
CONV: green LED; light up if CONVERSION ENABLE bit (see § 3.3) is ON
and CONV input signal is not active.
LINK ON: green LED; lights up as USB port is powered
TX/RX: yellow LED; signals activity on USB port
1Amplifier INHIBIT Output provides a logic pulse when the internal pile-up rejection logic detects a distortion of the input
signal due to pile-up.

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 10
2.6 Internal hardware components
See Fig. 2.2 for their exact location on the PCB and their settings.
2.6.1 Switches
SW1 Type: DIP switch.
Function: it allows the selection between NIM and TTL I/O
signals (RIGHT: TTL; LEFT: NIM).
2.6.2 Firmware jumpers
J6 Type: Jumper.
Function: it allows to select whether the “Standard” or the
“Back up” firmware must be loaded at power on; (default
position: STD).
DAUGHTER BOARD
USB SECTION N957 FPGA
SW1 switch for
NIM/TTL logic
level selection
J6 jumper for
firmware
selection
Fig. 2.2: Mod. N957 PCB boardand component location

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 11
2.7 Technical specification table
Table 2.2: Mod. N957 Technical Features
No. of ADC channels 1
Input signals Unipolar (positive) or bipolar, 300 mV ÷ 10 V range,
rise time> 0.1 µs
Resolution 13 bit (8192 channels - 8064 valid if sliding scale enabled see 2.8)
ADC Conversion time 0.8 µs
Dead Time 4.8 µs
LSB 1.22 mV
Gate Signal must occur prior to and must extend for at least 0.2-μs after
the peak (in External Gate mode);
Maximum transfer rate 30 Mbyte/s (USB2.0); 75 Kbytes/s (USB1.1)
Differential Non-Linearity < 1% from 5% to 95% of input FSR (500 mV ÷ 9.5 V)
Integral Non-Linearity < 0.065% from 5% to 95% of input FSR (500 mV ÷ 9.5 V)
Gain Instability: <+150 ppm/°C
USB port
Compatible with USB 1.1 and USB 2.0
30Mbyte/s (USB 2.0 Bulk Transaction Protocol)
3m maximum cable length (longer distance can be achieved with
commercial off-the-shelf products)
I/O signals NIM/TTL; selected via internal switch SW1 on PCB (see Fig. 2.2)
Discriminator Threshold Software programmable, 0 mV ÷ 500 mV range, 100 steps
2.8 Analog to digital conversion
The input stage of the module is basically a linear stretcher which detects the input peak
value, while the gate is active, and keeps such value until the end of conversion.
Conversion can be triggered automatically (Auto Gate mode) or externally (External Gate
mode), depending on Control register setting (see § 3.3). In the first case a discriminator,
with a threshold settable via N957_SetLLD function, enables the conversion, which is
active as long as the input signal is above such threshold. In the second case, an
external gate is fed to the module, via front panel Gate In connector.
The output of the peak section is converted by a 13 bit Fast ADC. The ADC section
supports the sliding scale technique to reduce the differential non-linearity consists in
adding a known value to the analog level to be converted, thus spanning different ADC
conversion regions with the same analog value. The known level is then digitally
subtracted after the conversion and the final value is sent to the threshold comparator.
If the sliding scale is enabled, it reduces slightly the dynamic range of the ADC: the 13-bit
digital output is valid from 0 to 8063, while the values from 8064 to 8191 are not correct.

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 12
2.8.1 Analog to digital conversion timing
The signal conversion timing is shown in the following figures (Fig. 2.3, Fig. 2.4, Fig. 2.5
); the diagram includes five different logic states:
Idle
Track (acquiring data phase)
Settling (Settling time before ADC conversion)
Digitisation (ADC Conversion)
Clear (fast capacitor discharge in the peak section)
Idle state:
Auto Gate mode: the input signal after threshold starts the Track (acquiring data)
phase
External Gate mode: the occurrence of a GATE pulse starts the Track (acquiring
data) phase
Track (acquiring data ) state
Auto Gate mode: in the Track state the PEAK output increases according to the
input signal. When the first peak is detected starts the Settling phase (where the
peak value is held by means of a capacitor)
External Gate mode: in the Track state the PEAK output increases according to
the input signal until the highest peak within the GATE ON is reached. When the
GATE signal become inactive starts the Settling phase (where the peak value is
held by means of a capacitor)
Settling (Settling time before ADC conversion)
The peak value is held by means of a capacitor until the end of the digital conversion
(digitisation) The Settling state takes about 2 µs (settling time)
Digitisation state
During this phase the output of the PEAK section is converted by a 13 bit Fast ADC (the
phase takes 0.8 sec )
Clear state
After the digital conversion, the clear phase takes place by a fast capacitor discharge
(about 2 µs) which makes the conversion logic idle again.

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 13
Auto-Gate
(Internal)
Input
BUSY
Output
Conversion
Logic
State idle settling digitisa
tion clear idle
Threshold
track
2s0.8s2s
PEAK
section
Output
Peak detection
Fig. 2.3: Signal conversion timing Auto Gate mode (No Pileup)
Auto-Gate
(Internal)
PEAK
section
Output
Input
Busy
Output
Conversion
Logic
State
Threshold
idle settling digitisa
tion clear idle
track
2s0.8s2s
Peak detection
(first peak over threshold)
Fig. 2.4: Signal conversion timing Auto Gate mode (Trailing Edge Pileup)

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 14
GATE
PEAK section
Output
INPUT
BUSY
Output
Conversion
Logic
State idle settling digitisa
tion clear idle
track
2s0.8s2s
Peak detection
(absolute peak over threshold)
Fig. 2.5: Signal conversion timing External Gate mode
2.8.2 Pile Up Rejection
The PUR input signal prevents the ADC to store piled up events. It accepts NIM/TTL
(switch selected, see § 2.6.1) signal. To reject an event, the PUR signal must occur
before the conversion logic state Digitisation (before start of BUSY pulse) and must
overlap the BUSY output signal (see Fig. 2.6).
Auto-Gate
(Internal)
PEAK
section
Output
Input
Busy
Output
Conversion
Logic
State
Threshold
idle settling digitisa
tion clear idle
track
Peak detection
(first peak over threshold)
PUR
event
Rejected
Fig. 2.6: PUR timing for event rejection (Auto Gate mode)

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 15
2.9 Data readout
Converted peaks are stored into a 64 KSamples buffer memory, available for data
readout via built-in USB2.0 interface (also compatible with USB1.1). Data rate depends,
besides the connected PC capabilities, on the board setting via N957_ReadData
function, which allows to read a data block of programmable size; the larger the block
size, the faster the transfer rate.
The average transfer rate of the system can be evaluated in the following way:
Enable software conversion via N957_SetSwConvFlag function
Set the ADC sampling rate via N957_SetADCRate function
Readout data via N957_ReadData function
Acknowledge buffer occupancy via N957_GetBufferOccupancy function
During this procedure, the OUTP LED (in default setting) must not light up to signal that
buffer memory is full.
N957_ReadData function always returns the number of readout data; converted
waveforms are provided in the form of raw data, which have to be processed by the
User’s software tools.
0
200
400
600
800
1000
1200
1400
0 5000 10000 15000 20000 25000 30000 35000
Data Block size (Samples)
read_data parameter of N957_ReadData()
Max Data Rate (KS/s) with USB2.0
Fig. 2.7: Max Data Rate Vs. Data Block Size setting

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 16
2.10 Scaler and Timers
The board houses one 32 bit scaler and two 32 bit timers (named Timer and Livetime).
2.10.1Scaler description
Scaler counts the ADC conversion.
The Scaler is controlled by the bit 0 of the Control Register:
-Control Register <0> = 0: Scaler status: stop
-Control Register <0> = 1: Scaler status: count
The Scaler is cleared by the following operation:
-Dummy write access Software Clear register
-Dummy write access Software Reset register
Scaler read operation description:
1. Dummy write access Timer Low register: this operation freeze the value of
Scaler L/H registers
2. Read the Scaler Low register: Scaler<15..0>
3. Read the Scaler High register: Scaler<31..16>
2.10.2Timers description
Timer and Livetime input clock: 1 KHz
Timer is controlled by the bit 0 of the Control Register:
-Control Register <0> = 0: Timer status: stop
-Control Register <0> = 1: Timer status: count
Livetime is controlled by the bit 0 and 6 of the Control Register:
-Control Register <0> = 0: Livetime status: stop
-Control Register <0> = 1: Livetime status: enabled count
in Auto Gate mode (see Fig. 2.8):
-Idle and Track status: count (if board is not full)
-Settling, Digitisation and Clear status: stop
in External Gate mode (see Fig. 2.9):
-Track and Settling status: count (if board is not full)
-Idle, Digitisation and Clear status: stop

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 17
Auto-Gate
(Internal)
Input
BUSY
Output
Conversion
Logic
State idle settling digitisa
tion clear idle
Threshold
track
PEAK
section
Output
Peak detection
Livetime
status STOP COUNT
COUNT COUNT
Fig. 2.8: Livetime status (Control Register <0> = 1 and Auto Gate mode)
GATE
PEAK section
Output
INPUT
BUSY
Output
Conversion
Logic
State idle settling digitisa
tion clear idle
track
Peak detection
(absolute peak over threshold)
Livetime
status STOP
STOP COUNT
Fig. 2.9: Livetime status (Control Register <0> = 1 and External Gate mode)

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 18
Timer and Livetime are cleared by the following operation:
-Dummy write access Software Clear register
-Dummy write access Software Reset register
Timer and Livetime read operation description:
1. Dummy write access Timer Low register: this operation freeze the value of
Timer and Livetime L/H registers
2. Read the Timer Low register: Timer<15..0>
3. Read the Timer High register: Timer<31..16>
4. Read the Livetime Low register: Livetime <15..0>
5. Read the Livetime High register: Livetime <31..16>
2.11 Firmware upgrade
The board can store two firmware versions, called STD and BKP respectively; at Power
On, a microcontroller reads the Flash Memory and programs the module with the
firmware version selected via the J6 jumper (see § 2.6.2), which can be placed either on
the STD position, or in the BKP position. It is possible to upgrade the board firmware via
USB, by writing the Flash: for this purpose, download the firmware package available at:
http://www.caen.it/csite/CaenProd.jsp?parent=12&idmod=466.
The package includes the new firmware release file:
N957CTL_revXY.rbf
For upgrading the firmware, utilize the upgrade program situated in the folder described
in paragraph in § 4.1.1.5; open a DOS Shell, then launch:
N957Upgrade -Ifilename (filename= upgrade input file).
N.B.: it is strongly suggested to upgrade ONLY one of the stored firmware
revisions (generally the STD one): if both revision are simultaneously updated, and
a failure occurs, it will not be possible to upload the firmware via VME again!
2.11.1N957Upgrade command parameters
N957Upgrade can be configured via command line through a set of parameters,
described in the following.
The parameters format is as follows:
-param_id[param_value]
where:
param_id: a character which identifies the parameter.
param_value: value of the parameter, if foreseen by the parameter itself.

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 19
Notes about the parameters usage:
If one parameter is not assigned, default value is assumed.
The presentation order of the parameter is arbitrary:
Each not recognised parameter is ignored
Each parameter must be separated from the others via one or more
spaces.
List of available parameters with relevant default value and usage example:
params_list:
-ifilename | -Ifilename
filename= upgrade input file. If not specified 'N957.rbf' will be assumed.
example: N957Upgrade -i"N957_new.rbf"
N957Upgrade -Iupgrade.dat
-s | -S upgrade standard flash page. Default flash page value is 'standard'.
example: N957Upgrade -s
-b | -B upgrade backup flash page. Default flash page value is 'standard'.
example: N957Upgrade -b
-h | -H show the help screen
example: N957Upgrade -h

Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. N957 8k Multi-Channel Analyzer 28/05/2012 6
NPO: Filename: Number of pages: Page:
00105/04:N957x.MUTx/06 N957_REV6 35 20
3. Software interface
The module can be operated via a set of software accessible registers, whose
description is reported in the subsequent sections.
3.1 Register map
REGISTER NAME ADDRESS MODE FUNCTION
STATUS 0x00 R Status register
CONTROL 0x01 R/W Control register
FWREV 0x02 R FPGA firmware revision
FWDWLND 0x03 R/W R/W configuration rom data
FLENA 0x04 R/W Flash enable
PULSER 0x05 R/W SW pulse duration
DAC 0x06 R/W DAC value setting
BLDIM 0x07 R/W Data transfer block size
POTCTRL 0x08 R/W Digital pot control register
CAL_SET 0x09 W Digital pot bit set register
CAL_CLEAR 0x0A W Digital pot bit clear register
SCRATCH 0x0B R/W Scratch
BUFFER OCCUPANCY 0x0C R Buffer occupancy
SCALER_L 0x0D R Scaler (16 LSB)
SCALER_H 0x0E R Scaler (16 MSB)
TIMER_L 0x0F R/W Timer (16 LSB)
TIMER_H 0x10 R Timer (16 MSB)
LIVETIME_L 0x11 R Live Timer (16 LSB)
LIVETIME_H 0x12 R Live Timer (16 MSB)
SW CLEAR 0x13 W Software Clear
SW RESET 0x134 W Software Reset