Casio WK-1200 User manual

ELECTRONIC KEYBOARD
WK-1200
WK-1200
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REVERB GM
FREE
SESSION
LAYER
SPLIT
TOUCH
RESPONSE
MEMORY TRACK/DRUM PAD
HALL
STAGE
ROOM
SYNTH
MIXER
MEMORY
STEP
CHORD/1 2 3 4 5 6
REVERB
SYNTH
MIXER
MUSICAL INFORMATION SYSTEM
MEMORY
STEP
TEMPO ACCOMP VOLUME
S
Y
N
C
H
R
O
/
E
N
D
I
N
G
I
N
T
R
O
N
O
R
M
A
L
/
F
I
L
L
-
I
N
V
A
R
/
F
I
L
L
-
I
N
AMP ENVELOPE
000-048 DECAY
PITCH ENVELOPE
00 FLAT049-137 SUSTAIN 01-19 VIBRATO 20-49 OTHERS
MODE
POWER
VOLUME
100 RHYTHMS
FULL RANGE MAX
ENVELOPE
MIN
CHORD
FINGERED
CASIO CHORD
NORMAL
TRANSPOSE/
FREE SESSION
LAYER
SPLIT
TOUCH
RESPONSE
TUNE/MIDI
C
U
R
S
O
R
RHYTHM TONE
ENTER
200TONES
DEMO
TIE
REST
3

— 1 —
SPECIFICATIONS
GENERAL
Keyboard: 73 standard-size keys, 6 octaves (with touch response on/off)
Drum pads: 6
Tones: 200 (128 General MIDI, 32 synthesized, 8 drum, 32 user); with layer and
split
Rhythm instrument tones: 51
Polyphony: 24 notes maximum (12 for certain tones)
Digital effects: 3 reverb types (HALL, STAGE, ROOM)
Auto accompaniment
Rhythm patterns: 100
Tempo: Variable (216 steps, = 40 to 255)
Chords: 3 fingering methods (CASIO CHORD, FINGERED, FULL RANGE
CHORD)
Rhythm controller: START/STOP, INTRO, NORMAL /FILL-IN, VAR/FILL-IN, SYNCHRO/
ENDING
Accomp volume: 0 to 127 (128 steps)
Free session
Number of patterns 100 (auto-accompaniment in accordance with selected chord progres-
sion)
Memory function
Songs: 2
Recording tracks: 6 (2 through 6 are melody tracks)
Recording methods: Real-time, step
Memory capacity: Approximately 5,200 notes (total for two songs)
Edit function: Equipped
Demo tunes: 2
Synthesizer function
Parameters: PCM set, amp envelope set, attack rate, release rate, pitch envelope set,
pitch, level, touch sense, pan
Mixer function
Channels: 16
Parameters: Program change number, volume, expression, pan, coarse tuning, fine
tuning, on/off/solo
MIDI: 16 multi-timbre receive, GM Level 1 standard
Other functions
Pitch bend range: 12 semitones upwards and downwards
Transpose: 25 steps (–12 semitones to +12 semitones)
Tuning: Variable (A4 = approximately 440 Hz ±50 cents)
CONTENTS Page
Specifications............................................................................................................................................ 1
Block Diagram........................................................................................................................................... 3
Circuit Description..................................................................................................................................... 4
Adjustment .............................................................................................................................................. 12
Major Waveforms .................................................................................................................................... 13
Printed Circuit Boards ............................................................................................................................. 14
Schematic Diagrams ............................................................................................................................... 15
Exploded View ........................................................................................................................................ 21
Parts List ................................................................................................................................................. 23

— 2 —
ELECTRICAL
Current drain with 12 V DC:
No sound output 430 mA ±20 %
Maximum volume 1570 mA ±20 %
with 24 keys from C4 to C6 pressed in Bassoon tone
Volume: maximum, Touch response: maximum
Reverb: Hall
Phone output level (Vrms with 8 Ωload each channel):
with key A5 pressed in Bassoon tone L-ch 165 mV ±20 %
Volume: maximum R-ch 150 mV ±20 %
Reverb: Hall
Speaker output level (Vrms with 4 Ωload each channel):
with key A5 pressed in Bassoon tone L-ch 5500 mV ±20 %
Volume: maximum R-ch 5200 mV ±20 %
Reverb: Hall
Output level (Vrms with 47 kΩload each channel):
with key A5 pressed in Bassoon tone L-ch 4260 mV ±20%
R-ch 3950 mV ±20%
Minimum operating voltage: 6.3 V
About General MIDI
General MIDI standardizes MIDI data for all sound source types, regardless of manufacturer. General MIDI
specifies such factors as tone numbering, drum sounds, and available MIDI channels for all sound sources.
This standard makes it possible for all MIDI equipment to reproduce the same nuances when playing
General MIDI data, regardless of the manufacturer of the sound source.
This keyboard supports General MIDI, so it can be used to play commercially available pre-recorded
General MIDI data and General MIDI data send to it from a personal computer.
Terminals
MIDI terminals: IN, OUT
Assignable terminal: Standard jack (sustain, sostenuto, soft, rhythm start/stop)
Headphone/Output terminal: Stereo standard jack
Output Impedance: 200 Ω
Output Voltage: 4.9 V (RMS) MAX
Power supply terminal: 12 V DC
Power supply Dual power supply system
Batteries: Six D-size batteries
Battery life: Approximately 2 hours (UM-1/R20) 8 hours (AM-1/LR20)
AC adaptor: AD-12
Auto power off: Turns power off approximately six minutes after last key operation. En-
abled under battery power only, can be disabled manually.
Power consumption: 12 V --- 18 W
Speaker output: 5 W + 5 W
Dimensions (HWD): 116.2 ×42.1 ×14.7 cm (45-13/16 ×16-9/16 ×5-13/16 inches)
Weight: Approximately 9.1 kg (20.1 lbs) (without batteries)

— 3 —
BLOCK DIAGRAM
KC0 ~ KC7
FI0 ~ FI9
SI0 ~ SI9
KI0 ~ KI2
PB0 ~ PB3
P10, P13
P14, P17
Working Storage
RAM (256K-bit)
LSI4
TC55257DFL-70L(EL)
MIDI
EA0 ~
EA14
EIO0 ~
EIO7
Sound Source ROM
(16M-bit)
LSI3
MX23C1610MC-
12CA64
LRCK
SO
BCK
D/A Converter
IC1
UPD6379GR
Filter
Q308 ~ Q311
Main
Volume
Power Amplifier
IC301
LA4620
Keyboard
MA0 ~ MA19
Power Supply Circuit
Q301 ~ Q304, 306, 307
D307, 310
VCC AVDD VDD
CVDDLVDD VC
APO
Effect RAM
(256K-bit)
LSI5
TC55257DFL-
70L(EL)
MD0
~
MD7
Speakers
Output
MA0
~
MA14
MA0, MA1 LRCK, SO
BCK, SINK
LCD
LCD Driver
LSI501
SED1278F0A
SEG1 ~ SEG40
INOUT
Reset IC
IC2
RN5VD40AA
RESET
COM1 ~ COM16
DSP
LSI2
HG51B277FB-1
MD0 ~ MD15 CPU
LSI1
GT-913F
Buttons
Assingnable Jack
PB4
VDD Power Switch
NMI
FI10
P23
PA0 ~ PA5
PB0 ~ PB3

— 4 —
CIRCUIT DESCRIPTION
KEY MATRIX
Note: Each key has two contacts,
the first conatct (1) and second contact (2).
Key
Second contact (2) First contact (1) KC
SI
FI
0CK1CK2CK3CK4CK5CK6CK7CK
0IF)1(1C)1(1#C)1(1D)1(1#D)1(1E)1(1F)1(1#F)1(1G
0IS)2(1C)2(1#C)2(1D)2(1#D)2(1E)2(1F)2(1#F)2(1G
1IF)1(1#G)1(1A)1(1#A)1(1B)1(2C)1(2#C)1(2D)1(2#D
1IS)2(1#G)2(1A)2(1#A)2(1B)2(2C)2(2#C)2(2D)2(2#D
2IF)1(2E)1(2F)1(2#F)1(2G)1(2#G)1(2A)1(2#A)1(2B
2IS)2(2E)2(2F)2(2#F)2(2G)2(2#G)2(2A)2(2#A)2(2B
3IF)1(3C)1(3#C)1(3D)1(3#D)1(3E)1(3F)1(3#F)1(3G
3IS)2(3C)2(3#C)2(3D)2(3#D)2(3E)2(3F)2(3#F)2(3G
4IF)1(3#G)1(3A)1(3#A)1(3B)1(4C)1(4#C)1(4D)1(4#D
4IS)2(3#G)2(3A)2(3#A)2(3B)2(4C)2(4#C)2(4D)2(4#D
5IF)1(4E)1(4F)1(4#F)1(4G)1(4#G)1(4A)1(4#A)1(4B
5IS)2(4E)2(4F)2(4#F)2(4G)2(4#G)2(4A)2(4#A)2(4B
6IF)1(5C)1(5#C)1(5D)1(5#D)1(5E)1(5F)1(5#F)1(5G
6IS)2(5C)2(5#C)2(5D)2(5#D)2(5E)2(5F)2(5#F)2(5G
7IF)1(5#G)1(5A)1(5#A)1(5B)1(6C)1(6#C)1(6D)1(6#D
7IS)2(5#G)2(5A)2(5#A)2(5B)2(6C)2(6#C)2(6D)2(6#D
8IF)1(6E)1(6F)1(6#F)1(6G)1(6#G)1(6A)1(6#A)1(6B
8IS)2(6E)2(6F)2(6#F)2(6G)2(6#G)2(6A)2(6#A)2(6B
9IF)1(7C
9IS)2(7C
NOMENCLATURE OF KEYS
C2
C#2 D#2 F#2 G#2 A#2 C#3 D#3 F#3 G#3 A#3 C#4 D#4 F#4 G#4 A#4 C#5 D#5 F#5 G#5 A#5 C#6 D#6 F#6 G#6 A#6
D2 E2 F2 G2 A2 B2C1 D1 E1 F1 G1 A1 B1 C3 D3 E3 F3 G3 A3 B3
C#1 D#1 F#1 G#1 A#1
C4 D4 E4 F4 G4 A4 B4 C5 D5 E5 F5 G5 A5 B5 D6 E6 F6 G6 A6 B6C6 C7

— 5 —
PA0 PA1 PA2 PA3
PB0 FULL RANGE INTRO TOUCH REVERB
CHORD RESPONSE
PB1 FINGERED NORMAL/ FREE ACCOMP
FILL-IN SESSION VOLUME
PB2 CASIO SYNCHRO/ LAYER SYNTH
CHORD ENDING
PB3 NORMAL VARIATION/ SPILIT MIXER
FILL-IN
KC0 KC1 KC2 KC3 KC4 KC5 KC6 KC7
DRUM DRUM PITCH H
FI10 PAD 3 PAD 1 BEND ENTER 9 6 + TONE
CHORD 3 CHORD 1 H
DRUM DRUM PITCH G START/
KI0 PAD 4 PAD 2 BEND STOP 8 3 — RHYTHM
CHORD 4 CHORD 2 G
DRUM TEMPO
KI1 PAD 5 STEP HE7 2 0 DEMO
CHORD 5
DRUM TEMPOG TRANSPOSE/
KI2 PAD 6 MEMORY GF451
CHORD 6 TUNE/MIDI
POWER SUPPLY CIRCUIT
The power supply circuit generates five voltages as shown in the following table. VDD and VC voltages
are always generated. The others are controlled by APO signal from the CPU.
BUTTON MATRIX
Name Voltage For operation of
VDD +5 V CPU, Reset IC, DSP, Sound source ROM, Working storage RAM, Effect RAM
AVDD +5 V DAC, Filter
LVDD +5.6 V LCD driver
VCC,VC +9 V Power amplifier, Pilot lamp
CVDD +5 V Power jack, Pedal jack, MIDI jacks, Source voltage for LCD backlight

— 6 —
RESET CIRCUIT
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU. The
CPU then initializes its internal circuit, and clears the working storage RAM.
When the power switch is pressed, the CPU receives a low pulse of POWER signal. The CPU sends APO
signal to the power supply circuit, also sends a reset signal to the DSP.
LCD BACKLIGHT
When voltage CVDD is supplied, transistors Q501 and 502 start oscillation.
From the oscillation voltage, transformer T501 generates about 600 V which is necessary for lighting the
backlight.
Reset IC
IC2
RN5VD40AA
DSP
LSI2
HG51B277FB-1
VDD
Reset signal
To power supply circuit
VDD Battery set
RESET
VDD
POWER
From power switch NMI
APO
PLE
CPU
LSI1
GT-913F
SCKO
10 1
11
C502
(Bottom View)
NT-07
T501
CFL1
L501
LHL08TB101K
1
1
12
DG
CVDD
C104FA
C104M
2SD965R 2SD965R
C501
R501
4.7K
Q501
CP14
Q502
C516
1
12
23 32
2
HMBV26BG1W63N/AZ
DE0405-979SL180J2K
2
12
2
3
4
5
8
9
7
5

— 7 —
CPU (LSI1: GT-913F)
The 16-bit CPU contains a 1k-byte RAM, three 8-bit I/O ports, two timers, a key controller and serial interfaces.
The CPU detects key velocity by counting the time between first-key input signal FI and second-key SI from
the keyboard. The CPU reads sound data and velocity data from the sound source ROM in accordance with
the selected tone; the CPU can read rhythm data simultaneously when a rhythm pattern is selected. Then the
CPU provides 16-bit serial sound data to the DSP. The CPU also controls MIDI input/output and stores
sequencer data into the working storage RAM.
The following table shows the pin functions of LSI1.
.oNniPlanimreTtuO/nInoitcnuF
10DXTtuOtuptuolangisIDIM
20DXRnItupnilangisIDIM
30KCStuOtuptuolangis)ffOrewoPotuA(OPA
5,4
,31P/DXT
41P/DXR
tuO/nIrevirdDCLehtrofsubataD
61KCStuOtuptuoeslupgnizinorhcnysZHM1
7CCVAnIecruos)V5+(DDVC
80NAnI .lanimretnoitcetedrotpadaCA V0semocebdnaseirettabybderewopsidraobyekehtnehwV5+ .detcennocsirotpadaCAnehwnoitcnufOPAehtlecnacot
91NAnIrednebhctipmorftupnI
01DNGAnIecruos)V0(dnuorG
11KCBtuOtuptuokcolctiB
21OStuOtuptuoataddnuoslaireS
31KCRLtuOtuptuokcolcdroW
41DNGnIecruos)V0(dnuorG
61,511TLX,0TLXtuO/nItuptuo/tupnikcolczHM03
71CCVnIecruosV5+
91,811DOM,0DOMnIlanimretnoitcelesedoM
02BTSRnItupnilangisteseR
12IMNnItupnilangisNOrewoP
2201P/TNItuO/nIrevirdDCLehtrofsubataD
03~32
3IF~0IF
3IS~0IS
nIlangistupniyekroflanimreT
83~137CK~0CKtuOlangisnacsyekroflanimreT
05~93
9IF~4IF
9IS~4IS
nIlangistupniyekroflanimreT
1501IFnIlangistupninottubroflanimreT
2532P/01IStuOrevirdDCLehtroflangiselbanepihC
55~352IK~0IKnIlangistupninottubroflanimreT
65BNWMtuOPSDehtroflangiselbaneetirW
67~7591AM~0AMtuOsubsserddA
770BSCMtuOMORecruosdnuosehtroftuptuolangiselbanepihC
871BSCMtuOdesutoN
972BSCMtuOPSDehtroftuptuolangiselbanepihC

— 8 —
.oNniPlanimreTtuO/nI noitcnuF
08,3~13BP~0BPnIslanimrettupninottuB
44BPnItupnikcaJELBANGISSA
5OStuOCADehtroftuptuoataddnuoslaireS
6OKCWtuOCADehtroftuptuokcolcdroW
73DDVnIecruosV5+
8TSET—desutoN
9BSERnItupnilangisteseR
012SSVnIecruos)V0(dnuorG
21,11TUOX,NIXtuO/nItuptuo/tupnikcolczHM02
31IKCWnIUPCehtmorftupnikcolcdroW
41ISnIUPCehtmorftupniataddnuoslaireS
51IKCBnIUPCehtmorftupnikcolctiB
61CNISnItupnieslupgnizinorhcnyszHM1
712DDVnIecruosV5+
52~817OI~0OItuO/nIsubataD
62BECRtuOMARegarotsgnikrowehtroftuptuolangiselbanepihC
723SSVnIecruos)V0(dnuorG
821DAnIsubsserddA
92BEDnIMARegarotsgnikrowroflangiselbaneataD
03BEWnIlangiselbaneetirW
133DDVnIecruosV5+
232ECnI.evitcahgiH.tupnilangiselbanepihC
330DAnIsubsserddA
43B1ECnI.evitcawoL.tupnilangiselbanepihC
34,14~537OIE~0OIEtuO/nIMARtceffeehtrofsubataD
,84~64,44,24
16,95~15
41AE~0AEtuOMARtceffeehtrofsubsserddA
54BECEtuOMARtceffeehtroftuptuolangiselbanepihC
DIGITAL SIGNAL PROCESSOR (LSI2: HG51B227FB-1)
The DSP receives 16-bit serial sound data output from the CPU and adds the selected effect to the sound data
using the effect RAM. Then the DSP provides the sound data to the DAC. The DSP also controls button input/
output.
The following table shows the pin functions of LSI2.
.oNniPlanimreTtuO/nInoitcnuF
08CCVnIecruosV5+
18DNGnIecruos)V0(dnuorG
28BDRMtuOMORecruosdnuosehtroftuptuolangiselbanedaeR
89~3851DM~0DMtuO/nIsubataD
99ELPtuOPSDehtroftuptuolangisteseR
00171PtuO/nIrevirdDCLehtrofsubataD

— 9 —
Pin No. Terminal In/Out Function
49 EOEB Out Read enable signal output for the effect RAM
50 VSS3 In Ground (0 V) source
60 BWEB Out Write enable signal output for the effect RAM
62, 66, 70, 74, 78 VSS2 In Ground source
63, 67, 71, 75, 79 VDD2 In +5 V source
64, 65, 68, 69, PA0 ~ PA5 Out Button scan signal output
72, 73
76, 77 PA6/7 Out Not used
LCD DRIVER (LSI501 : SED1278F0A)
The LCD driver can drive a dot matrix LCD having 40 segment and 16 common lines. The LSI contains 240
graphic symbols in the built-in character generator ROM, and stores 80 characters in the built-in display data
RAM. In accordance with command from the CPU, the LSI is capable of displaying up to 16 characters
simultaneously. The following table shows the pin functions of LSI 501.
Pin No. Terminal In/Out Function
1 ~ 22, SEG1 ~ SEG40 Out Segment signal output
63 ~ 80
23 VSS — GND (0 V) source
24, 25 OSC1, OSC2 In/Out Terminals for the built-in clock pulse generator. The external
resistor connected determines the oscillation frequency.
26 ~ 30 V1 ~ V5 In LCD drive voltage input.
Those voltages are used forgenerating the stepped pulse of
the LCD drive signals.
31, 32 LP, XSCL — Not used
33 VDD In LVDD (+5 V) source
34, 35 FR, DO — Not used
36 RS In Data/command determination terminal.High: data, Low:
command
37 R/W In Read/write terminal. High: read, Low: write
38 E In Chip enable signal.
High: enable, the writing is done at fall edge.
Low: disenable
39 ~ 42 DB0 ~ DB3 — Not used. Connected to GND (0 V)
43 ~ 46 DB4 ~ DB7 In/Out Data bus
47 ~ 62 COM1 ~ COM16 Out Common signal/output

— 10 —
FILTER BLOCK
Since the sound signals from the DAC are stepped waveforms, the filter block is added to smooth the
waveforms.
DAC (IC1: UPD6379GR)
The DAC receives 16-bit serial data output from the DSP. The data contains digital sound data of the
melody, chord, bass, and percussion for the right and left channels. The DAC converts the data into
analog waveforms and output them to each channel separately.
Synch signal
Data
Word clock
Bit clock
Data
Word clock
Bit clock
DSP
LSI2
HG51B277FB-1
DAC
IC1
UPD6379GR
CPU
LSI1
GT-913F
L OUT
R OUT
SI
LRCK
CLK
SO
WCKO
SCK1
SO
LRCK
BCK
SINC
SI
WCKI
BCKI
AVDD
AVDD
2.2 K
AG AG
AG
AG
AG AG
1 K
Q308 Q310
1 K 1 K
2700 PF
6.3 V220 µ
25C1740SS-TP-T
25C1740SS-TP-T
5600 PF
1 K
AG
3.9 K
10 K
10 K
6.3 V100 µ
22 µF
0.015 µF
10 V22 µFrom DAC
To main volume

— 11 —
POWER AMPLIFIER (IC301: LA4620)
The power amplifier is a two-channel amplifier with standby switch.
6
16 2 10 11 13
12
Pre-drive
Amp.
Input
Amp. Power Amp.
+
–
Pre-drive
Amp.
Input
Amp. Power Amp.
+
–
9
7
3
5
+
–
Input
Amp. Pre-drive Amp. Power Amp.
+
–
Input
Amp. Pre-drive Amp. Power Amp.
4
19
20
21
22
23
1
18
17
15
14
8
RL Short
Protector
RL Short
Protector
Terminal
Protection
Circuit
Pop Noise
Prevention
Circuit
Ripple
Filter
IN11+
IN11–
IN12–
IN21+
IN21–
IN22–
NC DC MUTE ADJ
Boot11
OUT11
PoGND1
OUT12
Boot12
VCC1
Boot21
OUT21
PoGND2
OUT22
Boot22
VCC2
PriGND

— 12 —
3) Equipment connection/Procedure
Vop voltage setting
Output
Set Voltmeter
TP2
Input
Connection Input Point Input Signal Adjust Output Connection Output Point Adjust for
VR501 Voltmeter TP2 Adjust for 4.4 ±0.1 V reading
on voltmeter.
Makefineadjustmentaccord-
ing to the next instruction.
Watching the LCD at a 37.40°angle to the horizontal, adjust Vop
voltage so that unenergized segments are seen dimly.
ADJUSTMENT
DISPLAY PCB
1) Items to be adjusted:
2) Adjustment and Test Point Locations
(BOTTOM VIEW)
37.40°
LCD
Eye
metItnemurtsnIgnirusaeM
gnittesegatlovpoVretemtloV
TP2 (top side)
VR501

— 13 —
MAJOR WAVEFORMS
1Clock signal SINK
Test point T5 2Clock signal FB1 Test point T3
3Clock signal FB2
Test point T4
5Key common signal KC0
JC connector pin 3
6Key common signal KC1
JC connentor pin 4
7Sound signal (LMEL)
Test point T2
8Sound signal (RMEL)
Test point T1
9Sound signal (LIN)
JK connector pin 1
0Sound signal (RIN)
JK connector pin 2
1
2
34
5
6
7
8
9
0
4APO signal
JH connector pin 4
Power ON Power OFF
Tone: Bassoon, Volume: Maximum
Touch speed: Maximum, Reverb: Hall
Key: A4

— 14 —
PRINTED CIRCUIT BOARDS
Main PCB JCM730-MA1M Sub PCB JCM730-MA2M
Top View
Bottom View
5
6
3 2 7 8 14
910

— 15 —
SCHEMATIC DIAGRAMS
Main PCB JCM730-MA1M
87
2 3
1
4
65

— 16 —
Sub PCB JCM730-MA2M
10 9

— 17 —
Console PCBs JCM730-CN1M/CN2M/CN3M/CN4M

— 18 —
LCD Driver PCB JCM730-LCD1M

— 19 —
Keyboard PCBs JCM731T-KY1M/KY2M/KY3M