GR-VPX-GR740-BOARD
List of Figures
Figure 3-1: GR-VPX-GR740 Development Board mounted with GR-VPX-SPW-MEZZ mezzanine
board...................................................................................................................................................10
Figure 3-2: GR-VPX-GR740 Main Board without mezzanine board................................................12
Figure 4-1: GR-VPX-GR740 Board Board Block Diagram..............................................................14
Figure 4-2: GR-VPX-SPW-MEZZ Mezzanine Board Block Diagram..............................................15
Figure 4-3: VPX Style mechanical keying.........................................................................................16
Figure 4-4: Mezzanine board mounted on a GR-VPX-GR740 main board.......................................17
Figure 4-5: On-Board Spacewire Connections...................................................................................1
Figure 4-6: PPS input circuitry..........................................................................................................21
Figure 4-7: Configuration option for switch S23 and S24.................................................................27
Figure 4-8: Configuration option for switch S27 to S41....................................................................27
Figure 4- : Debug Support Unit connections.....................................................................................28
Figure 4-10: Board level Clock Distribution Scheme – GR-VPX-GR740........................................30
Figure 4-11: Power Regulation Scheme – GR-VPX-GR740.............................................................31
Figure 5-1: SW-SP3T configuration options and schematics.............................................................34
Figure 5-2: SW-SP3T mapping between schematics and a switch onboard......................................34
Figure 5-3: Configuration options for switch S1 to S22....................................................................35
Figure 5-4: GR740SBC Bootstrap Signals default configuration......................................................36
Figure 6-1: Front Panel View (pins 1 marked red).............................................................................3
Figure 6-2: GR-VPX-GR740 PCB Top View....................................................................................4
Figure 6-3: GR-VPX-GR740 PCB Bottom View...............................................................................50
List of Tables
Table 1: GR740 SpW Router Port mapping to Front panel interfaces...............................................1
Table 2: GR740 SpW Router Port mapping to Backplane interfaces.................................................1
Table 3: Functions assigned to GPIO signals of GR740....................................................................25
Table 4: Functions assigned to GPIO2 signals of GR740..................................................................26
Table 5: GR740 Bootstrap Settings....................................................................................................36
Table 6: GR740 GPIO Bootstrap Settings..........................................................................................37
Table 7: Other configurable switches default settings........................................................................37
Table 8: Default Setting of Jumpers – GR-VPX-GR740...................................................................38
Table : List of Connectors – GR-VPX-GR740.................................................................................40
Table 10: List of Connectors – GR-VPX-SPW-MEZZ......................................................................40
Table 11: J1 POWER – External Power Connector...........................................................................41
Table 12: J2 Dual MIL-STD-1553 interface connections..................................................................41
Table 13: J3 RJ45-ETHERNET Connector........................................................................................41
Table 14: J4 PPS Input........................................................................................................................41
GR-VPX-GR740-BOARD-UM, Nov 2020, Version 1.4 5
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