COBHAM GR-VPX-GR740-BOARD User manual

GR-VPX-GR740-BOARD
Development Board
2020 User's Manual
he most important thing we build is trust
GR-VPX-GR740-BOARD
Development Board
User's Manual
GR-VPX-GR740-BOARD-UM, 2020, Version 1.4 www.cobham.com/gaisler

GR-VPX-GR740-BOARD
Intentionally Blank
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GR-VPX-GR740-BOARD
Table of Contents
1 Introduction......................................................................................................................7
1.1 Scope of the Document.......................................................................................7
1.2 Reference Documents..........................................................................................7
2 Abbreviations...................................................................................................................8
3 Board Introduction..........................................................................................................9
3.1 Overview.............................................................................................................
3.2 Handling............................................................................................................13
4 Board Design..................................................................................................................14
4.1 Board Block Diagram........................................................................................14
4.2 Board Mechanical Format.................................................................................15
4.3 GR740 Microcontroller.....................................................................................18
4.4 Memory.............................................................................................................18
4.5 Main Board Interfaces.......................................................................................18
4.5.1 SPW Interfaces..................................................................................................18
4.5.1.1 SPW connector implementation details and precautions to follow...................20
4.5.2 Ethernet..............................................................................................................20
4.5.3 MIL-1553..........................................................................................................20
4.5.4 PPS....................................................................................................................21
4.5.5 FTDI (USB Serial)............................................................................................21
4.5.6 VPX Backplane.................................................................................................21
4.6 Mezzanine Interfaces.........................................................................................22
4.7 GPIO..................................................................................................................24
4.8 Debug Support Unit Interfaces..........................................................................28
4. Oscillators and Clock Inputs.............................................................................2
4.10 Power Supply and Voltage Regulation..............................................................31
Setting Up and Using the Board...................................................................................33
5.1 Switches and Bootstrap Signals.........................................................................33
5.1.1 SP3T Switch description and configuration properties.....................................34
5.1.2 GR740 Bootstrap Signals..................................................................................35
5.1.3 Other configurable switches default settings.....................................................37
5.2 Jumper configurations.......................................................................................37
5.2.1 Default Setting of Jumpers – GR-VPX-GR740................................................38
6 Interfaces and Configuration.......................................................................................39
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6.1 List of Connectors – GR-VPX-GR740..............................................................40
6.2 List of Connectors – GR-VPX-SPW-MEZZ.....................................................40
6.3 List of Oscillators, Switches and LED's - GR-VPX-GR740.............................47
7 Change Record............................................................................................................... 2
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List of Figures
Figure 3-1: GR-VPX-GR740 Development Board mounted with GR-VPX-SPW-MEZZ mezzanine
board...................................................................................................................................................10
Figure 3-2: GR-VPX-GR740 Main Board without mezzanine board................................................12
Figure 4-1: GR-VPX-GR740 Board Board Block Diagram..............................................................14
Figure 4-2: GR-VPX-SPW-MEZZ Mezzanine Board Block Diagram..............................................15
Figure 4-3: VPX Style mechanical keying.........................................................................................16
Figure 4-4: Mezzanine board mounted on a GR-VPX-GR740 main board.......................................17
Figure 4-5: On-Board Spacewire Connections...................................................................................1
Figure 4-6: PPS input circuitry..........................................................................................................21
Figure 4-7: Configuration option for switch S23 and S24.................................................................27
Figure 4-8: Configuration option for switch S27 to S41....................................................................27
Figure 4- : Debug Support Unit connections.....................................................................................28
Figure 4-10: Board level Clock Distribution Scheme – GR-VPX-GR740........................................30
Figure 4-11: Power Regulation Scheme – GR-VPX-GR740.............................................................31
Figure 5-1: SW-SP3T configuration options and schematics.............................................................34
Figure 5-2: SW-SP3T mapping between schematics and a switch onboard......................................34
Figure 5-3: Configuration options for switch S1 to S22....................................................................35
Figure 5-4: GR740SBC Bootstrap Signals default configuration......................................................36
Figure 6-1: Front Panel View (pins 1 marked red).............................................................................3
Figure 6-2: GR-VPX-GR740 PCB Top View....................................................................................4
Figure 6-3: GR-VPX-GR740 PCB Bottom View...............................................................................50
List of Tables
Table 1: GR740 SpW Router Port mapping to Front panel interfaces...............................................1
Table 2: GR740 SpW Router Port mapping to Backplane interfaces.................................................1
Table 3: Functions assigned to GPIO signals of GR740....................................................................25
Table 4: Functions assigned to GPIO2 signals of GR740..................................................................26
Table 5: GR740 Bootstrap Settings....................................................................................................36
Table 6: GR740 GPIO Bootstrap Settings..........................................................................................37
Table 7: Other configurable switches default settings........................................................................37
Table 8: Default Setting of Jumpers – GR-VPX-GR740...................................................................38
Table : List of Connectors – GR-VPX-GR740.................................................................................40
Table 10: List of Connectors – GR-VPX-SPW-MEZZ......................................................................40
Table 11: J1 POWER – External Power Connector...........................................................................41
Table 12: J2 Dual MIL-STD-1553 interface connections..................................................................41
Table 13: J3 RJ45-ETHERNET Connector........................................................................................41
Table 14: J4 PPS Input........................................................................................................................41
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GR-VPX-GR740-BOARD
Table 15: J5: Front Panel Input/Output pins.......................................................................................42
Table 16: J6: SDRAM SODIMM socket Pin-out...............................................................................44
Table 17: J7 GR740 – JTAG Connector.............................................................................................44
Table 18: J8 USB Micro connector – FTDI Quad Serial Link...........................................................44
Table 1 : J Mezzanine Connector – Female.....................................................................................45
Table 20: J10 SPW-HDR interface connections.................................................................................46
Table 21: J11 FPGA– JTAG Connector.............................................................................................46
Table 22: List and definition of Oscillators and Crystals...................................................................47
Table 23: List and definition of PCB mounted LED's........................................................................47
Table 24: List and definition of Switches...........................................................................................48
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GR-VPX-GR740-BOARD
1 Introduction
1.1 Scope of the Document
This document provides a User's Manual and Interface document for the “GR-VPX-
GR740-BOARD” Development and Demonstration board.
The work has been performed by Cobham Gaisler AB, Göteborg, Sweden.
1.2 Reference Documents
[RD1] GR740, “Data Sheet and User's Manual",Cobham Gaisler, GR740-UM-DS, available
from http://www.gaisler.com/index.php/products/components/GR740
[RD2] GRMON3 User's Manual, available from:
https://www.gaisler.com/index.p hp/products/debug-tools/grmon3
[RD3] GR-VPX-GR740 Board_schematic.pdf, Schematic
[RD4] GR-VPX-GR740 Board_assy_drawing.pdf, Assembly Drawing
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GR-VPX-GR740-BOARD
2 Abbreviations
ASIC Application Specific Integrated Circuit.
DSU Debug Support Unit
EDAC Error Detection and Correction
EDCL Ethernet Debug Communication Link
ESD Electro-Static Discharge
GPIO General Purpose Input / Output
IC Integrated Circuit
I/O Input/Output
IP Intellectual Property
LDO Low Drop-Out
LVDS Low Voltage Digital Signalling
PCB Printed Circuit Board
PCI Peripheral Component Interconnect
POL Point of Load
PPS Pulse Per Second
PROM Programmable Read Only Memory
SOC System On a Chip
SP3T Single Pole,3-throw (position) Switch
SPW SpaceWire
TBC To Be Confirmed
TBD To Be Defined
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GR-VPX-GR740-BOARD
3 Board Introduction
3.1 Overview
This document describes the GR-VPX-GR740 Development Board.
This equipment is a 1 slot, 6U high board with a VPX backplane format, consists of
•Main Board: GR-VPX-GR740
•Mezzanine Board: GR-VPX-SPW-MEZZ
The GR-VPX-GR740 board shown in Figure 3-1 integrated with a 6U front panel and a
mezzanine board, which can be used stand alone on the bench top, or installed in a VPX
rack.
A GR-VPX-SPW-MEZZ mezzanine board has been developed and integrated with the
GR-VPX-GR740, which provides two SpaceWire interface from the GR740 to the Front
panel.
This board provides developers with a convenient hardware platform for the evaluation
and development of software.
Note: The delivered product is GR-VPX-GR740 main board and GR-VPX-SPW-
MEZZ mezzanine board, the mezzanine board only provides two SpaceWire
interfaces in the front panel.
This user manual provides information about the GR-VPX-GR740 main boards
many different mezzanine interfaces through out the document, such descriptions
are provided in order to help the users to develop their own mezzanine board, for
example see section 4.6 Mezzanine Interfaces. However, the delivered GR-VPX-
SPW-MEZZ do not implement all such interfaces and only provides two
SpaceWire interfaces in the front panel.
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Figure 3-1: GR-VPX-GR740 Develo ment Board mounted with GR-VPX-SPW-MEZZ mezzanine board

GR-VPX-GR740-BOARD
The board contains the following main items as detailed in section 4 of this document:
Main Board
•size 233.35x160mm
•Cobham Gaisler GR740 radiation-hard system-on-chip featuring a quad-core
fault-tolerant LEON4 SPARC V8 processor
•1 Mbit (128k x 8bit) MRAM
•512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package)
•SODIMM socket for SDRAM memory (48 bit wide interface)
•Gbit Ethernet interface with standard RJ45 connector
•Dual MIL-1553 Interface
•1 PPS interface
•FTDI Serial to USB converter for JTAG and UART interface
•Front Panel General Purpose IO interface
•FMC style 400 pin mezzanine connector
•VPX Backplane interface
•VIN power input (+5V to +12V) via backplane or 2 pin header
•on-board regulators converting from VIN to 3.3V, 2.5V & 1.2V
•switches for bootstrap and configuration settings
Mezzanine Board
•GR-VPX-SPW-MEZZ
◦2 SpaceWire interfaces connected to the GR740 router (Port 1 and 2)
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Figure 3-2: GR-VPX-GR740 Main Board without mezzanine board

GR-VPX-GR740-BOARD
3.2 Handling
ATTENTION: OBSERVE PRECAUTIONS FOR
HANDLING ELECTROSTATIC SENSITIVE DEVICES
This unit contains sensitive electronic components which can be damaged by
Electrostatic Discharges (ESD). When handling or installing the unit observe
appropriate precautions and ESD safe practices.
When not in use, store the unit in an electrostatic protective container or bag.
When configuring the jumpers on the board, or connecting/disconnecting cables, ensure
that the unit is in an unpowered state.
When operating the board in a 'stand-alone' configuration, the power supply should be
current limited to prevent damage to the board or power supply in the event of an over-
current situation.
This board is intended for commercial use and evaluation in a standard laboratory
environment, nominally, 20°C. All devices are standard commercial types, intended for
use over the standard commercial operating temperature range (0 to 70ºC).
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GR-VPX-GR740-BOARD
4 Board Design
4.1 Board Block Diagram
The GR-VPX-GR740 Board provides the electrical functions and interfaces as represented
in the block diagram, Figure 4-1.
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Figure 4-1: GR-VPX-GR740 Board Board Block Diagram
GR740
PROCESSOR
GR740
PROCESSOR
GBIT
ETHERNET
GBIT
ETHERNET
PC100 SDRAM
PC100 SDRAM
MEZZANINE
CONNECTOR
MEZZANINE
CONNECTOR
VPX BACKPLANE
CONNECTORS
VPX BACKPLANE
CONNECTORS
JTAG
PROM - MRAM
PROM - MRAM
PROM - SPI
PROM - SPI
MIL155
INTERFACE
MIL155
INTERFACE
GENERAL
PURPOSE IO
GENERAL
PURPOSE IO
FTDI
(USB Serial)
FTDI
(USB Serial) UART x 2
PPS
PPS
SPW x 6
SPW x 2
SPW x10
PCI
(option)
SPW
HEADER
SPW
HEADER
POWER
CIRCUITS
POWER
CIRCUITS
RESET & AUX.
CIRCUITS
RESET & AUX.
CIRCUITS
POWER
RESET &
CLOCKS
FPIO
BPIO
SMBUS
REF-CLK's
MEZZANINE IO
FRONT PANEL
OSCILLATORS
OSCILLATORS

GR-VPX-GR740-BOARD
The Mezzanine connector of the GR-VPX-GR740 is a FMC High Pin Count (400 pin)
connector conforming to the VITA57.1 format.
The GR-VPX-SPW-MEZZ board has been designed to mount on this connector and provides the
electrical functions and interfaces as represented in the block diagram, Figure 4-2.
Figure 4-2: GR-VPX-SPW-MEZZ Mezzanine Board Block Diagram
4.2 Board Mechanical Format
The design is conceived as a 6U high, 1 slot (25.4mm) wide module for mounting in the
controller slot of a 6U rack with a VPX Backplane.
The dimensions of the main PCB are 233.35x160mm (excluding the connector
protrusions).
To ensure boards are correctly installed in the appropriate slot of a backplane, the VPX
backplane standard defines mechanical alignment keys (Figure 4-3) which can be
defined with various orientations of keying.
However, as the keying for the backplane itself is not definitively known at this stage,
this board has been equipped with 'universal' keys (Part number TE-1-146 4 2- ),
allowing its installation into any slot. These keys can easily be dismounted and replaced
with specific key parts if when these are known.
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MEZZANINE
CONNECTOR
MEZZANINE
CONNECTOR
FRONT PANEL
SPW-0
SPW-0
SPW-1
SPW-1
LVDS
RE
DRIVER
LVDS
RE
DRIVER
LVDS
RE
DRIVER
LVDS
RE
DRIVER
SpW0 is connected with GR740 SPWROUTER PORT1
SpW1 is connected with GR740 SPWROUTER PORT2

GR-VPX-GR740-BOARD
This prototype board is intended for installation in a rack with forced air cooling.
However, for installation in conduction cooled environment, a future design could
accommodate standard wedge locks on the top and bottom rail edges of the board.
This would require the exact wedge lock type and mounting hole definition to be
known, and the front panel to be modified to accommodate them.
A standard FMC style (VITA 57.1) mezzanine interface connector allows the Mezzanine
board to be mounted to the main board.
The dimensional format, outline and mezzanine connector position for the Mezzanine
board follows the requirements of VITA57.1 for a double-slot conduction cooled board.
Due to the necessity to be able to fit the SDRAM module and power converters on the
mezzanine board, the back edge of the board has been extended, giving an overall size
of 13 x 117.5mm.
The face to face mounting distance of the two boards is 10mm. While the prototype
board is mounted using simple 10mm nickel-brass Hex spacers, a future design could
accommodate a custom aluminium bracket to act as a thermal interface between the two
boards.
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Figure 4-3: VPX Style mechanical keying

GR-VPX-GR740-BOARD
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Figure 4-4: Mezzanine board mounted on a GR-VPX-GR740 main board

GR-VPX-GR740-BOARD
4.3 GR740 Microcontroller
The GR740 Leon Processor is a complex device with many modes of operation. For the
details of the interfaces, operation and programming, refer to [RD1].
4.4 Memory
These boards incorporate various on-board memories as follows:
Main Board
SODIMM -SDRAM An SODIMM Module with 48 bit wide interface to the GR740
with 32 bit data and 16 bit check-bit memory width.
MRAM – PROM An MRAM based, 8 bit wide boot Prom is connected to the
Prom interface of the GR740. The implemented device is an
Evers in MR0A08B, which is a 128k x 8bit, 3.3V device. This
device is pin compatible with and alternative device from 3D
lus: 3DMR1M08VS1426.
SPI Flash 512 Mbit SPI serial boot prom (Cypress, S7 FL512S). The SPI
boot memory is connected directly to the SPIM interface of the
GR740 Micro-controller. S7 FL256S consists of two SPI
devices internally. Clock and chip select is common for the two
internal chips bus the MOSI/MOSI buses are independent.
IO0..IO3 versus IO4..IO5. Only the first data bus is connected
with the GR740 and the GR740 has only one SPI bus. The
consequence is that only half the device capacity can be used.
Hence S7 FL512S is used to get 32 MiB capacity.
4. Main Board Interfaces
4. .1 SPW Interfaces
The board incorporates a large number of SpaceWire Links distributed between the
VPX backplane, GR740 Processor, mezzanine connector, External Front panel
connectors and an on board header/connector.
The on-board SPW network is represented in the figure below.
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GR-VPX-GR740-BOARD
GR740 SPW router
port number
Front panel SpW interface
PORT 1 Front Panel port marked as SpW-0
PORT 2 Front Panel port marked as SpW-1
Table 1: GR740 SpW Router Port mapping to Front panel interfaces
GR740 SPW router
port number
Backplane SpW Interface
PORT 3 SPW_PL1R_CP
PORT 4 SPW_PL2N_CP
PORT 5 SPW_PL3R_CP
PORT 6 SPW_PL2R_CP
PORT 7 SPW_PL1N_CP
PORT 8 SPW_PL3N_CP
Table 2: GR740 SpW Router Port mapping to Backplane interfaces
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Figure 4-5: On-Board S acewire Connections
MEZZANINE
CONNECOTR
MEZZANINE
CONNECOTR
GR740
PROCESSOR
GR740
PROCESSOR
VPX
BACKPLANE
VPX
BACKPLANE
SPW_PL2N_CP
SPW_PL1N_CP
SPW_PL3N_CP
SPW_PL2R_CP
SPW_PL1R_CP
SPW_PL3R_CP
SPW_PL3N_DP
SPW_PL2N_DP
SPW_BPN_DP
SPW_PL2R_DP
SPW_PL1R_DP
SPW_PL3R_DP
SPW_PL1N_DP
SPW_BPR_DP
SPW_SCR_CP2
SPW_SCR_CP1
SPW_GR0
SPW_GR1
SPW_HDR LVDS
TRANS-
CEIVER
LVDS
TRANS-
CEIVER
MDM
HEADER
MDM
HEADER
GR-VPX
-SPW-MEZZ
GR-VPX
-SPW-MEZZ
MDM
FP
SpW 1
MDM
FP
SpW 1
MDM
FP
SpW 0
MDM
FP
SpW 0
SPW_GR0
SPW_GR1

GR-VPX-GR740-BOARD
The SPW_0 and SPW_1 link connect to MDM S connector on the GR-VPX-SPW-
MEZZ board and is buffered with a DS10BR150 LVDS repeater circuits.
The SPW_HDR link connect to an MDM S connector on the GR-VPX-GR740 board
and is buffered with a DS10BR150 LVDS repeater circuits.
4. .1.1 SPW connector implementation details and precautions to follow
This equipment has SPW ports that use Low Voltage Differential Signalling (LVDS)
which has limited common mode voltage protection.
Before plugging the SPW cable between two equipment's please power up and make
sure that there is no voltage difference between their grounds.
The SPW standard specification specifies that the cable side outer-shield is bonded to
the connector shell, but does not say anything about the grounding/bonding of the
connector side shell. In this equipment the SPW connector side shell are by default
bonded to the front panel/box local chassis but not bonded to the local GND of the SPW
circuits.
The pin three of this equipment's SPW connectors are connected to the GND through a
parallel capacitor (100p) and resistor (10k) network. When connected to a SPW cable
(properly designed as per the standard) the pin three will be connected to its inner
shield. Note the inner shield does not provide end to end ground connection between
two equipment's as per the SPW standard.
In this equipment there is no grounding provided via the SPW connectors (neither
through pin three inner shield nor through connector side shell between two
equipments). The users connecting the board to other equipment only via SPW should
ensure grounding via other means (e.g. a dedicated wire).
4. .2 Ethernet
An Ethernet RJ45 interface is provided on the board front panel, and is connected to the
Ethernet interface of the GR740 rocessor. This interface can operate in either 100Mbit
or Gbit mode, and can be used either for standard networking, or if the GR740 is
configured, can be used for a debug communication link over Ethernet (EDCL).
An external PHY, (Micrel KSZ9021GN) is implemented on the board.
4. .3 MIL-1 3
A dual MIL-1553 interface is provided on the board, with a DSUB pin connector (J3)
on the front panel. The interface is connected to the MIL-1553 interface pins of the
GR740, via a Holt HI-2579 transceiver. This is a CMOS dual transceiver with integrated
transformers designed to meet the requirements of the MIL-STD-1553 / MIL-STD-1760
specifications.
The configuration on the board is intended for 'transformer coupling'. For a 'direct
coupling' interface to external equipment external 55 Ohm series resistors would be
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