Compaq Deskpro EP 6233 Use and care manual

Technical
Reference
Guide
For the
Compaq Deskpro EP Series Personal Computers

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Technical Reference Guide
Compaq Deskpro EP Series Personal Computers
First Edition – April 1998
i
NOTICE
The information in this document is subject to change without notice.
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CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE,
OR USE OF THIS MATERIAL. IT IS THE RESPONSIBILITY OF MANUFACTURERS TO
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1998 Compaq Computer Corporation
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Technical Reference Guide
for
Compaq Deskpro EP Series Personal Computers
First Edition -April 1998
Document Number DSK-107A/0498

Technical Reference Guide
Compaq Deskpro EP Series Personal Computers
First Edition - April 1998
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Compaq Deskpro EP Series Personal Computers
First Edition – April 1998
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TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION.............................................................................................................
1.1 ABOUT THIS GUIDE ...........................................................................................................1-1
1.1.1 USING THIS GUIDE.....................................................................................................1-1
1.1.2 ADDITIONAL INFORMATION SOURCES..................................................................1-1
1.2 NOTATIONAL CONVENTIONS..........................................................................................1-2
1.2.1 VALUES........................................................................................................................1-2
1.2.2 RANGES........................................................................................................................1-2
1.2.3 SIGNAL LABELS..........................................................................................................1-2
1.2.4 REGISTER NOTATION AND USAGE .........................................................................1-2
1.2.5 BIT NOTATION............................................................................................................ 1-2
1.3 COMMON ACRONYMS AND ABBREVIATIONS..............................................................1-3
CHAPTER 2 SYSTEM OVERVIEW.....................................................................................................
2.1 INTRODUCTION.................................................................................................................. 2-1
2.2 FEATURES...........................................................................................................................2-2
2.2.1 STANDARD FEATURES..............................................................................................2-2
2.2.2 OPTIONS.......................................................................................................................2-2
2.3 MECHANICAL DESIGN......................................................................................................2-3
2.3.1 CABINET LAYOUT......................................................................................................2-3
2.3.2 CHASSIS LAYOUT.......................................................................................................2-4
2.3.3 SYSTEM BOARD LAYOUT......................................................................................... 2-5
2.4 SYSTEM ARCHITECTURE..................................................................................................2-6
2.4.1 PROCESSOR.................................................................................................................2-8
2.4.2 MEMORY...................................................................................................................... 2-8
2.4.3 SUPPORT CHIPSET......................................................................................................2-9
2.4.4 MASS STORAGE..........................................................................................................2-9
2.4.5 SERIAL AND PARALLEL INTERFACES....................................................................2-9
2.4.6 UNIVERSAL SERIAL BUS INTERFACE................................................................... 2-10
2.4.7 GRAPHICS SUBSYSTEM........................................................................................... 2-10
2.5 SPECIFICATIONS..............................................................................................................2-11
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM........................................................................
3.1 INTRODUCTION.................................................................................................................. 3-1
3.2 66-MHZ SLOT 1 PROCESSOR/MEMORY SUBSYSTEM ...................................................3-2
3.2.1 CELERON PROCESSOR...............................................................................................3-3
3.2.2 PENTIUM II PROCESSOR............................................................................................ 3-3
3.2.3 PROCESSOR CHANGING/UPGRADING.....................................................................3-4
3.2.4 SYSTEM MEMORY......................................................................................................3-5
3.2.5 SUBSYSTEM CONFIGURATION.................................................................................3-8
3.3 100-MHZ SLOT 1 PROCESSOR/MEMORY SUBSYSTEM..................................................3-9

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3.3.1 PENTIUM II PROCESSOR.......................................................................................... 3-10
3.3.2 SYSTEM MEMORY.................................................................................................... 3-12
3.3.3 SUBSYSTEM CONFIGURATION............................................................................... 3-13
CHAPTER 4 SYSTEM SUPPORT.........................................................................................................
4.1 INTRODUCTION.................................................................................................................. 4-1
4.2 PCI BUS OVERVIEW...........................................................................................................4-2
4.2.1 PCI CONNECTOR.........................................................................................................4-3
4.2.2 PCI BUS MASTER ARBITRATION..............................................................................4-4
4.2.3 PCI BUS TRANSACTIONS...........................................................................................4-5
4.2.4 OPTION ROM MAPPING ............................................................................................. 4-8
4.2.5 PCI INTERRUPT MAPPING.........................................................................................4-9
4.2.6 PCI POWER MANAGEMENT SUPPORT.....................................................................4-9
4.2.7 PCI CONFIGURATION............................................................................................... 4-10
4.3 AGP BUS OVERVIEW .......................................................................................................4-11
4.3.1 BUS TRANSACTIONS................................................................................................ 4-11
4.3.2 AGP CONFIGURATION............................................................................................. 4-14
4.3.3 AGP CONNECTOR..................................................................................................... 4-15
4.4 ISA BUS OVERVIEW......................................................................................................... 4-16
4.4.1 ISA CONNECTOR ......................................................................................................4-17
4.4.2 ISA BUS TRANSACTIONS......................................................................................... 4-18
4.4.3 DIRECT MEMORY ACCESS......................................................................................4-20
4.4.4 INTERRUPTS.............................................................................................................. 4-23
4.4.5 INTERVAL TIMER.....................................................................................................4-27
4.4.6 ISA CONFIGURATION...............................................................................................4-27
4.5 SYSTEM CLOCK DISTRIBUTION.................................................................................... 4-28
4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY............................................... 4-29
4.6.1 CONFIGURATION MEMORY BYTE DEFINITIONS................................................ 4-30
4.7 I/O MAP AND REGISTER ACCESSING............................................................................ 4-46
4.7.1 SYSTEM I/O MAP ......................................................................................................4-46
4.7.2 82371 SOUTH BRIDGE GPIO CONFIGURATION..................................................... 4-47
4.7.3 87309 I/O CONTROLLER CONFIGURATION ........................................................... 4-49
4.8 SYSTEM MANAGEMENT SUPPORT ............................................................................... 4-50
4.8.1 FLASH ROM WRITE PROTECT ................................................................................4-50
4.8.2 USER SECURITY........................................................................................................4-50
4.8.3 I/O SECURITY............................................................................................................ 4-51
4.8.4 POWER MANAGEMENT........................................................................................... 4-51
CHAPTER 5 INPUT/OUTPUT INTERFACES.....................................................................................
5.1 INTRODUCTION.................................................................................................................. 5-1
5.2 ENHANCED IDE INTERFACE............................................................................................ 5-1
5.2.1 IDE PROGRAMMING...................................................................................................5-1
5.2.2 IDE CONNECTOR........................................................................................................ 5-9
5.3 DISKETTE DRIVE INTERFACE........................................................................................5-10
5.3.1 DISKETTE DRIVE PROGRAMMING ........................................................................ 5-11
5.3.2 DISKETTE DRIVE CONNECTOR.............................................................................. 5-14
5.4 SERIAL INTERFACE ......................................................................................................... 5-15

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5.4.1 RS-232 INTERFACE ...................................................................................................5-15
5.4.2 SERIAL INTERFACE PROGRAMMING.................................................................... 5-16
5.5 PARALLEL INTERFACE...................................................................................................5-21
5.5.1 STANDARD PARALLEL PORT MODE ..................................................................... 5-21
5.5.2 ENHANCED PARALLEL PORT MODE..................................................................... 5-22
5.5.3 EXTENDED CAPABILITIES PORT MODE............................................................... 5-22
5.5.4 PARALLEL INTERFACE PROGRAMMING.............................................................. 5-23
5.5.5 PARALLEL INTERFACE CONNECTOR ................................................................... 5-27
5.6 KEYBOARD/POINTING DEVICE INTERFACE ...............................................................5-28
5.6.1 KEYBOARD INTERFACE OPERATION ...................................................................5-28
5.6.2 POINTING DEVICE INTERFACE OPERATION .......................................................5-30
5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING ......................... 5-30
5.6.4 KEYBOARD/POINTING DFEVICE INTERFACE CONNECTOR.............................. 5-34
5.7 UNIVERSAL SERIAL BUS INTERFACE........................................................................... 5-35
5.7.1 USB KEYBOARD CONSIDERATIONS...................................................................... 5-35
5.7.2 USB CONFIGURATION.............................................................................................. 5-35
5.7.3 USB CONTROL........................................................................................................... 5-36
5.7.4 USB CONNECTOR .....................................................................................................5-36
CHAPTER 6 POWER AND SIGNAL DISTRIBUTION.......................................................................
6.1 INTRODUCTION.................................................................................................................. 6-1
6.2 POWER SUPPLY ASSEMBLY/CONTROL..........................................................................6-1
6.2.1 POWER SUPPLY ASSEMBLY......................................................................................6-2
6.2.2 POWER CONTROL.......................................................................................................6-3
6.3 POWER DISTRIBUTION......................................................................................................6-5
6.3.1 3/5/12 VDC DISTRIBUTION.........................................................................................6-5
6.3.2 LOW VOLTAGE DISTRIBUTION................................................................................ 6-6
6.4 GENERAL SIGNAL DISTRIBUTION ..................................................................................6-7
CHAPTER 7 BIOS ROM .......................................................................................................................
7.1 INTRODUCTION.................................................................................................................. 7-1
7.2 BOOT FUNCTIONS..............................................................................................................7-2
7.2.1 BOOT BLOCK...............................................................................................................7-2
7.2.2 QUICKBOOT.................................................................................................................7-2
7.2.3 SILENTBOOT ............................................................................................................... 7-2
7.3 MEMORY DETECTION AND CONFIGURATION..............................................................7-3
7.4 CLIENT MANAGEMENT SUPPORT...................................................................................7-4
7.4.1 SYSTEM ID/REVISION/SERIAL NO. ..........................................................................7-6
7.4.2 SYSTEM INFORMATION TABLE...............................................................................7-6
7.4.3 EDID RETRIEVE ........................................................................................................ 7-12
7.4.4 DRIVE FAULT PREDICTION..................................................................................... 7-12
7.4.5 SYSTEM MAP RETRIEVAL....................................................................................... 7-13
7.4.6 FLASH ROM FUNCTIONS......................................................................................... 7-14
7.4.7 POWER BUTTON FUNCTIONS.................................................................................7-14
7.4.8 ACCESSING CMOS....................................................................................................7-16

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7.4.9 ACCESSING CMOS FEATURE BITS......................................................................... 7-16
7.4.10 SECURITY FUNCTIONS............................................................................................7-18
7.5 PNP SUPPORT.................................................................................................................... 7-19
7.5.1 SMBIOS....................................................................................................................... 7-20
7.6 POWER MANAGEMENT FUNCTIONS ............................................................................ 7-21
7.6.1 INDEPENDENT PM SUPPORT .................................................................................. 7-21
7.6.2 ACPI SUPPORT...........................................................................................................7-21
7.6.3 APM SUPPORT...........................................................................................................7-22
7.7 USB LEGACY SUPPORT ................................................................................................... 7-24
7.8 BIOS UPGRADING............................................................................................................. 7-24
APPENDIX A ERROR MESSAGES AND CODES...............................................................................
A.1 INTRODUCTION.................................................................................................................A-1
A.2 POWER-ON MESSAGES..................................................................................................... A-1
A.3 BEEP/KEYBOARD LED CODES........................................................................................ A-1
A.4 POWER-ON SELF TEST (POST) MESSAGES.................................................................... A-2
A.5 PROCESSOR ERROR MESSAGES (1XX-XX) ...................................................................... A-3
A.6 MEMORY ERROR MESSAGES (2XX-XX)........................................................................... A-4
A.7 KEYBOARD ERROR MESSAGES (30X-XX)....................................................................... A-4
A.8 PRINTER ERROR MESSAGES (4XX-XX)............................................................................ A-5
A.9 VIDEO (GRAPHICS) ERROR MESSAGES (5XX-XX).......................................................... A-5
A.10 DISKETTE DRIVE ERROR MESSAGES (6XX-XX) ......................................................... A-6
A.11 SERIAL INTERFACE ERROR MESSAGES (11XX-XX)................................................... A-6
A.12 MODEM COMMUNICATIONS ERROR MESSAGES (12XX-XX).................................... A-7
A.13 HARD DRIVE ERROR MESSAGES (17XX-XX)............................................................... A-8
A.14 HARD DRIVE ERROR MESSAGES (19XX-XX)............................................................... A-9
A.15 VIDEO (GRAPHICS) ERROR MESSAGES (24XX-XX) .................................................... A-9
A.16 AUDIO ERROR MESSAGES (3206-XX)......................................................................... A-10
A.17 NETWORK INTERFACE ERROR MESSAGES (60XX-XX) ........................................... A-10
A.18 SCSI INTERFACE ERROR MESSAGES (65XX-XX, 66XX-XX, 67XX-XX) ....................... A-11
A.19 POINTING DEVICE INTERFACE ERROR MESSAGES (8601-XX).............................. A-11
A.20 CEMM PRIVILEDGED OPS ERROR MESSAGES........................................................ A-12
A.21 CEMM EXCEPTION ERROR MESSAGES ................................................................... A-12
APPENDIX B ASCII CHARACTER SET .............................................................................................
B.1 INTRODUCTION..................................................................................................................B-1
APPENDIX C KEYBOARD...................................................................................................................
C.1 INTRODUCTION..................................................................................................................C-1
C.2 KEYSTROKE PROCESSING................................................................................................C-2
C.2.1 TRANSMISSIONS TO THE SYSTEM ..........................................................................C-3
C.2.2 KEYBOARD LAYOUTS ...............................................................................................C-4
C.2.3 KEYS.............................................................................................................................C-7
C.2.4 KEYBOARD COMMANDS.........................................................................................C-10

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C.2.5 SCAN CODES.............................................................................................................C-10
APPENDIX D AUDIO CARD.................................................................................................................
D.1 INTRODUCTION.................................................................................................................D-1
D.2 FUNCTIONAL DESCRIPTION............................................................................................ D-2
D.2.1 PCM AUDIO PROCESSING......................................................................................... D-4
D.2.2 FM SYNTHESIS AUDIO PROCESSING...................................................................... D-7
D.3 AUDIO CARD PROGRAMMING........................................................................................ D-8
D.3.1 CONFIGURATION....................................................................................................... D-8
D.3.2 CONTROL....................................................................................................................D-9
D.4 SPECIFICATIONS............................................................................................................. D-11
APPENDIX E ATI RAGE IIC GRAPHICS CARD...............................................................................
E.1 INTRODUCTION..................................................................................................................E-1
E.2 FUNCTIONAL DESCRIPTION.............................................................................................E-2
E.2.1 ATI RAGE IIC GRAPHICS CONTROLLER..................................................................E-3
E.3 DISPLAY CONFIGURATIONS ............................................................................................E-4
E.4 PROGRAMMING..................................................................................................................E-5
E.4.1 CONFIGURATION........................................................................................................E-5
E.4.2 CONTROL.....................................................................................................................E-5
E.5 POWER MANAGEMENT.....................................................................................................E-6
E.5.1 MONITOR CONTROL ..................................................................................................E-6
E.5.2 POWER CONSUMPTION .............................................................................................E-6
E.6 CONNECTORS.....................................................................................................................E-7
E.6.2 MONITOR CONNECTOR.............................................................................................E-7
E.6.3 MULTIMEDIA INTERFACE CONNECTOR ................................................................E-8
APPENDIX F ATI RAGE PRO AGP 1X GRAPHICS CARD ..............................................................
F.1 INTRODUCTION..................................................................................................................F-1
F.2 FUNCTIONAL DESCRIPTION.............................................................................................F-2
F.2.1 ATI RAGE PRO TURBO AGP GRAPHICS CONTROLLER.........................................F-3
F.3 DISPLAY MODES................................................................................................................F-4
F.4 PROGRAMMING..................................................................................................................F-5
F.4.1 CONFIGURATION........................................................................................................F-5
F.4.2 CONTROL.....................................................................................................................F-5
F.5 MONITOR POWER MANAGEMENT CONTROL...............................................................F-6
F.6 CONNECTORS.....................................................................................................................F-6
F.6.1 MEMORY EXPANSION CONNECTOR.......................................................................F-6
F.6.2 MONITOR CONNECTOR.............................................................................................F-7
F.6.3 MULTIMEDIA INTERFACE CONNECTOR ................................................................F-8

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APPENDIX G DIAMOND FIRE GRAPHICS CARD...........................................................................
G.1 INTRODUCTION.................................................................................................................G-1
G.2 FUNCTIONAL DESCRIPTION............................................................................................ G-2
G.2.1 SGS nVIDIA RIVA 128 GRAPHICS CONTROLLER................................................... G-3
G.3 DISPLAY MODES............................................................................................................... G-4
G.4 PROGRAMMING................................................................................................................. G-5
G.4.1 CONFIGURATION....................................................................................................... G-5
G.4.2 CONTROL....................................................................................................................G-5
G.5 MONITOR POWER MANAGEMENT CONTROL.............................................................. G-6
G.6 CONNECTORS.................................................................................................................... G-6
G.6.1 MONITOR CONNECTOR............................................................................................ G-7
G.6.2 MEDIA PORT CONNECTOR ...................................................................................... G-8

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LIST OF FIGURES
FIGURE 2–1. COMPAQ DESKPRO EP PERSONAL COMPUTERS WITH MONITOR ..........................................2-1
FIGURE 2–2. CABINET LAYOUT, FRONT VIEW .......................................................................................2-3
FIGURE 2–3. CABINET LAYOUT, REAR VIEW .........................................................................................2-3
FIGURE 2–4. CHASSIS LAYOUT, TOP VIEW ............................................................................................2-4
FIGURE 2–5. SYSTEM BOARD LAYOUT, COMPONENT SIDE .....................................................................2-5
FIGURE 2–6. SYSTEM ARCHITECTURE, BLOCK DIAGRAM........................................................................2-7
FIGURE 2–7. PROCESSOR ARCHITECTURAL COMPARISON DIAGRAM........................................................ 2-8
FIGURE 3–1. 66-MHZ SLOT 1 PROCESSOR/MEMORY SUBSYSTEM ARCHITECTURE...................................3-2
FIGURE 3–2. CELERON PROCESSOR INTERNAL ARCHITECTURE...............................................................3-3
FIGURE 3–3. PENTIUM II PROCESSOR INTERNAL ARCHITECTURE............................................................. 3-3
FIGURE 3–4. SYSTEM MEMORY MAP..................................................................................................... 3-7
FIGURE 3–5. 100-MHZ SLOT 1 PROCESSOR/MEMORY SUBSYSTEM ARCHITECTURE.................................3-9
FIGURE 3–6. 350-/400-MHZ PENTIUM II PROCESSOR INTERNAL ARCHITECTURE .................................. 3-10
FIGURE 4–1. PCI BUS DEVICES AND FUNCTIONS.....................................................................................4-2
FIGURE 4–2. PCI BUS CONNECTOR (32-BIT TYPE).................................................................................4-3
FIGURE 4–3. TYPE 0 CONFIGURATION CYCLE........................................................................................4-6
FIGURE 4–4. PCI CONFIGURATION SPACE MAP......................................................................................4-7
FIGURE 4–5. AGP 1X DATA TRANSFER (PEAK TRANSFER RATE: 266 MB/S)........................................ 4-12
FIGURE 4–6. AGP 2X DATA TRANSFER (PEAK TRANSFER RATE: 532 MB/S)........................................ 4-13
FIGURE 4–7. AGP BUS CONNECTOR ...................................................................................................4-15
FIGURE 4–8. ISA BUS BLOCK DIAGRAM................................................................................................ 4-16
FIGURE 4–9. ISA EXPANSION CONNECTOR.......................................................................................... 4-17
FIGURE 4–10. MASKABLE INTERRUPT PROCESSING, BLOCK DIAGRAM.................................................. 4-23
FIGURE 4–11. CONFIGURATION MEMORY MAP.................................................................................... 4-29
FIGURE 5–1. 40-PIN IDE CONNECTOR. .................................................................................................5-9
FIGURE 5–2. 34-PIN DISKETTE DRIVE CONNECTOR.............................................................................. 5-14
FIGURE 5–3. SERIAL INTERFACE CONNECTOR (MALE DB-9 AS VIEWED FROM REAR OF CHASSIS)........... 5-15
FIGURE 5–4. PARALLEL INTERFACE CONNECTOR (FEMALE DB-25 AS VIEWED FROM REAR OF CHASSIS).. 5-27
FIGURE 5–5. 8042-TO-KEYBOARD TRANSMISSION OF CODE EDH, TIMING DIAGRAM............................ 5-28
FIGURE 5–6. KEYBOARD OR POINTING DEVICE INTERFACE CONNECTOR............................................... 5-34
FIGURE 5–7. UNIVERSAL SERIAL BUS CONNECTOR (ONE OF TWO AS VIEWED FROM REAR OF CHASSIS)..... 5-36
FIGURE 6–1. POWER SUPPLY ASSEMBLY AND ASSOCIATED CIRCUITRY, BLOCK DIAGRAM....................... 6-1
FIGURE 6–2. POWER CABLE DIAGRAM ..................................................................................................6-5
FIGURE 6–3. LOW VOLTAGE REGULATOR CIRCUITRY, BLOCK DIAGRAM ................................................. 6-6
FIGURE 6–4. GENERAL SIGNAL DISTRIBUTION, FUNCTIONAL BLOCK DIAGRAM.......................................6-7
FIGURE 6–5. FRONT PANEL (BEZEL) CONTROL/INDICATOR CONNECTOR ................................................ 6-8
FIGURE 6–6. WAKE-ON-LAN NIC CONNECTOR....................................................................................6-8
FIGURE B–1. ASCII CHARACTER SET ...................................................................................................B-1

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FIGURE C–1. KEYSTROKE PROCESSING ELEMENTS, BLOCK DIAGRAM ....................................................C-2
FIGURE C–2. KEYBOARD-TO-SYSTEM TRANSMISSION OF CODE 58H, TIMING DIAGRAM..........................C-3
FIGURE C–3. U.S. ENGLISH (101-KEY) KEYBOARD KEY POSITIONS.......................................................C-4
FIGURE C–4. NATIONAL (102-KEY) KEYBOARD KEY POSITIONS............................................................C-4
FIGURE C–5. U.S. ENGLISH WINDOWS (101W-KEY) KEYBOARD KEY POSITIONS...................................C-5
FIGURE C–6. NATIONAL WINDOWS (102W-KEY) KEYBOARD KEY POSITIONS ........................................C-5
FIGURE C–7. U.S. ENGLISH WINDOWS (101WE-KEY) KEYBOARD KEY POSITIONS.................................C-6
FIGURE C–8. NATIONAL WINDOWS (102WE-KEY) KEYBOARD KEY POSITIONS......................................C-6
FIGURE C–9. SCANNER ELEMENTS, BLOCK DIAGRAM..........................................................................C-14
FIGURE C–10. SCANNER OPERATION FLOW CHART ..............................................................................C-16
FIGURE D–1. AUDIO CARD LAYOUT..................................................................................................... D-1
FIGURE D–2. AUDIO CARD BLOCK DIAGRAM........................................................................................ D-3
FIGURE D–3. ANALOG SIGNAL SAMPLING/QUANTIZING ........................................................................ D-4
FIGURE D–4. DAC OPERATION ........................................................................................................... D-5
FIGURE D–5. AUDIO CARD-TO-ISA BUS PCM AUDIO DATA FORMATS / BYTE ORDERING...................... D-6
FIGURE D–6. FM SYNTHESIS PATCH.................................................................................................... D-7
FIGURE D–7. AUDIO CAR-TO-ISA BUS FM AUDIO DATA FORMAT ........................................................ D-7
FIGURE E–1. ATI RAGE IIC AGP GRAPHICS CARD LAYOUT (COMPAQ P/N 332836-001) ......................... 1
FIGURE E–2. ATI RAGE IIC AGP GRAPHICS CARD BLOCK DIAGRAM...................................................... 2
FIGURE E–3. ATI 3D RAGE IIC GRAPHICS CONTROLLER INTERNAL ARCHITECTURE ............................... 3
FIGURE E–4. VGA MONITOR CONNECTOR, (FEMALE DB-15, AS VIEWED FROM REAR)................................. 7
FIGURE E–5. MULTIMEDIA INTERFACE CONNECTOR (40-PIN HEADER P1).................................................. 8
FIGURE F–1. ATI RAGE PRO AGP GRAPHICS CARD LAYOUT (P/N 008061-XXX)....................................F-1
FIGURE F–2. ATI RAGE PRO AGP GRAPHICS CARD BLOCK DIAGRAM .................................................F-2
FIGURE F–3. ATI 3DRAGE PRO GRAPHICS CONTROLLER INTERNAL ARCHITECTURE...............................F-3
FIGURE F–4. VGA MONITOR CONNECTOR, (FEMALE DB-15, AS VIEWED FROM REAR)..............................F-7
FIGURE F–5. MULTIMEDIA INTERFACE CONNECTOR (40-PIN HEADER P1)...............................................F-8
FIGURE G–1. DIAMOND FIRE AGP GRAPHICS CARD LAYOUT................................................................. G-1
FIGURE G–2. DIAMOND FIRE AGP GRAPHICS CARD BLOCK DIAGRAM................................................... G-2
FIGURE G–3. SGS NVIDIA RIVA 128 GRAPHICS CONTROLLER INTERNAL ARCHITECTURE................... G-3
FIGURE G–4. VGA MONITOR CONNECTOR, (FEMALE DB-15, AS VIEWED FROM REAR). ........................... G-7
FIGURE G–5. MEDIA PORT CONNECTOR (26-PIN HEADER P1)............................................................... G-8

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LIST OF TABLES
TABLE 1–1. ACRONYMS AND ABBREVIATIONS.......................................................................................1-3
TABLE 2–1. ARCHITECTURAL COMPARISON.............................................................................................2-6
TABLE 2–2. SUPPORT CHIPSETS ............................................................................................................2-9
TABLE 2–3. GRAPHICS SUBSYSTEM COMPARISON ................................................................................ 2-10
TABLE 2–4. ENVIRONMENTAL SPECIFICATIONS.................................................................................... 2-11
TABLE 2–5. ELECTRICAL SPECIFICATIONS ........................................................................................... 2-11
TABLE 2–6. PHYSICAL SPECIFICATIONS............................................................................................... 2-11
TABLE 2–7. DISKETTE DRIVE SPECIFICATIONS..................................................................................... 2-12
TABLE 2–8. 8X CD-ROM DRIVE SPECIFICATIONS................................................................................ 2-12
TABLE 2–9. HARD DRIVE SPECIFICATIONS........................................................................................... 2-13
TABLE 3–1. PROCESSOR/MEMORY ARCHITECTURAL COMPARISON...........................................................3-1
TABLE 3–2. PENTIUM II COVINGTON PROCESSOR BUS/CORE SPEED SWITCH SETTINGS.......................3-4
TABLE 3–3. SPD ADDRESS MAP (SDRAM DIMM).................................................................................3-6
TABLE 3–4. HOST/PCI BRIDGE CONFIGURATION REGISTERS (443EX, FUNCTION 0) ................................3-8
TABLE 3–5. PENTIUM II MICROPROCESSOR BUS/CORE SPEED SWITCH SETTINGS .................................. 3-11
TABLE 3–6. HOST/PCI BRIDGE CONFIGURATION REGISTERS (443BX, FUNCTION 0) .............................. 3-13
TABLE 4–1. PCI BUS CONNECTOR PINOUT............................................................................................ 4-3
TABLE 4–2. PCI BUS MASTERING DEVICES........................................................................................... 4-4
TABLE 4–3. PCI DEVICE CONFIGURATION ACCESS................................................................................4-6
TABLE 4–4. PCI FUNCTION CONFIGURATION ACCES..............................................................................4-7
TABLE 4–5. PCI DEVICE IDENTIFICATION .............................................................................................4-8
TABLE 4–6. PCI/ISA BRIDGE CONFIGURATION REGISTERS (82371, FUNCTION 0).................................. 4-10
TABLE 4–7. PCI/AGP BRIDGE CONFIGURATION REGISTERS (82371, FUNCTION 1)................................. 4-14
TABLE 4–8. AGP BUS CONNECTOR PINOUT .........................................................................................4-15
TABLE 4–9. ISA EXPANSION CONNECTOR PINOUT............................................................................... 4-17
TABLE 4–10. DEFAULT DMA CHANNEL ASSIGNMENTS ....................................................................... 4-20
TABLE 4–11. DMA PAGE REGISTER ADDRESSES................................................................................. 4-21
TABLE 4–12. DMA CONTROLLER REGISTERS...................................................................................... 4-22
TABLE 4–13. MASKABLE INTERRUPT PRIORITIES AND ASSIGNMENTS.................................................... 4-24
TABLE 4–14. MASKABLE INTERRUPT CONTROL REGISTERS.................................................................. 4-24
TABLE 4–15. INTERVAL TIMER FUNCTIONS .........................................................................................4-27
TABLE 4–16. INTERVAL TIMER CONTROL REGISTERS........................................................................... 4-27
TABLE 4–17. CLOCK GENERATION AND DISTRIBUTION ........................................................................ 4-28
TABLE 4–18. CONFIGURATION MEMORY (CMOS) MAP....................................................................... 4-30
TABLE 4–19. SYSTEM I/O MAP...........................................................................................................4-46
TABLE 4–20. 82371 SOUTH BRIDGE GENERAL PURPOSE INPUT PORT UTILIZATION ............................... 4-47
TABLE 4–21. 82371 SOUTH BRIDGE GENERAL PURPOSE OUTPUT PORT UTILIZATION............................ 4-48
TABLE 4–22. 87309 I/O CONTROLLER PNP STANDARD CONFIGURATION REGISTERS.............................. 4-49
TABLE 5–1. IDE PCI CONFIGURATION REGISTERS ................................................................................5-2

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TABLE 5–2. IDE BUS MASTER CONTROL REGISTERS............................................................................. 5-3
TABLE 5–3. IDE ATA CONTROL REGISTERS.........................................................................................5-4
TABLE 5–4. IDE CONTROLLER COMMANDS ..........................................................................................5-7
TABLE 5–5. 40-PIN IDE CONNECTOR PINOUT .......................................................................................5-9
TABLE 5–6. DISKETTE DRIVE CONTROLLER CONFIGURATION REGISTERS ............................................. 5-11
TABLE 5–7. DISKETTE DRIVE CONTROLLER REGISTERS ....................................................................... 5-12
TABLE 5–8. 34-PIN DISKETTE DRIVE CONNECTOR PINOUT................................................................... 5-14
TABLE 5–9. DB-9 SERIAL CONNECTOR PINOUT................................................................................... 5-15
TABLE 5–10. SERIAL INTERFACE CONFIGURATION REGISTERS.............................................................. 5-16
TABLE 5–11. SERIAL INTERFACE CONTROL REGISTERS........................................................................ 5-17
TABLE 5–12. PARALLEL INTERFACE CONFIGURATION REGISTERS......................................................... 5-23
TABLE 5–13. PARALLEL INTERFACE CONTROL REGISTERS ................................................................... 5-24
TABLE 5–14. DB-25 PARALLEL CONNECTOR PINOUT .......................................................................... 5-27
TABLE 5–15. 8042-TO-KEYBOARD COMMANDS .................................................................................. 5-29
TABLE 5–16. KEYBOARD/MOUSE INTERFACE CONFIGURATION REGISTERS ........................................... 5-30
TABLE 5–17. CPU COMMANDS TO THE 8042...................................................................................... 5-32
TABLE 5–18. KEYBOARD/POINTING DEVICE CONNECTOR PINOUT........................................................ 5-34
TABLE 5–19. USB INTERFACE CONFIGURATION REGISTERS................................................................. 5-35
TABLE 5–20. USB CONTROL REGISTERS.............................................................................................5-36
TABLE 5–21. USB CONNECTOR PINOUT ..............................................................................................5-36
TABLE 6–1. POWER SUPPLY ASSEMBLY SPECIFICATIONS........................................................................6-2
TABLE 7–1. PNP CLIENT MANAGEMENT FUNCTIONS (INT15)................................................................7-4
TABLE 7–2. PNP BIOS FUNCTIONS..................................................................................................... 7-19
TABLE 7–3. APM BIOS FUNCTIONS (INT15) .....................................................................................7-23
TABLE A–1. POWER-ON MESSAGES ..................................................................................................... A-1
TABLE A–2. BEEP/KEYBOARD LED CODES.......................................................................................... A-1
TABLE A–3. POWER-ON SELF TEST (POST) MESSAGES........................................................................ A-2
TABLE A–4. PROCESSOR ERROR MESSAGES ......................................................................................... A-3
TABLE A–5. MEMORY ERROR MESSAGES............................................................................................. A-4
TABLE A–6. KEYBOARD ERROR MESSAGES.......................................................................................... A-4
TABLE A–7. PRINTER ERROR MESSAGES.............................................................................................. A-5
TABLE A–8. VIDEO (GRAPHICS) ERROR MESSAGES .............................................................................. A-5
TABLE A–9. DISKETTE DRIVE ERROR MESSAGES.................................................................................. A-6
TABLE A–10. SERIAL INTERFACE ERROR MESSAGES............................................................................. A-6
TABLE A–11. SERIAL INTERFACE ERROR MESSAGES............................................................................. A-7
TABLE A–12. HARD DRIVE ERROR MESSAGES...................................................................................... A-8
TABLE A–13. HARD DRIVE ERROR MESSAGES...................................................................................... A-9
TABLE A–14. HARD DRIVE MESSAGES ................................................................................................. A-9
TABLE A–15. AUDIO ERROR MESSAGES............................................................................................. A-10
TABLE A–16. NETWORK INTERFACE ERROR MESSAGES...................................................................... A-10
TABLE A–17. SCSI INTERFACE ERROR MESSAGES ............................................................................. A-11
TABLE A–18. POINTING DEVICE INTERFACE ERROR MESSAGES........................................................... A-11
TABLE A–19. CEMM PRIVILEGED OPS ERROR MESSAGES.................................................................. A-12
TABLE A–20. CEMM EXCEPTION ERROR MESSAGES ......................................................................... A-12

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TABLE C–1. KEYBOARD-TO-SYSTEM COMMANDS ...............................................................................C-10
TABLE C–2. KEYBOARD SCAN CODES.................................................................................................C-11
TABLE C–3. SCANNER PERFORMANCE CHART .....................................................................................C-17
TABLE C–4. SCANNER I/F SIGNALS.....................................................................................................C-18
TABLE C–5. SCANNER SPECIFICATIONS...............................................................................................C-20
TABLE D–1. AUDIO MODE DIFFERENCES.............................................................................................. D-6
TABLE D–2. AUDIO CARD I/O MAP ..................................................................................................... D-9
TABLE D–3. COMPATIBILITY MODE AUDIO MIXER CONTROL REGISTER MAPPING ................................... D-9
TABLE D–4. EXTENDED MODE AUDIO MIXER CONTROL REGISTER MAPPING ........................................ D-10
TABLE D–5. FM SYNTHESIZER CONTROL REGISTER MAPPING .............................................................. D-10
TABLE D–6. AUDIO CARD SPECIFICATIONS ........................................................................................ D-11
TABLE E–1. 2D GRAPHICS DISPLAY MODES (W/EDO RAM)...................................................................... 4
TABLE E–2. 3D GRAPHICS DISPLAY MODES............................................................................................... 4
TABLE E–3. ATI RAGE IIC PCI CONFIGURATION SPACE REGISTERS....................................................... 5
TABLE E–4. STANDARD VGA MODE I/O MAPPING .................................................................................. 5
TABLE E–5. MONITOR POWER MANAGEMENT CONDITIONS ...................................................................... 6
TABLE E–6. DB-15 MONITOR CONNECTOR PINOUT ................................................................................. 7
TABLE E–7. MULTIMEDIA INTERFACE CONNECTOR PINOUT ...................................................................... 8
TABLE F–1. 2D GRAPHICS DISPLAY MODES (W/SGRAM)........................................................................F-4
TABLE F–2. 3D GRAPHICS DISPLAY MODES............................................................................................F-4
TABLE F–3. ATI RAGE PRO PCI CONFIGURATION SPACE REGISTERS ..................................................F-5
TABLE F–4. STANDARD VGA MODE I/O MAPPING................................................................................F-5
TABLE F–5. MONITOR POWER MANAGEMENT CONDITIONS....................................................................F-6
TABLE F–6. DB-15 MONITOR CONNECTOR PINOUT...............................................................................F-7
TABLE F–7. MULTIMEDIA INTERFACE CONNECTOR PINOUT ...................................................................F-8
TABLE G–1. 2D GRAPHICS DISPLAY MODES (W/SGRAM)...................................................................... G-4
TABLE G–2. SGS NVIDA RIVA 128 PCI CONFIGURATION SPACE REGISTERS...................................... G-5
TABLE G–3. STANDARD VGA MODE I/O MAPPING .............................................................................. G-5
TABLE G–4. MONITOR POWER MANAGEMENT CONDITIONS.................................................................. G-6
TABLE G–5. DB-15 MONITOR CONNECTOR PINOUT ............................................................................. G-7
TABLE G–6. MEDIA PORT CONNECTOR PINOUT.................................................................................... G-8

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First Edition - April 1998
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Technical Reference Guide
Compaq Deskpro EP Series of Personal Computers
First Edition - April 1998
1-1
Chapter 1
INTRODUCTION
1. Chapter 1 INTRODUCTION
1.1 ABOUT THIS GUIDE
This guide provides technical information about the Compaq Deskpro EP Series of Personal
Computers. This document includes information regarding system design, function, and features
that can be used by programmers, engineers, technicians, and system administrators.
1.1.1 USING THIS GUIDE
This guide consists of chapters and appendices. The chapters primarily describe the hardware
and firmware elements contained within the chassis and specifically deal with the system board
and the power supply assembly. The appendices contain general information about standard
peripheral devices such as the keyboard as well as separate audio or other interface cards, as well
as other general information in tabular format.
1.1.2 ADDITIONAL INFORMATION SOURCES
This guide does not describe in detail other manufacturer’s components used in the product
covered. For more information on individual commercial-off-the-shelf (COTS) components refer
to the indicated manufacturers’ documentation. The products covered by this guide use
architecture based on industry-standard specifications that can be referenced for detailed
information.
Hardcopy documentation sources:
♦The Lotus/Intel/Microsoft Expanded Memory Specification, Ver. 4.0
♦PCI Local Bus Specification Revision 2.1
Online information sources:
♦Compaq Computer Corporation: http://www.compaq.com
♦Intel Corporation: http://www.intel.com
♦National Semiconductor Incorporated: http://www.national.com
♦AGP forum: http://www.agpforum.org/index.htm
♦ATI Incorporated: http://www.atitech.com
♦NVIDIA Corp.: http://www.nvidia.com

Chapter 1 Introduction
Compaq Deskpro EP Series of Personal Computers
First Edition – April 1998
1-2
1.2 NOTATIONAL CONVENTIONS
1.2.1 VALUES
Hexadecimal values are indicated bythe letter “h” following an alpha-numerical value. Binary
values are indicated by the letter “b” following a value of ones and zeros. Memory addresses
expressed as “SSSS:OOOO” (SSSS = 16-bit segment, OOOO = 16-bit offset) can be assumed as
a hexadecimal value. Values that have no succeeding letter can be assumed to be decimal.
1.2.2 RANGES
Ranges or limits for a parameter are shown as a pair of values separated by two dots:
Example: Bits <7..4> = bits 7, 6, 5, and 4.
1.2.3 SIGNAL LABELS
Signal names are indicated using abbreviations, acronyms, or, if possible, the full signal name in
all capital letters. Signals that are meant to be active low are indicated with a dash immediately
following the name.
1.2.4 REGISTER NOTATION AND USAGE
This guide uses standard Intel naming conventions in discussing the microprocessor’s (CPU)
internal registers. Registers that are accessed through programmable I/O using an indexing
scheme are indicated using the following format:
03C5.17h
Index port
Data port
In the example above, register 03C5.17h is accessed by writing the index port value 17h to the
index address (03C4h), followed by a write to or a read from port 03C5h.
1.2.5 BIT NOTATION
Bit values are labeled with bit <0> representing the least-significant bit (LSb) and bit <7>
representing the most-significant bit (MSb) of a byte. Bytes, words, double words, and quad
words are typically shown with most-significant portions on the left or top and the least-
significant portions on the right or bottom respectively.

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First Edition - April 1998
1-3
1.3 COMMON ACRONYMS AND ABBREVIATIONS
Table 1-1 lists the acronyms and abbreviations used in this guide.
Table 1–1. Acronyms and Abbreviations
Table 1-1.
Acronyms and Abbreviations
Acronym/Abbreviation Description
A ampere
AC alternating current
ACPI Advanced Configuration and Power Interface
A/D analog-to-digital
AGP Accelerated graphics port
API application programming interface
APM advanced power management
ASIC application-specific integrated circuit
AT 1. attention (commands) 2. 286-based PC architecture
ATA AT attachment (mode)
AVI audio-video interleaved
AVGA Advanced VGA
BCD binary-coded decimal
BIOS basic input/output system
bis second/new revision
BitBLT bit block transfer
BNC Bayonet Neill-Concelman (connector)
bps or b/s bits per second
BSP Bootstrap processor
CAS column address strobe
CD compact disk
CD-ROM compact disk read-only memory
CDS compct disk system
CF carry flag
CGA color graphics adapter
Ch channel
CLUT color look-up table (pallete)
cm centimeter
CMC cache/memory controller
CMOS complimentary metal-oxide semiconductor (configuration memory)
Cntlr controller
codec compressor/decompressor
CPQ Compaq
CPU central processing unit
CRT cathode ray tube
CSM Compaq system management / Compaq server management
DAA direct access arrangement
DAC digital-to-analog converter
db decibel
DC direct current
DCH DOS compatibility hole
DDC Display Data Channel
DF direction flag
Continued

Chapter 1 Introduction
Compaq Deskpro EP Series of Personal Computers
First Edition – April 1998
1-4
Table 1-1. Acronyms and Abbreviations
Continued
Acronym/Abbreviation Description
DIMM dual inline memory module
DIN Deutche IndustriNorm (connector standard)
DIP dual inline package
DMA direct memory access
DMI Desktop management interface
dpi dots per inch
DRAM dynamic random access memory
DRQ data request
ECC error correction coding
EDID extended display identification data
EDO extended data out (RAM type)
EEPROM electrically eraseable PROM
EGA enhanced graphics adapter
EIA Electronic Industry Association
EISA extended ISA
EPP enhanced parallel port
EIDE enhanced IDE
ESCD Extended System Configuration Data (format)
EV Environmental Variable (data)
ExCA Exchangeable Card Architecture
FIFO first in / first out
FL flag (register)
FM frequency modulation
FPM fast page mode (RAM type)
FPU Floating point unit (numeric or math coprocessor)
ft foot
GB gigabyte
GND ground
GPIO general purpose I/O
GPOC general purpose open-collector
GUI graphics user interface
h hexadecimal
HW hardware
hex hexadecimal
Hz hertz
IDE integrated drive element
IEEE Institute of Electrical and Electronic Engineers
IF interrupt flag
I/F interface
in inch
INT interrupt
I/O input/output
IPL initial program loader
IrDA InfraRed Data Association
IRQ interrupt request
ISA industry standard architecture
JEDEC Joint Electron Device Engineering Council
Kb / KB kilobits / kilobytes (x 1024 bits / x 1024 bytes)
Kb/s kilobits per second
kg kilogram
KHz kilohertz
kv kilovolt
Continued