Crystal CS5521-AS Operating and maintenance instructions

Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.crystal.com
CS5521
CS5523
2- or 4-Channel 16-Bit Buffered ∆Σ Multi-Range ADC
Features
lDelta-Sigma A/D Converter
—Linearity Error: 0.0015%FS
lBuffered Bipolar/Unipolar Input Ranges
—25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V
lChopper Stabilized Instrumentation Amplifier
lOn-Chip Charge Pump Drive Circuitry
lDifferential Multiplexer
lConversion Data FIFO
lProgrammable/Auto Channel Sequencer
l2-Bit Output Latch
lSimple three-wire serial interface
—SPI™ and Microwire™ Compatible
—Schmitt Trigger on Serial Clock (SCLK)
lOutput Settles in One Conversion Cycle
l50/60 Hz ±3 Hz Simultaneous Rejection
lBuffered VREF with +5 V Input Capability
lSystem and Self-Calibration with R/W
Registers per Channel
lSingle +5 V Analog Supply
+3.0 V or +5 V Digital Supply
lPower Consumption: 5.5 mW
- 1.8 mW in 1 V, 2.5 V and 5 V input ranges
General Description
The 16-bit CS5521/23 are highly integrated ∆Σ A/D con-
verters which include an instrumentation amplifier, a PGA
(programmable gain amplifier), a multi-channel multiplexer,
digital filters, and self and system calibration circuitry.
The chips are designed to provide their own negative
supply which enables their on-chip instrumentation am-
plifiers to measure bipolar ground-referenced signals
less-than or equal to ±100 mV.
The digital filters provide programmable output update
rates of 1.88 Hz, 3.76 Hz, 7.51 Hz, 15 Hz, 30 Hz,
61.6 Hz, 84.5 Hz, and 101.1 Hz when operating from a
32 kHz crystal. The CS5521/23 are capable of producing
output update rates up to 303 Hz with a 100kHz clock.
The filters are designed to settle to full accuracy for the
selected output update rate within one conversion cycle.
When operated at word rates of 15 Hz or less, the digital
filters reject both 50 and 60 Hz line interference ±3Hz
simultaneously.
Low power, single conversion settling time, programma-
ble output rates, and the ability to handle negative input
signals make these single supply products ideal solu-
tions for isolated and non-isolated applications.
ORDERING INFORMATION
See page 33.
VD+DGND
Differential
4th order
delta-sigma
modulator
Digital Filter Calibration
Register
Calibration
µ
C
VA+
Control
Register
XIN XOUT
Programmable
Gain
AGND
CS
SCL
K
SDI
SDO
VREF-
CPD
NBV
X20
A0 A1
Calibration
Memory
VREF+
Latch
AIN1-
AIN1+
AIN2+
AIN2-
+
-
Output
Register
X1
X1
X1
MUX
CS5523
Shown
AIN3-
AIN3+
AIN4+
AIN4-
Clock
Gen.
MAR ‘99
DS317PP2

CS5521 CS5523
2DS317PP2
TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS ............................................................ 4
ANALOG CHARACTERISTICS...................................................................4
RMS NOISE.................................................................................................4
5 V DIGITAL CHARACTERISTICS ............................................................. 6
3 V DIGITAL CHARACTERISTICS ............................................................. 6
DYNAMIC CHARACTERISTICS.................................................................7
RECOMMENDED OPERATING CONDITIONS..........................................7
ABSOLUTE MAXIMUM RATINGS.............................................................. 7
SWITCHING CHARACTERISTICS.............................................................8
GENERAL DESCRIPTION ................................................................................10
Theory of Operation ..................................................................................10
System Initialization ..................................................................................12
Serial Port Overview .................................................................................12
Serial Port Interface ..................................................................................13
Serial Port Initialization .............................................................................13
Channel-Setup Registers ..........................................................................13
Conversion Protocol .................................................................................13
Calibration Protocol ..................................................................................19
Use of Pointers in Command Byte ............................................................20
Analog Input .............................................................................................21
Charge Pump Drive ..................................................................................23
Voltage Reference ....................................................................................24
Calibration .................................................................................................24
Self Calibration .........................................................................................25
System Calibration ....................................................................................25
Calibration Tips .........................................................................................27
Limitations in Calibration Range ...............................................................27
Analog Output Latch Pins .........................................................................28
Output Word Rate Selection .....................................................................28
Clock Generator ........................................................................................28
Digital Filter ...............................................................................................28
Output Coding ..........................................................................................28
Power Consumption .................................................................................29
PCB Layout ..............................................................................................30
PIN DESCRIPTIONS .........................................................................................31
Clock Generator ........................................................................................31
Control Pins and Serial Data I/O ...............................................................31
Measurement and Reference Inputs ........................................................32
Power Supply Connections .......................................................................32
SPECIFICATION DEFINITIONS ........................................................................33
ORDERING GUIDE ............................................................................................33
PACKAGE DESCRIPTIONS .............................................................................34
SPI™ is a trademark of Motorola Inc., Microwire™ is a trademark of National Semiconductor Corp.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance
product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts
to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice
and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this
information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no
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tem, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication
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Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners
which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

CS5521 CS5523
DS317PP2 3
TABLE OF FIGURES
CS5521/23 Configured to use on-chip charge pump to supply NBV. ................ 10
Charge Pump Drive Circuit for VD+ = 3 V. ......................................................... 11
Alternate NBV Circuits. ...................................................................................... 11
CS5521/23 Configured for ground-referenced Unipolar Signals. ....................... 11
CS5521/23 Configured for Single Supply Bridge Measurement. ....................... 12
Command and Data Word Timing. ..................................................................... 15
Multiplexer Configuration ................................................................................... 22
Input models for AIN+ and AIN- pins for each range. ........................................ 24
Input model for VREF+ and VREF- pins. ........................................................... 24
Self Calibration of Offset (Low Ranges). ............................................................ 26
Self Calibration of Offset (High Ranges). ........................................................... 26
Self Calibration of Gain (All Ranges). ................................................................ 26
System Calibration of Offset (Low Ranges). ...................................................... 26
System Calibration of Offset (High Ranges). ..................................................... 26
System Calibration of Gain (Low Ranges) ......................................................... 26
System Calibration of Gain (High Ranges). ....................................................... 26
Filter Response (Normalized to Output Word Rate = 1) .................................... 28

CS5521 CS5523
4DS317PP2
CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA= 25 °C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND,
NBV = -2.1 V, FCLK =32.768 kHz, OWR (Output Word Rate) = 15.0 Hz, Bipolar Mode, Input Range = ±100 mV;
See Notes 1 and 2.)
Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.
2. Specifications guaranteed by design, characterization, and/or test.
3.
Specification applies to the device only and does not include any effects by external parasitic thermocouples.
4. Drift over specified temperature range after calibration at power-up at 25 °C.
5. See the section of the data sheet which discusses input models.
RMS NOISE (Notes 6 and 7)
Notes: 6. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.
7. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.
8. For input ranges <100 mV and output rates >61.6 Hz 16.384 kHz chopping frequency is used.
Parameter Min Typ Max Unit
Accuracy
Resolution - - 16 Bits
Linearity Error - ±0.0015 ±0.003 %FS
Bipolar Offset (Note 3) - ±1±2LSB
16
Unipolar Offset (Note 3) - ±2±4LSB
16
Offset Drift (Notes 3 and 4) - 20 - nV/°C
Bipolar Gain Error - ±8±31 ppm
Unipolar Gain Error - ±16 ±62 ppm
Gain Drift (Note 4) - 1 3 ppm/°C
Voltage Reference Input
Range (VREF+) - (VREF-) 1 2.5 VA+ V
VREF+ (VREF-)+1 -VA+V
VREF- NBV - (VREF+)-1 V
Common Mode Rejection dc
50, 60 Hz - -110 130 - -dB dB
Input Capacitance - 16 - pF
CVF Current (Note 5) - 5.0 - nA
Output Rate
(Hz) -3 dB Filter Frequency Input Range, (Bipolar/Unipolar Mode) 25 mV 55 mV 100 mV 1 V 2.5 V 5 V
1.88 1.64 90 nV 148 nV 220 nV 1.8 µV 3.9 µV 7.8 µV
3.76 3.27 122 nV 182 nV 310 nV 2.6 µV 5.7 µV 11.3 µV
7.51 6.55 180 nV 267 nV 435 nV 3.7 µV 8.5 µV 18.1 µV
15.0 12.7 280 nV 440 nV 810 nV 5.7 µV 14 µV 28 µV
30.0 25.4 580 nV 1.1 µV 2.1 µV 18.2 µV 48 µV 96 µV
61.6 50.4 2.6 µV 4.9 µV 8.5 µV 92 µV 238 µV 390 µV
84.5 (Note 8) 70.7 11 µV 27 µV 43 µV 458 µV 1.1 mV 2.4 mV
101.1 (Note 8) 84.6 41 µV 72 µV 130 µV 1.2 mV 3.4 mV 6.7 mV

CS5521 CS5523
DS317PP2 5
ANALOG CHARACTERISTICS (Continued)
Notes: 9. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path.
10. Measured with Charge Pump Drive off.
11. All outputs unloaded. All input CMOS levels.
Parameter Min Typ Max Unit
Analog Input
Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode
NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
NBV = AGND Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
-0.150
NBV
1.85
0.0
-
-
-
-
0.950
VA+
2.65
VA+
V
V
V
V
Common Mode Rejection dc
50, 60 Hz - -120 120 - -dB dB
Input Capacitance - 10 - pF
CVF Current on AIN+ or AIN- (Note 5)
Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V - -100 10 300 -pA nA
System Calibration Specifications
Full Scale Calibration Range Bipolar/Unipolar Mode
25 mV
55 mV
100 mV
1 V
2.5 V
5 V
10
25
40
0.40
1.0
2.0
-
-
-
-
-
-
32.5
71.5
105
1.30
3.25
VA+
mV
mV
mV
V
V
V
Offset Calibration Range Bipolar/Unipolar Mode
25 mV
55 mV
100 mV (Note 9)
1 V
2.5 V
5 V
-
-
-
-
-
-
-
-
-
-
-
-
±12.5
±27.5
±50
±0.5
±1.25
±2.50
mV
mV
mV
V
V
V
Power Supplies
DC Power Supply Currents (Normal Mode) IA+
(Note 10) ID+
INBV
-
-
-
0.9
90
260
1.2
135
375
mA
µA
µA
Power Consumption Normal Mode (Note 11)
Standby
Sleep
-
-
-
5.5
1.2
500
7.5
-
-
mW
mW
µW
Power Supply Rejection dc Positive Supplies
dc NBV - -120 110 - -dB dB

CS5521 CS5523
6DS317PP2
5 V DIGITAL CHARACTERISTICS (TA= 25 °C; VA+, VD+ = 5 V ±5%; GND = 0;
See Notes 2 and 12.)
Notes: 12. All measurements performed under static conditions.
13. Iout = -100 µA unless stated otherwise. (VOH = 2.4 V @ Iout = -40 µA.)
3 V DIGITAL CHARACTERISTICS (TA= 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0;
See Notes 2 and 12.)
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
VIH 0.6 VD+
(VD+)-0.5
(VD+) - 0.45
-
-
-
-
-
-
V
V
V
Low-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
VIL -
-
-
-
-
-
0.8
1.5
0.6
V
V
V
High-Level Output Voltage
All Pins Except CPD and SDO (Note 13)
CPD, Iout = -4.0 mA
SDO, Iout = -5.0 mA
VOH (VA+) - 1.0
(VD+) - 1.0
(VD+) - 1.0
-
-
-
-
-
-
V
V
V
Low-Level Output Voltage
All Pins Except CPD and SDO, Iout = 1.6 mA
CPD, Iout = 2 mA
SDO, Iout = 5.0 mA
VOL -
-
-
-
-
-
0.4
0.4
0.4
V
V
V
Input Leakage Current Iin -±1±10µA
3-State Leakage Current IOZ --±10µA
Digital Output Pin Capacitance Cout -9-pF
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
VIH 0.6 VD+
(VD+)-0.5
(VD+) - 0.45
-
-
-
-
-
-
V
V
V
Low-Level Input Voltage All Pins Except XIN and SCLK
XIN
SCLK
VIL -
-
-
-
-
-
0.16 VD+
0.3
0.6
V
V
V
High-Level Output Voltage
All Pins Except CPD and SDO, Iout = -400 µA
CPD, Iout = -4.0 mA
SDO, Iout = -5.0 mA
VOH (VA+) - 0.3
(VD+) - 1.0
(VD+) - 1.0
-
-
-
-
-
-
V
V
V
Low-Level Output Voltage
All Pins Except CPD and SDO, Iout = 400 µA
CPD, Iout = 2 mA
SDO, Iout = 5.0 mA
VOL -
-
-
-
-
-
0.3
0.4
0.4
V
V
V
Input Leakage Current Iin -±1±10µA
3-State Leakage Current IOZ --±10µA
Digital Output Pin Capacitance Cout -9-pF

CS5521 CS5523
DS317PP2 7
DYNAMIC CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; See Note 14.)
Notes: 14. All voltages with respect to ground.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 14.)
Notes: 15. No pin should go more negative than NBV - 0.3 V.
16. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.
17. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.
18. Total power dissipation, including all input currents and output currents.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter Symbol Ratio Unit
Modulator Sampling Frequency fsXIN/4 Hz
Filter Settling Time to 1/2 LSB (Full Scale Step) ts1/fout s
Parameter Symbol Min Typ Max Unit
DC Power Supplies Positive Digital
Positive Analog VD+ VA+ 2.7 4.75 5.0 5.0 5.25 5.25 V V
Analog Reference Voltage (VREF+) - (VREF-) VRefdiff 1.0 2.5 VA+ V
Negative Bias Voltage NBV -1.8 -2.1 -2.5 V
Parameter Symbol Min Typ Max Unit
DC Power Supplies (Note 15)
Positive Digital
Positive Analog VD+ VA+ -0.3 -0.3 - -+6.0 +6.0 V V
Negative Bias Voltage Negative Potential NBV +0.3 -2.1 -3.0 V
Input Current, Any Pin Except Supplies (Note 16 and 17) IIN --±10mA
Output Current IOUT --±25mA
Power Dissipation (Note 18) PDN - - 500 mW
Analog Input Voltage VREF pins
AIN Pins VINR
VINA
NBV -0.3
NBV -0.3 - -(VA+) + 0.3 (VA+) + 0.3 V V
Digital Input Voltage VIND -0.3 - (VD+) + 0.3 V
Ambient Operating Temperature TA-40 - 85 °C
Storage Temperature Tstg -65 - 150 °C

CS5521 CS5523
8DS317PP2
SWITCHING CHARACTERISTICS (TA= 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;
Levels: Logic 0 = 0 V, Logic 1 = VD+; CL= 50 pF.)
Notes: 19. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 100 kHz can be used
for increased throughput.
20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
22. Applicable when SCLK is continuously running.
Specifications are subject to change without notice.
Parameter Symbol Min Typ Max Unit
Master Clock Frequency (Note 19)
External Clock or Internal Oscillator XIN 30 32.768 100 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 20)
Any Digital Input Except SCLK
SCLK
Any Digital Output
trise -
-
-
-
-
50
1.0
100
-
µs
µs
ns
Fall Times (Note 20)
Any Digital Input Except SCLK
SCLK
Any Digital Output
tfall -
-
-
-
-
50
1.0
100
-
µs
µs
ns
Start-up
Oscillator Start-up Time XTAL = 32.768 kHz (Note 21) tost -500-ms
Power-on Reset Period tpor - 2006 - XIN
cycles
Serial Port Timing
Serial Clock Frequency SCLK 0 - 2 MHz
SCLK Falling to CS Falling for continuous running SCLK
(Note 22) t0100 - - ns
Serial Clock Pulse Width High
Pulse Width Low t1
t2
250
250 - -- -ns ns
SDI Write Timing
CS Enable to Valid Latch Clock t350 - - ns
Data Set-up Time prior to SCLK rising t450 - - ns
Data Hold Time After SCLK Rising t5100 - - ns
SCLK Falling Prior to CS Disable t6100 - - ns
SDO Read Timing
CS to Data Valid t7--150ns
SCLK Falling to New Data Bit t8--150ns
CS Rising to SDO Hi-Z t9--150ns

CS5521 CS5523
DS317PP2 9
CS
SCLK
t
0
t
2
t
1
t
3
t
6
Continuous Running SCLK Timing (Not to Scale)
CS
SCLK
MSB MSB-1 LSBSDI
t
3
t
4
t
5
t
1
t
2
t
6
SDI Write Timing (Not to Scale)
CS
SCLK
MSB MSB-1 LSB
SDO
t
7
t
8
t
1
t
2
t
9
SDO Read Timing (Not to Scale)

CS5521 CS5523
10 DS317PP2
GENERAL DESCRIPTION
The CS5521/23 are 16-bit converters which in-
clude a chopper-stabilized instrumentation amplifi-
er, and an on-chip programmable gain amplifier.
They are optimized for measuring low-level unipo-
lar or bipolar signals in process control and medical
applications.
The CS5521/23 also include a fourth order delta-
sigma modulator, a calibration microcontroller,
eight digital filters used to select between eight out-
put update rates, a 2-bit analog latch, a multiplexer,
and a serial port.
The CS5521/23 include a CPD (Charge Pump
Drive) output (shown in Figure 1) which provides
a negative bias voltage to the on-chip instrumenta-
tion amplifier when used with a combination of ex-
ternal diodes and capacitors. This makes the
converters ideal for thermocouple temperature
measurements because the biasing scheme enables
the CS5521/23 to measure negative voltages with
respect to ground without the need for a negative
supply.
Theory of Operation
The CS5521/23 A/D converters are designed to op-
erate from a single +5 V analog supply with several
different input ranges. See the Analog Character-
istics section on page 3 for details.
Figure 1 illustrates the CS5521/23 connected to
generate their own negative bias supply using the
on-chip CPD (Charge Pump Drive). This enables
the CS5521/23 to measure ground referenced sig-
nals with magnitudes down to -100mV. Figure 2 il-
lustrates a charge pump circuit when the converters
are powered from a +3.0 V digital supply. Alterna-
tively, the negative bias supply can be generated
from a negative supply voltage or a resistive divid-
er as illustrated in Figure 3.
XOUT
VD+
VA+
VREF+
VREF-
DGNDNBV
AIN1+
SCLK
SDO
SDI
CS5521
XIN
CPD
CS
10 Ω
+5V
Analog
Supply
0.1
µ
F0.1
µ
F
20
19
3
1
AGND
2 14
11
10
15
12
8
9
13 5
Optional
Clock
Source
Serial
Data
Interface
7
32.768 ~ 100 kHz
2.5V
Up to ± 100 mV Input
AIN1-
4
10 k
Ω
0.1
µ
F
10
µ
F
0.03
µ
F
1N4148
1N4148
+
BAV199
18
AIN2+
17
AIN2-
16 A1
6
A0
Charge-pump network
for VD+ = 5V only and
XIN = 32.768 kHz.
Logic Outputs:
A0 - A1 Switch from
VA+ to AGND.
10 k Ω
301 Ω
499
Ω
+5V
V+
R
LM334
Absolute
Current
Reference V-
Cold Junction
BAT85
Figure 1. CS5521/23 Configured to use on-chip charge pump to supply NBV.

CS5521 CS5523
DS317PP2 11
Figure 4 illustrates the CS5521/23 connected to
measure ground referenced unipolar signals of a
positive polarity using the 1 V, 2.5 V, and 5V rang-
es on the converter. For the 25 mV, 55 mV, and 100
mV ranges the signal must have a common mode
near +2.5 V (NBV = 0V).
The CS5521/23 are optimized for the measurement
of thermocouple outputs, but are also well suited
for the measurement of ratiometric bridge trans-
ducer outputs. Figure 5 illustrates the CS5521/23
connected to measure the output of a ratiometric
differential bridge transducer while operating from
a single +5 V supply.
-5V
NBV
30.1K Ω
34.8K Ω
2N5087
or similar
-5V
2.1K Ω
2.0K Ω
NBV
+
10 µ F
10 µ F
+
BAT85 BAT85
Figure 2. Charge Pump Drive Circuit for VD+ = 3 V. Figure 3. Alternate NBV Circuits.
XOUT
VD+VA+
VREF+
VREF-
DGNDNBV
AIN1+
AIN1- SCLK
SDO
SDI
CS55 1
XIN
CPD
C
S
10
Ω
+5V
Analog
Supply 0.1
µ
F
0
.
1
µ
F
20
19
3
4
1AGND
214
11
10
15
12
8
9
135
Optional
Clock
Source
S
e
r
i
a
l
D
a
t
a
I
n
t
e
r
f
a
c
e
7
3
2
.
7
6
8
~
1
0
0
k
H
z
0 to +5V Input
18 AIN2+
17 AIN2-
16
A1
6A0
+
-
CM = 0 to VA+
Figure 4. CS5521/23 Configured for ground-referenced Unipolar Signals.

CS5521 CS5523
12 DS317PP2
System Initialization
When power to the CS5521/23 are applied, the
chips are held in a reset condition until the 32.768
kHz oscillator has started and a counter-timer
elapses. Due to the high Q of the 32.768 kHz crys-
tal, the oscillator takes 400-600 ms to start. The
counter-timer counts 2006 oscillator clock cycles
to make sure the oscillator is fully stable. During
this time-out period the serial port logic is reset and
the RV (Reset Valid) bit in the configuration regis-
ter is set to indicate that a valid reset occurred. Af-
ter a reset, the on-chip registers are initialized to the
following states and the converter is placed in the
command mode where it waits for a valid com-
mand.
Note: A system reset can be initiated at any time by writing a
logic 1 to the RS (Reset System) bit in the configuration reg-
ister. After a reset, the RV bit is set until the configuration
register is read. The user must then write a logic 0 to the RS
bit to take the part out of reset mode.
Serial Port Overview
The CS5521/23’s serial port includes a microcon-
troller which contains a command register, a con-
figuration register, and a gain and offset register for
each input channel. The serial port also includes a
programmable channel sequencer which can se-
quence up to 8 channels to be converted. The se-
quencer consists of channel-setup registers (CSRs)
which contain information about the modes used
when conversions are performed. To complement
the sequencer a conversion data FIFO (CDF, read
only) is included to store up to sixteen data conver-
sions. All registers except the 8-bit command reg-
ister are 24-bits in length. The conversion data
FIFO is just an array of 24-bit conversion data reg-
isters used to store conversion words until the FIFO
is read.
The serial port has two modes of operation: the
command mode and the data mode. After a system
initialization or reset, the serial port is initialized
into commandmode where it waits to receive a val-
id command (the first 8-bits into the serial port).
Tables 1 and 2 can be used to decode all valid com-
mands. Once a valid command is received, the byte
XOUT
VD+
VA+
VREF+
VREF-
DGNDNBV
AIN1+
AIN1-
S
C
L
K
S
D
O
S
D
I
CS5521
XIN
CPD
C
S
10
Ω
+5V
Analog
Supply 0.1
µ
F
0
.
1
µ
F
+
-
20
19
3
4
1AGND
214
11
10
15
12
8
9
135
Optiona
l
Clock
Source
S
e
r
i
a
l
D
a
t
a
I
n
t
e
r
f
a
c
e
7
3
2
.
7
6
8
~
1
0
0
k
H
z
18
AIN2+
17 AIN2-
16 A1
6A0
Figure 5. CS5521/23 Configured for Single Supply Bridge Measurement.
configuration register: 000040(H)
offset registers: 000000(H)
gain registers: 400000(H)
channel setup registers: 000000(H)

CS5521 CS5523
DS317PP2 13
instructs the converter to read from or write to a
register(s), perform a conversion or a calibration,
or perform a NULL command. If a command other
than start calibration or NULL command is re-
ceived, the serial port enters data mode. In data
mode, either the internal registers, the CSRs, or the
CDF (read only) are read from or written to. The
number of bytes transferred depends on the type of
register/FIFO being accessed and the way it is ac-
cessed. Once the data is transferred, the serial port
either remains in data mode or returns to the com-
mand mode. The mode which is entered depends
on the status of the loop (LP), the MC (multiple
conversion), and the RC (read convert) bits in the
configuration register. More information concern-
ing the LP bit is provided in the Conversion/Cali-
bration Protocol section. Note that SDO will fall to
logic 0 anytime a calibration or conversion is com-
pleted.
Serial Port Interface
The CS5521/23’s serial interface consists of four
control lines: CS, SCLK, SDI, SDO.
CS, Chip Select, is the control line which enables
access to the serial port. If the CS pin is tied low,
the port can function as a three wire interface.
SCLK, Serial Clock, is the serial bit-clock which
controls the shifting of data to or from the ADC’s
serial port. The CS pin must be held low (logic 0)
before SCLK transitions can be recognized by the
port logic.
SDI, Serial Data In, is the data signal used to trans-
fer data to the converters.
SDO, Serial Data Out, is the data signal used to
transfer output data from the converters. The SDO
output will be held at high impedance any time CS
is at logic 1. Figure 6 illustrates the serial sequence
necessary to write to, or read from the serial port’s
registers.
To accommodate optoisolators SCLK is designed
with a Schmitt-trigger input to allow an optoisola-
tor with slower rise and fall times to directly drive
the pin. Additionally, SDO is capable of sinking or
sourcing up to 5 mA to directly drive an optoisola-
tor LED. SDO will have less than a 400 mV loss in
the drive voltage when sinking or sourcing 5 mA.
Serial Port Initialization
The serial port is initialized to the command mode
whenever a power-on reset is performed inside the
converter, or when the user transmits the port ini-
tialization sequence. The port initialization se-
quence involves clocking 15 bytes of all 1's,
followed by one byte with the contents ‘11111110’.
This sequence places the chip into command mode
where it awaits a valid command.
Channel-Setup Registers
Table 3 depicts the channel-setup registers (CSRs).
The CS5521 has two CSRs and the CS5523 has four
CSRs. Each CSR contains two logical channels
which are programmed by the user to contain data
conversion information such as: 1) state of the out-
put latch pins, 2) output word rate, 3) gain range, 4)
polarity, and 5) the address of a physical input chan-
nel to be converted. Note that any physical input
channel can be represented in more than one logical
channel with different output rates, gain ranges, and
conversion modes. Once programmed the CSRs act
as a sequencer and determine the order in which con-
versions are performed. To program the CSRs
twelve bits are needed for each logical channel. For
example, to configure CSR#2 in the CS5521,bits 23
to 12 contain information on the third logical chan-
nel and bits 11 to 0 contain information on the fourth
logical channel. While reading/writing CSRs, only
an even number of logical channels are accessed.
The depth bits in the configuration register can only
be: 001, 011, 101, 111 when accessing CSRs.
Conversion Protocol
To acquire single or multiple conversion(s) a com-
mand byte is issued with its MSB=1 and CC2-CC0
= ‘000’. The type of conversion(s) performed and

CS5521 CS5523
14 DS317PP2
C
omman
d
Reg
i
ster
D7(MSB)D6D5D4D3D2D1D0
CB NU CSB1 CSB0 R/W RSB2 RSB1 RSB0
BIT NAME VALUE FUNCTION
D7 Command Bit, CB 0
1Must be logic 0 for these commands. See Table 2.
D6 Not Used, NU 0 Must always be logic zero.
D5-D4 Channel Select Bits,
CSB1-CSB0 00 .
.
11
CSB1-CSB0 provide the address of one of the four physical
channels. These bits are used to access the calibration regis-
ters associated with respective channels.
Note: These bits are ignored when reading the data register.
D3 Read/Write, R/W 0
1Write to selected register. Read from selected register.
D2-D0 Register Select Bit,
RSB2-RSB0 000 001
010
011
100
101
110
111
Reserved
Offset Register
Gain Register
Configuration Register
Conversion Data FIFO (read only)
Channel Set-up Registers
- register is 48-bits long for CS5521
- register is 96-bits long for CS5523
Reserved
Reserved
Table 1. Command-Set with MSB=0
D7(MSB)D6D5D4D3D2D1D0
CB NU CPB2 CPB1 CPB0 CC2 CC1 CC0
BIT NAME VALUE FUNCTION
D7 Command Bit, CB 0
1See Table 1. Must be logic 1 for these commands.
D6 Not Used, NU 0 Must always be logic zero.
D5-D3 Channel Pointer Bits,
CPB2-CPB0 000 .
.
.
111
These bits are used as pointers to the logical channels.
Note: The MC bit, must be logic 0 for these bits to take effect.
When MC = 1, these bits are ignored. The LP, MC, and RC
bits in the configuration register are ignored during calibra-
tion.
D2-D0 Conversion/Calibration
Bits, CC2-CC0 000 001
010
011
100
101
110
111
Normal Conversion
Self-Offset Calibration
Self-Gain Calibration
Reserved
Reserved
System-Offset Calibration
System-Gain Calibration
Reserved
Table 2. Command-Set with MSB=1

CS5521 CS5523
DS317PP2 15
Command Time
8 SCLKs Data Time 24 SCLKs
Write Cycle
CS
SCLK
SDI
MSB LSB
Command Time
8 SCLKs
CS
SCLK
SDI
Data Time 24 SCLKs
Read Cycle
SDO
MSB LSB
Command Time
8 SCLKs
8 SCLKs Clear SDO Flag
SDO
SCLK
SDI
Data Time
24 SCLKs
MSB LSB
* td = XIN/OWR clock cycles for each conversion except the
first conversion which will take XIN/OWR + 7 clock cycles
XIN/OWR
Clock Cycles
t *
d
Figure 6. Command and Data Word Timing.

CS5521 CS5523
16 DS317PP2
Channel-Setup Registers
* R indicates the bit value after the part is reset
CSR (Channel-Setup Register) CSR
#1 LC (Log. Channel) 1
Bits <47:36> LC 2 Bits <35:24> #1 LC 1 Bits <95:84> LC 2 Bits <83:72>
#2 LC 3
Bits <23:12> LC 4 Bits <11:0> #4 LC 7
Bits <23:12> LC 8 Bits <11:0>
CS5521 CS5523
D23(MSB) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
A1 A0 NU CS1 CS0 WR2 WR1 WR0 G2 G1 G0 U/B
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A1 A0 NU CS1 CS0 WR2 WR1 WR0 G2 G1 G0 U/B
BIT NAME VALUE FUNCTION
D23/D11-
D22/D10 Latch Outputs, A1-A0 00 *R Latch Output Pins A1-A0 mimic D23/D11-D22/D10 register bits.
D21/D9 Not Used, NU 0 R Must always be logic zero.
D20/D8-
D19/D7 Channel Select, CS1- CS0 00 01
10
11
R Select physical channel 1.
Select physical channel 2.
Select physical channel 3.
Select physical channel 4.
D18/D6-
D16/D4 Word Rate, WR2-WR0 000 001
010
011
100
101
110
111
R 15.0 Hz (2180 XIN cycles).
30.0 Hz (1092 XIN cycles).
61.6 Hz (532 XIN cycles).
84.5 Hz (388 XIN cycles).
101.1 Hz (324 XIN cycles).
1.88 Hz (17444 XIN cycles).
3.76 Hz (8724 XIN cycles).
7.51 Hz (4364 XIN cycles).
D15/D3-
D13/D1 Gain Bits, G2-G0 000 001
010
011
100
101
110
111
R 100 mV (assumes VREF Differential = 2.5 V)
55 mV
25 mV
1.0 V
5.0 V
2.5 V
Not used.
Not used.
D12/D0 Unipolar/Bipolar, U/B 0
1R Bipolar measurement mode. Unipolar measurement mode.
Table 3. Channel-Setup Registers

CS5521 CS5523
DS317PP2 17
C
on
fi
gurat
i
on Reg
i
ster
* R indicates the bit value after the part is reset
D23(MSB) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
NU NU CFS1 CFS0 NU MC LP RC NU DP2 DP1 DP0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PSS PD PS/R NU RS RV OD OF NU NU NU NU
BIT NAME VALUE FUNCTION
D23-D22 Not Used, NU 00 R* Must always be logic 0.
D21-D20 Chop Frequency Select,
CFS1-CFS0 00 01
10
11
R 256 Hz Amplifier chop frequency.
4,096 Hz Amplifier chop frequency.
16,384 Hz Amplifier chop frequency.
1,024 Hz Amplifier chop frequency.
D19 Not Used, NU 0 R Must always be logic 0.
D18 Multiple Conversion, MC 0
1R Perform single channel conversions. MC bit is ignored during calibrations. Perform multiple conversions on logical channels in the channel-setup
register by issuing only one command with MSB = 1.
D17 Loop, LP 0
1RDon’t loop. LP bit is ignored during calibrations. The conversions on the single channel (MC = 0) or multiple channels (MC
= 1) are continuously performed.
D16 Read Convert, RC 0
1R Don’t wait for user to finish reading data before starting new conversions. The RC bit is used in conjunction with the LP bit when the LP bit is set to
logic 1. If LP = 0, the RC bit is ignored. If LP = 1, the ADC waits for user to
read data conversion(s) before converting again. The RC bit is ignored
during calibrations. Refer to Calibration Protocol for details.
D15 Not Used, NU 0 R Must always be logic 0.
D14-D12 Depth Pointer, DP2-DP0 000
.
.
111
R When writing or reading the CSRs, these bits (DP2-DP0) determine the
number of CSR’s to be accessed. They are also used to determine how
many logical channels are converted when MC=1 and a command byte
with its MSB = 1 is issued. Note that the CS5521 has two CSRs and the
CS5523 has four CSRs.
D11 Power Save Select, PSS 0
1R Standby Mode (Oscillator active, allows quick power-up). Sleep Mode (Oscillator inactive).
D10 Pump Disable, PD 0
1R Charge Pump Enabled. For PD = 1, the CPD pin goes to a Hi-Z output state.
D9 Power Save/Run, PS/R 0
1RRun. Power Save.
D8 Not Used, NU 0 R Must always be logic 0.
D7 Reset System, RS 0
1R Normal Operation. Activate a Reset cycle. To return to Normal Operation write bit to zero.
D6 Reset Valid, RV 0
1R
No reset has occurred or bit has been cleared (read only).
Bit is set after a Valid Reset has occurred. (Cleared when read.)
D5 Oscillation Detect, OD 0
1R Bit is clear when an oscillation condition has not occurred (read only). Bit is set when an oscillatory condition is detected in the modulator.
D4 Overrange Flag, OF 0
1R Bit is clear when an overrange condition has not occurred (read only). Bit is set when input signal is more positive than the positive full scale,
more negative than zero (unipolar mode), or when the input is more neg-
ative then the negative full scale (bipolar mode).
D3-D0 Not Used, NU 0000 R Must always be logic 0.
Table 4. Configuration Register

CS5521 CS5523
18 DS317PP2
the way to access the resulting data is determined
by the MC (multiple conversion), the LP (loop),
and the RC (read convert) bits in the configuration
register. MC’s, LP’s, and RC’s functional descrip-
tions follow. The other bits in the configuration
register are detailed in Table 4.
MC = 0 LP = 0 RC = X
Based on the information provided in the channel-
setup registers (CSRs), a single conversion is per-
formed on the physical channel referenced by the
logical channel. The command byte contains the
pointer address of the logical channel to be used
during the conversion embedded in it. The serial
port enters data mode as soon as the 8-bit command
byte to start a conversion is issued. The port re-
mains in data mode during conversion. Upon the
completion of the conversion, SDO falls to logic 0.
Thirty-two SCLKs are needed to acquire the con-
version. The first 8 SCLKs are used to clear the
SDO flag. The last 24 are needed to read the con-
version result. After reading the data, the serial port
returns to the command mode, where it waits for a
new command to be issued.
MC = 0 LP = 1 RC = 0
Based on information contained in the CSRs, a sin-
gle conversion is repeatedly performed on the
physical channel referenced by the logical channel.
The command byte contains the pointer address of
the logical channel to be used during conversion.
Once a conversion is complete, SDO falls to indi-
cate that a conversion is ready. Thirty-two SCLKs
are needed to acquire the conversion (which must
be acquired within a certain window, refer to Fig-
ure 6). The first 8 SCLKs are used to clear the SDO
flag. The next 24 are needed to read the conversion
result. If ‘00000000’ is provided to SDI during the
first 8 SCLKs when the SDO flag is cleared, the
converter remains in this conversion mode and
continues to convert the selected channel. While in
this mode, the user may choose to acquire only the
conversions required for his application as SDO
rises and falls to indicate the availability of a new
conversion. To exit this conversion mode the user
must provide ‘11111111’ to the SDI pin during the
first 8 SCLKs. If the user decidesto exit, 24 SCLKs
are required to clock out the last conversion before
the converter will return to the command mode.
MC = 0 LP = 1 RC = 1
Based on information provided in the CSRs, a sin-
gle conversion is performed repeatedly on the
physical channel referenced by the logical channel.
The command byte contains the pointer address of
the logical channel to be used during the conver-
sion embedded in it. After a conversion cycle is
complete, SDO falls and the serial port is placed in
the data mode where it will remain until the conver-
sion data is read. If the user doesn’t read the con-
version word the converter stops performing new
conversions and SDO will remain low until the
conversion data is acquired. To acquire the conver-
sion data thirty-two SCLKs are needed. The first 8
SCLKs are used to clear the SDO flag. The next 24
are needed to read the conversion result. If
‘00000000’ is provided to SDI during the first 8
SCLKs to clear the SDO flag, a new conversion cy-
cle will be started after the conversion data is read.
To exit this conversion mode and return to the com-
mand mode, the user must provide ‘11111111’ to
the SDI during the first 8 SCLKs. A final 24
SCLKs are required to clock out the last conversion
data.
MC = 1 LP = 0 RC = X
Based on information provided in the CSRs, multi-
ple conversions are performed once on the physical
channels referenced by the logical channels of the
CSRs. The first two conversions are based on the
information in the channel-setup register (CSR) #1
(logical channels one and two); the third and fourth
conversions are based on information in the CSR
#2 (logical channels three and four); and so on up
to 8 conversions when the CS5523 is used. The
depth (DP2-DP0) information bits in the configura-

CS5521 CS5523
DS317PP2 19
tion register determine how many conversions are
performed and hence must be initialized before this
conversion mode is entered. Upon completion of
the conversions, SDO falls to indicate that the con-
version data set is ready to be read. To read thecon-
versions from the conversion data FIFO, the user
must first issue 8 SCLKs to clear the SDO flag. To
read the conversions, the user must then supply
24x(N) SCLKs. N is defined here as the number
of logical channels being converted which is the
decimal equivalent of depth + 1. For example, if
DP2-DP0 = ‘010’, N = (2+1) = 3. To return to the
command mode, the user must read all the conver-
sion data from the FIFO because the serial port re-
mains in data mode during the conversions and
during the read of the data. Whether ‘00000000’ or
‘11111111’ is provided to the SDI during the 8
SCLKs needed to clear the SDO flag, the serial port
returns to the command mode after the conversion
data FIFO is read.
MC = 1 LP = 1 RC = 0
Based on information provided in the CSRs, multi-
ple conversions are repeatedly performed on the
physical channels referenced by the logical chan-
nels of the CSRs. This conversion mode is similar
to the conversion mode when MC=1, LP=0, and
RC=X. Once a conversion data set is converted the
conversions are stored in the conversion data FIFO.
The only exception is that the converter then re-
turns to the top of the CSRs (i.e. to logical channel
one of CSR #1) and repeats. As before, SDO falls
to indicate when a data set is compete. Once SDO
falls, the user has three options: 1) exit after reading
the conversion data FIFO; this is accomplished by
providing SDI ‘11111111’ during the first 8
SCLKS and then giving 24xN more SCLKs to ac-
quire the conversion data; 2) provide no SCLKs
and remain in this mode without reading the data;
in this case, SDO rises and falls once a new set of
conversions is complete to indicate that a new set
of data is ready to acquire; or 3) read the conversion
data FIFO and remain in this mode; this is accom-
plished by providing SDI with ‘00000000’ during
the first 8 SCLKs and then giving 24xN more
SCLKs to read the conversion data; the user must
finish reading the FIFO before the first logical
channel of CSR #1 finishes a new conversion.
MC = 1 LP = 1 RC = 1
Based on information provided in the CSRs, multi-
ple conversions are performed repeatedly on the
logical channel of the CSR. This mode is similar to
the conversion mode when MC=1, LP=1, and
RC=0. The only exception is that the converter
stops and waits for the conversion data FIFO to be
emptied before new conversions are started. As be-
fore SDO falls when a data set is complete. Once
SDO falls, the user has two options: 1) exit after
emptying the FIFO; this is accomplished by pro-
viding SDI ‘11111111’ during the first 8 SCLKs
and then giving 24xN more SCLKs to read the con-
version data; or 2) empty the conversion data FIFO
and remain in this mode; this is accomplished by
providing SDI with ‘00000000’ during the first 8
SCLKs and then giving 24xN more SCLKs to read
the conversion data. After the FIFO is emptied, the
converter returns to the top of the CSRs (i.e. to log-
ical channel one of CSR#1) and repeats.
Calibration Protocol
To perform a calibration the user must send a com-
mand byte with its MSB=1, its pointer bits (CPB2-
CPB0) set to address the desired logical channel to
be calibrated, and the appropriate calibration bits
(CC2-CC0) set to choose the type of calibration to
be performed. Proper calibration assumes that the
CSRs have been previously initialized because the
information concerning the physical channel, its
filter rate, gain range, and polarity, comes from the
channel-setup register being addressed by the
pointer bits in the command byte.
Once the CSRs are initialized all future calibrations
can be performed with one command byte. Once a

CS5521 CS5523
20 DS317PP2
calibration cycle is complete SDO falls and the re-
sults are stored in either the gain or offset register
for the physical channel being calibrated. Note that
if additional calibrations are performed on the same
physical channel referenced by a different logical
channel with different filter rates, gain ranges, or
conversion modes, the last calibration results will
replace the effects from the previous calibration as
only one offset and gain register is available per
physical channel. One final note is that only one
calibration is performed with each command byte.
To calibrate all the channels additional calibration
commands are necessary.
Use of Pointers in Command Byte
Any time a calibration command is issued (CB=1
and proper CC2-CC0 bits set) or any time a normal
conversion command is issued (CB=1,
CC2=CC1=CC0=0, MC=0), the bits D5-D3 in the
command byte are used as pointers to address one
of the logical channels in the channel-setup regis-
ters (CSRs). Table 5 details the pointer the bits ad-
dress. Note that for the CS5523, D5-D3 can only be
000 - 111 (8 logical channels). For the CS5521,
D5-D3 can only be 000 - 011 (4 logical channels).
Five example situations that a user might encounter
when acquiring a conversion or calibrating the con-
verter follow. These examples assume that the user
is using a CS5523 (8 logical channels) and that its
CSRs are programmed with the following physical
channel order: 4, 1, 4, 2, 4, 3, 4, 1.
Example 1: The configuration register has the fol-
lowing bits as shown: DP2-DP0 = ‘101’, MC = 1,
LP = 1, RC = 0. The command byte issued is
‘1XXXX000’. These settings instruct the converter
to repeatedly perform multiple single conversions
on six logical channels. The order in which the
channels are converted is: 4, 1, 4, 2, 4, 3. SDO falls
after physical channel 3 is converted. To acquire
the 6 conversions 8 SCLKs with SDI = 0 are re-
quired to clear the SD0 flag. Then 144 more
SCLKs are required to read the conversion data
from the FIFO. The order in which the data is pro-
vided is the same as the order in which the channels
are converted. The first 3 bytes of data correspond
to the first logical channel which in this example is
physical channel 4; the next 3 bytes of data corre-
spond to the second logical channel which in this
example is physical channel 1; and, the last 3 bytes
of data corresponds to 6th logical channel which
here is physical channel 3. Since the logical chan-
nels are converted in the background, while the
data is being read, the user must finish reading the
conversion data FIFO before it is updated with new
conversions. To exit this conversion mode the user
must provide ‘11111111’ to SDI during the first 8
SCLKs. If a byte of 1’s is provided, the serial port
returns to the command mode only after the con-
version data FIFO is emptied (in this case 6 conver-
sions are acquired). Note that in this example
physical channel 4 is converted three times. Each
conversion could be with the same or different fil-
ter rates depending on the setting of logical chan-
nels 1, 3, and 5. Note that there is only one offset
and one gain register per physical channel. There-
fore, any physical channel can only be calibrated
for the gain range selected during calibration. Spec-
ifying a different gain range in the logical channel
setting than the range that was calibrated will result
in a gain error.
CPB2-CPB0 CSR Address Logical Channel
000 CSR #1 1st
001 CSR #1 2nd
010 CSR #2 3rd
011 CSR #2 4th
100 CSR #3 5th
101 CSR #3 6th
110 CSR#4 7th
111 CSR #4 8th
Table 5. Command Byte Pointer Table