Curtiss-Wright PMC-605 User manual

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Document Number:
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Curtiss-Wright Controls Embedded Computing
333 Palladium Drive
Ottawa, Ontario, Canada
K2V 1A6
[phone]
OUTREACH PCI/PMC
EXPANSION SYSTEM
USER’SMANUAL
809524
D
February 2009
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OUTREACH PCI/PMC EXPANSION SYSTEM USER’SMANUAL CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
II 809524 VERSION DFEBRUARY 2009
REVISION HISTORY
Rev By Date Description
1 JL June 2000 First engineering release.
- JL June 2000 Production release.
Updated Appendix B to reflect modified PCI-P0 backplane pins.
Changed cable requirements in Appendix A as product now uses standard base-
card cables.
Changed title of document to reflect new tabset.
Added J1 JTAG connector information in Chapter 2.
A JP November 2001 Updated Chapter 3 to reflect modified PCI-P0 backplane pins.
Changed title of document to reflect new OUTREACH system name.
B JP June 2002 Improved the explanation on page 1-3 of JTAG support for the CPLD on the
PMC-605.
Clarified statement on page 1-8 to indicate that when the bus is parked, it is parked
on the System Slot.
Changed description of PCI System Reset (RST#) signal on page 2-3 to remove
dependence on the Busmode1 signal.
Removed the Clock Mask section on page 2-4, since the clock signal will now
always be present on the PMC sites (dependence on the Busmode1 signal has
been removed), regardless if a PMC module is installed.
Updated Table 2.6 to reflect pinout changes (signals on P0 connector pins P0-A4
and P0-C4 have been swapped) that were introduced via ECO number
500000000673. This ECO allows smart PMC modules installed on the SVME/DMV-
210 to perform DMA cycles back to the host card.
Added note on page 3-2 that summarizes which E jumpers on the BPL-605-002 and
BPL-605-003 are reserved.
Improved Figure 3.2, Figure 3.3, and Figure 3.4 to indicate the correct orientation of
the 2 or 3 Slot Development Backplanes and the location of the E-jumper straps.
Corrected errors in Table 3.7 (specifically the descriptions of “Clock Source”,
“Request Line”, and “Grant Line”).
Corrected error in “Configure Master’s Primary BARs” on page 4-9. The Command
Register is located at 0x44, not 0x40 as was previously shown.
Improved Figure A.3 to clarify how the BPL-605-002 and BPL-605-003 Develop-
ment Backplane modules need to be oriented for correct operation.
C JP June 2004 Updated to correct SVME/DMV-210 P0 pinout table (see Table 2.6 on page 2-11).
Updated to correct SVME/DMV-210 P2 pinout table (see Table 2.8 on page 2-13).
D JP February 2009 Updated to address CR#26124. See “Install PMC-605 on Basecard” on page A-3 for
corrected cross reference to document number 808335.
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CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
809524 VERSION DFEBRUARY 2009 III
COPYRIGHT NOTICE
The information in this document is subject to change without notice and should not be
construed as a commitment by Curtiss-Wright Controls, Inc. While reasonable precautions
have been taken, Curtiss-Wright Controls, Inc. assumes no responsibility for any errors that
may appear in this document.
No part of this document may be copied or reproduced without the prior written consent of
Curtiss-Wright Controls, Inc.
The proprietary information contained in this document must not be disclosed to others for
any purpose, nor used for manufacturing purposes, without written permission of Curtiss-
Wright Controls, Inc. The acceptance of this document will be construed as an acceptance of
the foregoing condition.
Copyright © 2009, Curtiss-Wright Controls, Inc. All rights reserved.
TRADEMARKS
PowerPC is a trademark of International Business Machines Corporation.
VxWorks is a registered trademark of Wind River Systems, Inc.
Outreach is a trademark of CWCEC Systems Inc.
All other brand and product names are trademarks or registered trademarks of their
respective owners.
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OUTREACH PCI/PMC EXPANSION SYSTEM USER’SMANUAL CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
IV 809524 VERSION DFEBRUARY 2009
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CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
809524 REVISION DFEBRUARY 2009 V
TABLE OF CONTENTS
1. PMC-605 PCI-P0 Bridge Module................................................................................ 1-1
General Description ..............................................................................................................1-1
Summary of Features......................................................................................................1-3
PCI-P0 Bridge Description......................................................................................................1-4
21554 PCI-to-PCI-Bridge Controller...................................................................................1-4
Primary and Secondary PCI Buses.....................................................................................1-4
PCI-P0 Bus Arbitration.....................................................................................................1-5
PCI-P0 Bus Clock ............................................................................................................1-6
PCI-P0 System Slot Termination .......................................................................................1-8
Interrupts......................................................................................................................1-8
Reset ............................................................................................................................1-9
Serial EEPROM..............................................................................................................1-10
LED.............................................................................................................................1-10
Registers .....................................................................................................................1-10
Physical, Electrical, and Environmental Characteristics.............................................................1-11
Dimensions..................................................................................................................1-11
Mating Connectors ........................................................................................................1-11
Electrical Characteristics ................................................................................................1-12
Environmental Characteristics.........................................................................................1-12
Connector Pin Assignments..................................................................................................1-13
Connector Locations......................................................................................................1-13
Pn1/Pn2 Pin Assignments...............................................................................................1-14
Pn3 Pin Assignments .....................................................................................................1-15
Pn4 Pin Assignments .....................................................................................................1-16
J1 Test JTAG Port..........................................................................................................1-17
2. SVME/DMV-210 Carrier Card...................................................................................... 2-1
General Description ..............................................................................................................2-1
Summary of Features......................................................................................................2-2
PCI-P0 Bridge Description......................................................................................................2-3
Configuration .................................................................................................................2-3
PCI Signal Environment ...................................................................................................2-3
PCI System Reset (RST#) ................................................................................................2-3
PCI Interrupts ................................................................................................................2-3
PCI JTAG Test Signals......................................................................................................2-4
PMC Bus Mode Signals.....................................................................................................2-4
Physical, Electrical, and environmental Characteristics...............................................................2-5
Dimensions....................................................................................................................2-5
Mating Connectors ..........................................................................................................2-5
Electrical Characteristics ..................................................................................................2-6
Environmental Characteristics...........................................................................................2-6
Connector Pin Assignments....................................................................................................2-7
PMC Site 1: Jn1 and Jn2 Connectors..................................................................................2-7
PMC Site 1: Jn3 and Jn4 Connectors..................................................................................2-8
PMC Site 2: Jn1 and Jn2 Connectors..................................................................................2-9
PMC Site 2: Jn3 and Jn4 Connectors................................................................................2-10
VME P0 Connector Pin Assignments.................................................................................2-11
VME P1 Connector Pin Assignments.................................................................................2-12
VME P2 Connector Pin Assignments.................................................................................2-13
3. PCI-P0 Development Backplane................................................................................ 3-1
General Description ..............................................................................................................3-1
Backplane Jumper Configurations ...........................................................................................3-2
Bus Arbiter Jumper Settings.............................................................................................3-2
PCI Bus Clock Jumper Settings .........................................................................................3-4
System Slot Termination Jumper Settings ..........................................................................3-5
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OUTREACH PCI/PMC EXPANSION SYSTEM USER’SMANUAL CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
VI 809524 REVISION DFEBRUARY 2009
PCI-P0 Backplane Pin Assignments......................................................................................... 3-7
2 Slot Backplane Configuration Pins .................................................................................. 3-7
2 Slot Backplane System Slot 0 Pin Assignments ................................................................ 3-8
2 Slot Backplane Peripheral Slot 1 Pin Assignments............................................................. 3-9
3 Slot Backplane Configuration Pins .................................................................................3-10
3 Slot Backplane System Slot 0 Pin Assignments ...............................................................3-11
3 Slot Backplane Peripheral Slot 1 Pin Assignments............................................................3-12
3 Slot Backplane Peripheral Slot 2 Pin Assignments............................................................3-13
4. System Integration......................................................................................................4-1
Configuration of the PCI-P0 Bus............................................................................................. 4-1
PMC-605 Non-Transparent PCI-PCI Bridging....................................................................... 4-1
SVME/DMV-210 Transparent PCI-PCI Bridging.................................................................... 4-1
PMC-605 Terminology..................................................................................................... 4-2
Example: Transferring Data Between Two SBCs ....................................................................... 4-3
Serial EEPROM Configuration............................................................................................ 4-3
SVME/DMV-179 GPM Map Command With PMC-605 Installed ............................................... 4-5
Base Address Register Initialization................................................................................... 4-7
Primary BAR Configuration............................................................................................... 4-8
Translated Base Register Configuration.............................................................................. 4-9
Address Map for Local PCI and P0 Buses...........................................................................4-11
Transferring Data ..........................................................................................................4-11
PCI-P0 Configuration Space Addressing..................................................................................4-12
Addressing Example.......................................................................................................4-12
A. Installation Instructions............................................................................................. A-1
Installation Overview............................................................................................................ A-1
Unpack Cards ................................................................................................................ A-2
Configure Cards and PCI-P0 Development Backplane........................................................... A-2
Install PMC-605 on Basecard............................................................................................ A-3
Insert Cards in Chassis.................................................................................................... A-3
Attach the PCI-P0 Development Backplane......................................................................... A-4
Connect Basecard to Terminal.......................................................................................... A-5
Apply Power .................................................................................................................. A-5
Display Initial Screen Message ......................................................................................... A-5
Install BSP.....................................................................................................................A-6
Index ...................................................................................................................................I-1
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CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
809524 REVISION DFEBRUARY 2009 VII
LIST OF FIGURES
Figure 1.1: Sample Application of PMC-605 PCI-P0 Bridge Module...............................................1-1
Figure 1.2: PMC-605 Functional Block Diagram ........................................................................1-2
Figure 1.3: Primary and Secondary PCI Buses..........................................................................1-4
Figure 1.4: Bus Arbitration and Signal Direction .......................................................................1-5
Figure 1.5: PCI-P0 Clock Source Configurations........................................................................1-7
Figure 1.6: Inter-Card Interrupt Mechanism.............................................................................1-9
Figure 1.7: PMC-605 Physical Layout ....................................................................................1-11
Figure 1.8: Connector Locations...........................................................................................1-13
Figure 1.9: Location of PMC-605 on a SVME/DMV-179.............................................................1-17
Figure 2.1: Sample Application of SVME/DMV-210 Carrier Card ..................................................2-1
Figure 2.2: SVME/DMV-210 Block Diagram..............................................................................2-2
Figure 2.3: SVME/DMV-210 Physical Layout.............................................................................2-5
Figure 3.1: PCI-P0 Development Backplane Slot Locations (3 Slot Version) ..................................3-1
Figure 3.2: Bus Arbiter Jumper Locations ................................................................................3-3
Figure 3.3: Clock Source Jumper Locations..............................................................................3-4
Figure 3.4: Bus Termination Jumper Locations .........................................................................3-6
Figure 4.1: Primary and Secondary PCI Buses..........................................................................4-2
Figure 4.2: Example System..................................................................................................4-3
Figure 4.3: Local PCI Address Map after BAR Configuration........................................................4-7
Figure 4.4: Example of Address Map based on BAR Requirements...............................................4-8
Figure 4.5: Master-Slave Memory Mappings...........................................................................4-11
Figure 4.6: Type 0 Configuration Cycle Example.....................................................................4-13
Figure 4.7: Type 1 Configuration Cycle Example.....................................................................4-13
Figure A.1: Outreach PCI/PMC Expansion System .....................................................................A-1
Figure A.2: PMC Site Location ................................................................................................A-3
Figure A.3: PCI-P0 Backplane Installation ................................................................................A-4
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OUTREACH PCI/PMC EXPANSION SYSTEM USER’SMANUAL CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
VIII 809524 REVISION DFEBRUARY 2009
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CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
809524 REVISION DFEBRUARY 2009 IX
LIST OF TABLES
Table 1.1: Clock Source Configurations ..................................................................................1-7
Table 1.2: Local Control and Status Register (LCSR)..............................................................1-10
Table 1.3: Environmental Specification Limits and Ruggedization Levels ...................................1-12
Table 1.4: Pn1/Pn2 Pin Assignments....................................................................................1-14
Table 1.5: Pn3 Pin Assignments ..........................................................................................1-15
Table 1.6: Pn4 Pin Assignments ..........................................................................................1-16
Table 1.7: J1 Test JTAG Port Pin Assignments.......................................................................1-17
Table 1.8: Sample SVME/DMV-179 P0 Connector Pin Assignments...........................................1-18
Table 2.1: Environmental Specification Limits and Ruggedization Levels .....................................2-6
Table 2.2: PMC Site 1: Pin Assignments (Jn1 and Jn2) .............................................................2-7
Table 2.3: PMC Site 1: Pin Assignments (Jn3 and Jn4) .............................................................2-8
Table 2.4: PMC Site 2: Pin Assignments (Jn1 and Jn2) .............................................................2-9
Table 2.5: PMC Site 2: Pin Assignments (Jn3 and Jn4) ...........................................................2-10
Table 2.6: VME P0 Connector Pin Assignments......................................................................2-11
Table 2.7: Pin Assignments for VME P1 Connector .................................................................2-12
Table 2.8: Pin Assignments for VME P2 Connector .................................................................2-13
Table 3.1: Bus Arbiter Jumper Settings..................................................................................3-3
Table 3.2: PCI Bus Clock Jumper Settings ..............................................................................3-4
Table 3.3: System Slot Termination Jumper Settings ...............................................................3-5
Table 3.4: 2 Slot Backplane Configuration Pins........................................................................3-7
Table 3.5: 2 Slot Backplane System Slot 0 Pin Assignments......................................................3-8
Table 3.6: 2 Slot Backplane Peripheral Slot 1 Pin Assignments ..................................................3-9
Table 3.7: 3 Slot Backplane Configuration Pins......................................................................3-10
Table 3.8: 3 Slot Backplane System Slot 0 ...........................................................................3-11
Table 3.9: 3 Slot Backplane Peripheral Slot 1........................................................................3-12
Table 3.10: 3 Slot Backplane Peripheral Slot 2........................................................................3-13
Table 4.1: Serial EEPROM Factory Default Values.....................................................................4-4
Table 4.2: PCI-P0 Configuration Space Address Map ..............................................................4-12
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