Curtiss-Wright PMC-605 User manual

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OUTREACH PCI/PMC
EXPANSION SYSTEM
USER’SMANUAL
809524
D
February 2009
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II 809524 VERSION DFEBRUARY 2009
REVISION HISTORY
Rev By Date Description
1 JL June 2000 First engineering release.
- JL June 2000 Production release.
Updated Appendix B to reflect modified PCI-P0 backplane pins.
Changed cable requirements in Appendix A as product now uses standard base-
card cables.
Changed title of document to reflect new tabset.
Added J1 JTAG connector information in Chapter 2.
A JP November 2001 Updated Chapter 3 to reflect modified PCI-P0 backplane pins.
Changed title of document to reflect new OUTREACH system name.
B JP June 2002 Improved the explanation on page 1-3 of JTAG support for the CPLD on the
PMC-605.
Clarified statement on page 1-8 to indicate that when the bus is parked, it is parked
on the System Slot.
Changed description of PCI System Reset (RST#) signal on page 2-3 to remove
dependence on the Busmode1 signal.
Removed the Clock Mask section on page 2-4, since the clock signal will now
always be present on the PMC sites (dependence on the Busmode1 signal has
been removed), regardless if a PMC module is installed.
Updated Table 2.6 to reflect pinout changes (signals on P0 connector pins P0-A4
and P0-C4 have been swapped) that were introduced via ECO number
500000000673. This ECO allows smart PMC modules installed on the SVME/DMV-
210 to perform DMA cycles back to the host card.
Added note on page 3-2 that summarizes which E jumpers on the BPL-605-002 and
BPL-605-003 are reserved.
Improved Figure 3.2, Figure 3.3, and Figure 3.4 to indicate the correct orientation of
the 2 or 3 Slot Development Backplanes and the location of the E-jumper straps.
Corrected errors in Table 3.7 (specifically the descriptions of “Clock Source”,
“Request Line”, and “Grant Line”).
Corrected error in “Configure Master’s Primary BARs” on page 4-9. The Command
Register is located at 0x44, not 0x40 as was previously shown.
Improved Figure A.3 to clarify how the BPL-605-002 and BPL-605-003 Develop-
ment Backplane modules need to be oriented for correct operation.
C JP June 2004 Updated to correct SVME/DMV-210 P0 pinout table (see Table 2.6 on page 2-11).
Updated to correct SVME/DMV-210 P2 pinout table (see Table 2.8 on page 2-13).
D JP February 2009 Updated to address CR#26124. See “Install PMC-605 on Basecard” on page A-3 for
corrected cross reference to document number 808335.
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CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
809524 VERSION DFEBRUARY 2009 III
COPYRIGHT NOTICE
The information in this document is subject to change without notice and should not be
construed as a commitment by Curtiss-Wright Controls, Inc. While reasonable precautions
have been taken, Curtiss-Wright Controls, Inc. assumes no responsibility for any errors that
may appear in this document.
No part of this document may be copied or reproduced without the prior written consent of
Curtiss-Wright Controls, Inc.
The proprietary information contained in this document must not be disclosed to others for
any purpose, nor used for manufacturing purposes, without written permission of Curtiss-
Wright Controls, Inc. The acceptance of this document will be construed as an acceptance of
the foregoing condition.
Copyright © 2009, Curtiss-Wright Controls, Inc. All rights reserved.
TRADEMARKS
PowerPC is a trademark of International Business Machines Corporation.
VxWorks is a registered trademark of Wind River Systems, Inc.
Outreach is a trademark of CWCEC Systems Inc.
All other brand and product names are trademarks or registered trademarks of their
respective owners.
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IV 809524 VERSION DFEBRUARY 2009
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TABLE OF CONTENTS
1. PMC-605 PCI-P0 Bridge Module................................................................................ 1-1
General Description ..............................................................................................................1-1
Summary of Features......................................................................................................1-3
PCI-P0 Bridge Description......................................................................................................1-4
21554 PCI-to-PCI-Bridge Controller...................................................................................1-4
Primary and Secondary PCI Buses.....................................................................................1-4
PCI-P0 Bus Arbitration.....................................................................................................1-5
PCI-P0 Bus Clock ............................................................................................................1-6
PCI-P0 System Slot Termination .......................................................................................1-8
Interrupts......................................................................................................................1-8
Reset ............................................................................................................................1-9
Serial EEPROM..............................................................................................................1-10
LED.............................................................................................................................1-10
Registers .....................................................................................................................1-10
Physical, Electrical, and Environmental Characteristics.............................................................1-11
Dimensions..................................................................................................................1-11
Mating Connectors ........................................................................................................1-11
Electrical Characteristics ................................................................................................1-12
Environmental Characteristics.........................................................................................1-12
Connector Pin Assignments..................................................................................................1-13
Connector Locations......................................................................................................1-13
Pn1/Pn2 Pin Assignments...............................................................................................1-14
Pn3 Pin Assignments .....................................................................................................1-15
Pn4 Pin Assignments .....................................................................................................1-16
J1 Test JTAG Port..........................................................................................................1-17
2. SVME/DMV-210 Carrier Card...................................................................................... 2-1
General Description ..............................................................................................................2-1
Summary of Features......................................................................................................2-2
PCI-P0 Bridge Description......................................................................................................2-3
Configuration .................................................................................................................2-3
PCI Signal Environment ...................................................................................................2-3
PCI System Reset (RST#) ................................................................................................2-3
PCI Interrupts ................................................................................................................2-3
PCI JTAG Test Signals......................................................................................................2-4
PMC Bus Mode Signals.....................................................................................................2-4
Physical, Electrical, and environmental Characteristics...............................................................2-5
Dimensions....................................................................................................................2-5
Mating Connectors ..........................................................................................................2-5
Electrical Characteristics ..................................................................................................2-6
Environmental Characteristics...........................................................................................2-6
Connector Pin Assignments....................................................................................................2-7
PMC Site 1: Jn1 and Jn2 Connectors..................................................................................2-7
PMC Site 1: Jn3 and Jn4 Connectors..................................................................................2-8
PMC Site 2: Jn1 and Jn2 Connectors..................................................................................2-9
PMC Site 2: Jn3 and Jn4 Connectors................................................................................2-10
VME P0 Connector Pin Assignments.................................................................................2-11
VME P1 Connector Pin Assignments.................................................................................2-12
VME P2 Connector Pin Assignments.................................................................................2-13
3. PCI-P0 Development Backplane................................................................................ 3-1
General Description ..............................................................................................................3-1
Backplane Jumper Configurations ...........................................................................................3-2
Bus Arbiter Jumper Settings.............................................................................................3-2
PCI Bus Clock Jumper Settings .........................................................................................3-4
System Slot Termination Jumper Settings ..........................................................................3-5
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PCI-P0 Backplane Pin Assignments......................................................................................... 3-7
2 Slot Backplane Configuration Pins .................................................................................. 3-7
2 Slot Backplane System Slot 0 Pin Assignments ................................................................ 3-8
2 Slot Backplane Peripheral Slot 1 Pin Assignments............................................................. 3-9
3 Slot Backplane Configuration Pins .................................................................................3-10
3 Slot Backplane System Slot 0 Pin Assignments ...............................................................3-11
3 Slot Backplane Peripheral Slot 1 Pin Assignments............................................................3-12
3 Slot Backplane Peripheral Slot 2 Pin Assignments............................................................3-13
4. System Integration......................................................................................................4-1
Configuration of the PCI-P0 Bus............................................................................................. 4-1
PMC-605 Non-Transparent PCI-PCI Bridging....................................................................... 4-1
SVME/DMV-210 Transparent PCI-PCI Bridging.................................................................... 4-1
PMC-605 Terminology..................................................................................................... 4-2
Example: Transferring Data Between Two SBCs ....................................................................... 4-3
Serial EEPROM Configuration............................................................................................ 4-3
SVME/DMV-179 GPM Map Command With PMC-605 Installed ............................................... 4-5
Base Address Register Initialization................................................................................... 4-7
Primary BAR Configuration............................................................................................... 4-8
Translated Base Register Configuration.............................................................................. 4-9
Address Map for Local PCI and P0 Buses...........................................................................4-11
Transferring Data ..........................................................................................................4-11
PCI-P0 Configuration Space Addressing..................................................................................4-12
Addressing Example.......................................................................................................4-12
A. Installation Instructions............................................................................................. A-1
Installation Overview............................................................................................................ A-1
Unpack Cards ................................................................................................................ A-2
Configure Cards and PCI-P0 Development Backplane........................................................... A-2
Install PMC-605 on Basecard............................................................................................ A-3
Insert Cards in Chassis.................................................................................................... A-3
Attach the PCI-P0 Development Backplane......................................................................... A-4
Connect Basecard to Terminal.......................................................................................... A-5
Apply Power .................................................................................................................. A-5
Display Initial Screen Message ......................................................................................... A-5
Install BSP.....................................................................................................................A-6
Index ...................................................................................................................................I-1
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LIST OF FIGURES
Figure 1.1: Sample Application of PMC-605 PCI-P0 Bridge Module...............................................1-1
Figure 1.2: PMC-605 Functional Block Diagram ........................................................................1-2
Figure 1.3: Primary and Secondary PCI Buses..........................................................................1-4
Figure 1.4: Bus Arbitration and Signal Direction .......................................................................1-5
Figure 1.5: PCI-P0 Clock Source Configurations........................................................................1-7
Figure 1.6: Inter-Card Interrupt Mechanism.............................................................................1-9
Figure 1.7: PMC-605 Physical Layout ....................................................................................1-11
Figure 1.8: Connector Locations...........................................................................................1-13
Figure 1.9: Location of PMC-605 on a SVME/DMV-179.............................................................1-17
Figure 2.1: Sample Application of SVME/DMV-210 Carrier Card ..................................................2-1
Figure 2.2: SVME/DMV-210 Block Diagram..............................................................................2-2
Figure 2.3: SVME/DMV-210 Physical Layout.............................................................................2-5
Figure 3.1: PCI-P0 Development Backplane Slot Locations (3 Slot Version) ..................................3-1
Figure 3.2: Bus Arbiter Jumper Locations ................................................................................3-3
Figure 3.3: Clock Source Jumper Locations..............................................................................3-4
Figure 3.4: Bus Termination Jumper Locations .........................................................................3-6
Figure 4.1: Primary and Secondary PCI Buses..........................................................................4-2
Figure 4.2: Example System..................................................................................................4-3
Figure 4.3: Local PCI Address Map after BAR Configuration........................................................4-7
Figure 4.4: Example of Address Map based on BAR Requirements...............................................4-8
Figure 4.5: Master-Slave Memory Mappings...........................................................................4-11
Figure 4.6: Type 0 Configuration Cycle Example.....................................................................4-13
Figure 4.7: Type 1 Configuration Cycle Example.....................................................................4-13
Figure A.1: Outreach PCI/PMC Expansion System .....................................................................A-1
Figure A.2: PMC Site Location ................................................................................................A-3
Figure A.3: PCI-P0 Backplane Installation ................................................................................A-4
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809524 REVISION DFEBRUARY 2009 IX
LIST OF TABLES
Table 1.1: Clock Source Configurations ..................................................................................1-7
Table 1.2: Local Control and Status Register (LCSR)..............................................................1-10
Table 1.3: Environmental Specification Limits and Ruggedization Levels ...................................1-12
Table 1.4: Pn1/Pn2 Pin Assignments....................................................................................1-14
Table 1.5: Pn3 Pin Assignments ..........................................................................................1-15
Table 1.6: Pn4 Pin Assignments ..........................................................................................1-16
Table 1.7: J1 Test JTAG Port Pin Assignments.......................................................................1-17
Table 1.8: Sample SVME/DMV-179 P0 Connector Pin Assignments...........................................1-18
Table 2.1: Environmental Specification Limits and Ruggedization Levels .....................................2-6
Table 2.2: PMC Site 1: Pin Assignments (Jn1 and Jn2) .............................................................2-7
Table 2.3: PMC Site 1: Pin Assignments (Jn3 and Jn4) .............................................................2-8
Table 2.4: PMC Site 2: Pin Assignments (Jn1 and Jn2) .............................................................2-9
Table 2.5: PMC Site 2: Pin Assignments (Jn3 and Jn4) ...........................................................2-10
Table 2.6: VME P0 Connector Pin Assignments......................................................................2-11
Table 2.7: Pin Assignments for VME P1 Connector .................................................................2-12
Table 2.8: Pin Assignments for VME P2 Connector .................................................................2-13
Table 3.1: Bus Arbiter Jumper Settings..................................................................................3-3
Table 3.2: PCI Bus Clock Jumper Settings ..............................................................................3-4
Table 3.3: System Slot Termination Jumper Settings ...............................................................3-5
Table 3.4: 2 Slot Backplane Configuration Pins........................................................................3-7
Table 3.5: 2 Slot Backplane System Slot 0 Pin Assignments......................................................3-8
Table 3.6: 2 Slot Backplane Peripheral Slot 1 Pin Assignments ..................................................3-9
Table 3.7: 3 Slot Backplane Configuration Pins......................................................................3-10
Table 3.8: 3 Slot Backplane System Slot 0 ...........................................................................3-11
Table 3.9: 3 Slot Backplane Peripheral Slot 1........................................................................3-12
Table 3.10: 3 Slot Backplane Peripheral Slot 2........................................................................3-13
Table 4.1: Serial EEPROM Factory Default Values.....................................................................4-4
Table 4.2: PCI-P0 Configuration Space Address Map ..............................................................4-12
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CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
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PREFACE
PURPOSE
This manual provides an overview of the OUTREACH PCI/PMC Expansion System, which is
comprised of the PMC-605 PCI-P0 Bridge Module, the SVME/DMV-210 Carrier Card, and the
PCI-P0 Development Backplane. The manual also explains how to install the system and
configure the PCI-P0 bus.
AUDIENCE
This document is intended for readers with a technical understanding of hardware engineering
fundamentals, as well as an understanding of the VMEbus, PCI, and CompactPCI
architectures.
SCOPE
This manual contains the following chapters:
Chapter 1 - PMC-605 Bridge Module. Describes the features, functions, and pin
assignments of the PMC-605.
Chapter 2 - SVME/DMV-210 Carrier Card. Describes the features, functions, and pin
assignments of the SVME/DMV-210 Carrier Card.
Chapter 3 - PCI-P0 Development Backplane. Describes the PMC-605’s PCI-P0 2 and 3 slot
development backplanes.
Chapter 4 - System Configuration. Explains how to program the base address registers of
the PMC-605 and lists the default contents of the EEPROM device.
Appendix A - Installation Instructions. Explains how to install the Outreach components
into a system.
RELATED DOCUMENTS
Foundation Firmware v8.0 User’s Manual, CWCEC document #808006. In particular, refer to
Appendix A of this document. It describes the Foundation Firmware extensions specific to the
PMC-605.
Getting Started with the 21554 Embedded PCI-to-PCI Bridge Application Note. Intel
Corporation document #278210-001. Available for download from website at
http://developer.intel.com.
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CONVENTIONS USED IN THIS MANUAL
This document and the accompanying documents in the documentation package use various
icon conventions and abbreviations to make the documents clearer and easier to read. These
conventions cover typography for such elements as sample software code and keystrokes,
signal meanings, and graphical elements for important information such as warnings or
cautions.
Typographic
Conventions Table 1 lists the typographical conventions used in documents contained in this documentation
package.
Signal
Conventions Table 2 lists symbols that can follow a signal name. For example, the asterisk (#) is used with
a PCI signal name, such as IRDY#.
TABLE 1: Typographical Conventions
Item Convention Example
Keystrokes Keys are listed as they appear on most keyboards,
surrounded by < > marks. Combinations of key-
strokes appear within a single set of < > brackets.
Type < Ctrl-Alt-C > to return to the previous menu.
Type < Esc > to exit.
File Names File names are set in italics. Open the file named es.h.
Directory Names Directory names show the full directory path. The last
directory in the path does not have a trailing slash
following it.
Go to the c:\windows\temp\backup directory.
Monitor Displays Prompts and other text appearing on monitors is set
in bold monospace type. % mpp MC68040gnu >
Firmware Code Firmware code, and any information you need to
type in response to a prompt, is set in monospace
type.
% make -f Makefile.MC68040gnu
TABLE 2: Signal Conventions
Symbol Description
[no symbol] The signal is active HIGH.
# or - The signal is active LOW.
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CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
809524 REVISION DFEBRUARY 2009 XIII
Abbreviations Table 3 lists the abbreviations used to describe the size of a memory device or a range of
addresses.
Memory
Addresses Unless otherwise stated, all memory addresses are shown in hexadecimal notation.
Icons The following icons are used throughout this document:
TABLE 3: Abbreviations
Abbreviation Convention
1 Kbyte 1,024 bytes
1 Mbyte 1,024 Kbytes
1 Gbyte 1,024 Mbytes
Cross Reference
Warning
Caution
Note
Tip
Cross references to other documents are used when a subject being discussed is addressed
in depth by another, more authoritative document. Cross references are also used for
document chapters and sections.
The warning icon indicates procedures in the manual that, if not carried out, or if carried out
incorrectly, could cause physical injury, electrical damage to equipment, or a non-
recoverable corruption of data. Warnings include instructions for preventing such damage.
Please observe warning icons and read the accompanying text completely before carrying
out the procedure.
The caution icon indicates non-catastrophic incidents, complex practices, or procedures
which, if not observed, could result in damage to the hardware. Cautions include specific
instructions for avoiding or minimizing these incidents.
The note icon highlights exceptions and special information.
Tips provide extra information on the subject matter. This could include hints about how to
use your current CWCEC card to its maximum potential.
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TECHNICAL SUPPORT INFORMATION
If you are unable to resolve installation or configuration-related difficulties using the guidance
provided in this document, contact Technical Support or check out the Continuum Support
Center web site for additional assistance:
http://csc.cwcembedded.com/
Once registered, you will have online access to additional or updated technical documentation,
in addition to software components, etc. as these items become available.
ToAccessCWCEC
Technical Support For Technical Support contact information, go to the CWCEC web site:
http://www.cwcembedded.com/
and click on the “Contact” tab. This will bring up a page containing links specific to your needs:
http://www.cwcembedded.com/1/88/61.html
From here you can access additional topics such as :
• Continuum Lifecycle Services
• Technical Support
• Professional Services
• Interoperability
• Repair and Warranty
• Software Upgrade Program
• Lifecycle Support
Repair and
Warranty
Information
Curtiss-Wright Controls Embedded Computing’s standard warranty provides one-year
coverage of parts and labor and also features:
• A repair turnaround target of 15 business days
• Return shipping
• No-fault-found coverage
• Quality Engineering services such as corrective repair reporting and failure analysis
when warranted
Repairs outside the scope of the warranty are performed for a fixed price for in-production
cards. Fixed prices help customers achieve cost determinism and, through streamlined
administration associated with fixed prices, shorten repair turn-around times.
To obtain and prepare a Return Material Authorization (RMA) form, click on the “Repair &
Warranty” link available on the Tech Support Contact page identified above.
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809524 REVISION DFEBRUARY 2009 1-1
1
PMC-605 PCI-P0 BRIDGE MODULE
GENERAL DESCRIPTION
The PMC-605 PCI-P0 Bridge Module is a single-width PMC module that extends the local PCI
bus of its host Single Board Computer (SBC) out to the SBC’s P0 connector. This enables the
SBC to communicate with other similarly equipped cards in the VMEbus system over a high-
speed PCI bus (referred to as the PCI-P0 bus in this manual).
The PMC-605 performs such functions as:
• Expanding the number of PMC modules attached to a processor card (single board
computer or digital signal processor)
• Interconnecting multiple processor cards via a high-speed PCI secondary backplane.
• Providing a private PCI data path to custom I/O cards.
Figure 1.1 shows a sample application of the PMC-605. The two SBCs use the PMC-605 to
access each others’ shared PCI resources while the SVME/DMV-210 Carrier Card extends the
PCI bus of each single board computer with additional I/O capabilities.
FIGURE 1.1: Sample Application of PMC-605 PCI-P0 Bridge Module
Figure 1.2 shows a functional block diagram of the PMC-605.
VMEbus
PCI-P0 Bus
Single
Board
Computer
Single
Board
Computer
SVME/DMV-210
Carrier Card
PMC-605 PMC-605 Custom
I/O Card
Custom
I/O Card
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FIGURE 1.2: PMC-605 Functional Block Diagram
Intel 21554
Embedded PCI Bridge
Controller
CPLD
System Controller Functions,
Arbiter and Local Control and Status
Register
Secondary PCI Bus Primary PCI Bus
Arbiter Functions
Configuration Settings
Status
LED
Serial EEPROM
(Bridge
Configuration)
JTAG
JTAG
3.3V
Regulator
+5V +3.3V
Secondary
Bus Primary Bus
Control
PCI Int
Pri D'bell Int
PCI Int
H
o
s
t
P
C
I
B
u
s
P
0
P
C
I
B
u
s
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CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING PMC-605 PCI-P0 BRIDGE MODULE
809524 REVISION DFEBRUARY 2009 1-3
SUMMARY OF FEATURES
The PMC-605 has the following major features:
Clock Speed The Intel 21554 PCI-to-PCI Bridge device supports a clock speed of 33 MHz on the Secondary
PCI Bus and 33 MHz on the Primary PCI bus. The Primary PCI bus connects to the PCI-P0
bus and the Secondary PCI bus interface connects to the Host PCI bus.
Bus Arbitration The PMC-605 is dynamically configured during power-up or reboot to act as the bus arbiter
when placed in the PCI-P0 backplane’s System Slot. The PMC-605 uses a parallel arbitration
scheme.
PCI Bus Clock The PMC-605 can generate a PCI bus clock for the PCI-P0 bus or receive it from an external
source. The PCI bus clock is dynamically enabled when placed in the PCI-P0 backplane’s
System Slot and is disabled when placed in a Peripheral Slot.
Synchronous and
Asynchronous
Operation
The PCI-P0 bus can be synchronous to the Primary PCI bus or operate completely
asynchronously according to the configuration of its PCI bus clock source.
System Slot
Termination The PMC-605 is dynamically configured during power-up or reboot to terminate signals as
necessary for the PCI bus when placed in the PCI-P0 backplane’s System Slot.
Power
Requirements The PCI-P0 bus is 3.3 V signalling, 5 V tolerant. The PMC-605 is powered via the basecard’s
+5 V rail; an on-board regulator provides +3.3 V.
Configuration
EEPROM A serial EEPROM stores basic configuration information for the 21554
PCI-to-PCI Bridge device.
JTAG Support The CPLD supports the IEEE Std 1149.1 boundary scan (JTAG) and is In-System
Programmable (if so configured by the fitting of optional zero ohm resistors) through the
host SBC JTAG interface. If the optional zero ohm resistors are not fitted, the CPLD must be
programmed through an on-board header. Note that the Intel 21554 is not included as part
of the JTAG loop.
Ruggedization
Levels The PMC-605 is available in air-cooled and conduction-cooled versions.
LED The PMC-605 has a green software-controllable power-on LED.
Note
More information on the PMC-605 features listed above is provided in the following sections.
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1-4 809524 REVISION DFEBRUARY 2009
PCI-P0 BRIDGE DESCRIPTION
21554 PCI-TO-PCI-BRIDGE CONTROLLER
The PMC-605 uses the Intel 21554 Embedded PCI-to-PCI Bridge device. The 21554 is a non-
transparent PCI-to-PCI bridge designed to connect multiple processor domains, enabling the
host basecard to independently configure and control the local subsystem.
PRIMARY AND SECONDARY PCI BUSES
The PMC-605’s Primary PCI bus runs through the P4 connector to the P0 connector on the
basecard. The Primary PCI bus runs at 33 MHz and supports 32-bit addressing and data
transfers.
The Secondary PCI bus is connected to the host basecard’s local PCI bus. The Secondary PCI
bus runs at 33 MHz and supports 64-bit addressing and data transfers.
FIGURE 1.3: Primary and Secondary PCI Buses
Cross Reference
The 21554 responds to Type 0 configuration cycles. For information about this device refer
to the Intel’s Getting Started with the 21554 Embedded PCI-to-PCI Bridge Application
Note, document #278210-001. Manuals and data sheets on the 21554 can be downloaded
from Intel’s website at http://developer.intel.com.
PCI Bridge
PMC-605
Module
Secondary PCI Bus
(Local Host PCI Bus)
Pn4
Pn1 Pn2
Host
Basecard
P0
VME
Backplane
(PCI-P0 bus)
Primary PCI Bus
Pn3
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CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING PMC-605 PCI-P0 BRIDGE MODULE
809524 REVISION DFEBRUARY 2009 1-5
PCI-P0 BUS ARBITRATION
The PMC-605 can act as the bus arbiter for the PCI-P0 bus. A CPLD provides the arbitration
functions; the arbitration functions built into the 21554 bridge chip are not used.
Arbitration
Scheme The PMC-605 uses a parallel arbitration scheme in which each card on the PCI-P0 bus is free
to request the use of the bus at any time. The PMC-605 acting as bus arbiter grants the bus
on a “first come, first serve” basis.
PCI-P0 Bus Arbiter
Enable/Disable The PMC-605 acts as the PCI-P0 bus arbiter when the ARBDIS signal is connected directly to
Ground. When the arbiter function is enabled, REQ0# and REQ1# signals are inputs to the
arbiter, signalling that the asserting device requests the use of the PCI-P0 bus. After
completing the arbitration process, the arbiter asserts the GNT0# or GNT1# signal to the
requesting device.
The PMC-605’s arbiter function is disabled when the ARBDIS signal is connected to Vcc.
When the arbiter function is disabled, the role of REQ0# and GNT0# become reversed. The
REQ0# pin functions as GNT0# (i.e. becomes the Grant 0 input) and the GNT0# pin
functions as REQ0# (i.e. becomes the Request 0 output). In other words, REQn# signals are
always inputs and GNTn# signals are always outputs.
Figure 1.4 illustrates the function of each signal when the PMC-605’s arbiter function is either
enabled or disabled.
FIGURE 1.4: Bus Arbitration and Signal Direction
PMC-605
21554
Arbiter/
Requester
GNT0#
REQ0# REQ1#
GNT1#
REQ
GNT
PMC-605
21554
GNT0#
REQ0# REQ1#
GNT1#
REQ
GNT
PMC-605
21554
GNT0#
REQ0# REQ1#
GNT1#
REQ
GNT
Arbiter Enabled Arbiter Disabled
Request to Enabled Arbiter
Grant from Enabled Arbiter
Request to Enabled Arbiter
Grant from Enabled Arbiter
Arbiter Disabled
(ARBDIS connected to GND) (ARBDIS connected to Vcc) (ARBDIS connected to Vcc)
System Slot 0 Peripheral Slot 1 Peripheral Slot 2
Arbiter/
Requester Arbiter/ Requester
Caution
The ARBDIS signal must not be left open circuit because it is an input to the arbiter device
which does not have a pull-up on it. Inputs should not be left floating. Also note that only
one card in the system should be configured as the bus arbiter.
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