Daewoo DSN-300A User manual

Service Manual
INTERNET SETTOP BOX
CHASSIS: CM-300
Model: DSN-300A
DSN-300B, S
DAEWOO ELECTRONICS CO., LTD.

1
TABLE OF CONTENTS
1. PRODUCT SPECIFICATION................................................................................................................. 2
2. DESCRIPTION OF THE EXTERNAL PORT ......................................................................................... 3
3. BLOCK DIAGRAM................................................................................................................................. 4
4. INTERNET SET TOP BOX SPECIFICATION........................................................................................ 5
5. DESCRIPTION OF THE CIRCUIT OPERATION................................................................................... 7
6. PIN.......................................................................................................................................................... 11
7. MODEM COM PORT SETTING............................................................................................................. 17
8. TROUBLE SHOOTING CHARTS.......................................................................................................... 18
9. REPLACEMENT PARTS LIST.............................................................................................................. 30
10. EXPLODED VIEW................................................................................................................................ 36
11. DESCRIPTION OF EXPLODED VIEW................................................................................................ 41

2
1. PRODUCT SPECIFICATION
1-1. DSN-300A
1-2. DSN-300B,S
SYSTEM INTERNET,E-MAIL, BBS
DISPLAY NTSC, PAL(4.43Mhz), VGA 640
 480
AC POWER AC120V, 60Hz
POWER CONSUMPTION 15W Under
WIDTH 280mm
DEPTH 220mm
HEIGHT 52mm
WEIGHT 1.6Kg
SYSTEM INTERNET,E-MAIL, BBS
DISPLAY NTSC, PAL(4.43Mhz), VGA 640
 480
AC POWER AC85V-265V, 47~63Hz
POWER CONSUMPTION 15W Under
WIDTH 280mm
DEPTH 220mm
HEIGHT 52mm
WEIGHT 1.6Kg

3
2. DESCRIPTION OF THE EXTERNAL PORT
ITEM TESTING POSITION
AND CONDITIONS SPECIFICATIONS REMARKS
Main AC Both ends of the AC 120 Vac ± 10% DSN-300A
Vcc B+ VCC, GND 5V
± 5%
Image Input VGA IN 75 Standard Signal
Image Output RCA VCR 75 1Vp-p
± 5%
S-VHS 75 burstlevel Y:1VP-P ± 5%
C:0.28Vp-p ±5%
VGA OUT 75 R.G.B.: 0.707 ±5%
LINEAR
DC OFFSET 0.5 V
H SYNC : 31.5kHz-40kHz
V SYNC : 50kHz-90kHz
Sound Output RCA AUDIO
(47 k or more) 1.414Vp-p
± 10%
(The standard is-3.8dBM)
Wire Keyboard or
Mouse Input VCC,GND
KBCLK
KBDATA
MSCLK
MSDATA
5V
± 5%
Normal; high. In operation; low.
12.5 kHZ [5.0Vp-p
± 15%]
4.2 kHz[5.0Vp-p ± 15%]
11kHz[5.0Vp-p ± 15%]
2kHz[5.0Vp-p ± 15%]
Wireless Keyboard or
Wireless Mouse Input IR When inputting using the keyboard 5Vp-p
± 15%
Printer Output PARALLEL standard output

4
3. BLOCK DIAGRAM

5
4. INTERNET SET TOP BOX SPECIFICATION
4-1. HARDWARE SPECIFICATION
1. CPU : VLSI VY86C7500
ARM7 RISC CPU core from Advanced RISC Machine Co.

Highly intergrated RISC computer

30 Dhrystone 2.1 MIPS ARM7 core @ 33MHz CPU clock

4 Kbyte combined instruction and data cache

Flexible Memory Management Unit

Supports 16 or 32 bit wide memory via internal ROM and DRAM controllers

3 channel DMA

I/O controller

8 stereo sound channels

2 serial ports, 4 A/D channels

32-bit CD quality serial sound channel

Video controller with up to 120MHz pixel clock

16 million colors from 256-entry palette

16-level grey scales for LCD displays

Suspend and stop power saving modes
2.Memory

PROM : 512 KB
Boot routine & Emergency Program Storage

FLASH ROM : 1MB Extendible up to 2MB
Application Program & User Data Storage

DRAM : 4 MB Extendible up to 32MB
Program Running Spec.
3. Modem

33,600bps Modem ( ISA Interface )
4. Miscellaneous

NTSC/PAL Encoder, IR Receiver Circuit
5. Peripheral Port

Keyboard/Mouse Ports

S-video Output

Composite A/V Output

Telephone Line I/O Ports

VGA Output

VGA Input Port for TV encoder

Printer Port

6
6. Accessory

Remocon

Wireless Keyboard ( Option )

RCA, S-Cabie
4-2. SOFTWARE SPECIFICATION
1. Network Access

Any ISP accessible (DirectPPP Server)
2. Browser

HTML 3.2 Support

Font size : 3 sets

Fast Formatting

HTTP 1.0 Protocol Support

FORM, Table Support

GIF, JPEG, XBM Type Image Support

GIF animation Support

WAV, PCM Type Audio Support

Frame Support

Bookmark

Proxy Support

Caching of recently visited pages

Software Keyboard

Word Search

Printer Output Support
3. E-mail

IMAP, POP3 Client Protocol Support

Software Keyboard

7
5. DESCRIPTION OF THE CIRCUIT OPERATION
1. ARM 7500 part
The circuit is divided into digital and analogue input/output parts around the ARM 7500 part.
Two addresses and two data buses are basically served from the ARM 7500 part.

RA (DRAM ROW/COLUMN MULTIPLEXED ADDRESSES) uses 12 bits.

LA (LATCHED ADDRESSES) uses 29 bits.

D (MAIN DATA BUS) uses 32 bits.

BD (MAIN EXTERNAL BUS) uses 16 bits.
RA and D are connected to the DRAM (the capacity is 8 Mbyte), the main memory,
in the SIMM module, and are used when the actual program is operated.
2. PROM part
D and LA are connected to the PROM (the capacity is 4 Mbit).
When the power is turned on, the system reads the initial program codes set in the PROM
and loads them onto the memory.
There is a smallWEB BROWSER for emergency use in the PROM.
This can be used if there are any problems in the WEB BROWSER.
The ROM can be loaded by operating the power SW and the A/S SW.
(Turn the power SW on while pressing the A/S SW, then turn the A/S SW off in 2 sec.)
3. FLASH MEMORY part
BD and LA are connected to FLASH MEMORY (the capacity is 1 Mbyte to 4 Mbitmemories-[1 byte = 8 bit]),
which performs the same function as a hard disc in a PC.
The main program, WEB BROWSER, is loaded, and the INTERNET SET TOP BOX operates.
4. RECEIVER CIRCUIT part
A PS/2-type keyboard and a PS/2-type mouse used for PCs are provided from the ARM 7500.
These can be connected as normal-type wired keyboards and mouses or can be used as
wireless-type accessories through the receiver circuit composed of wireless receiver devices,
89C2051 and 97C52.
5. PRINTER OUTPUT part
8 bit data is supplied to the printer port from BD through 74HC377 for printing.
The printer controlsignals are supplied through the 8 bit WIDE IO PORT.
6. IMAGE OUTPUT part
VGA signals are provided to display images directly to the PC monitor from the ARM 7500.
The composite video and S-VHS(Y, C) signals are provided so that the signals can be displayed on
the CRT using the CH7001A NTSC ENCODER.

Horizontal/vertical position change: UP(26), DOWN (27), LEFT (28), RIGHT (29)

NTSC/PAL selection:NTSC*PAL (30)

Flicker filtering: MS0 (11), MS1(12)

8
7. CLOCK part
A clock is needed for the main board of the INTERNET SET TOP BOX.
MCLK (65 MHz) and VCLK (25.18 MHz) are supplied to the ARM 7500,
and XOUT (14.318 MHz) is supplied to CH7001A.
The clock doubling chip, CH9294, connected to crystal takes the role.
8. SOUND OUTPUT part
SOUND OUTPUT is supplied from the ARM 7500 in digital and analogue types.
Analogue signals, R and L, are supplied to the external amplifier through
CS4333 SOUND ENCODER using the digital type stereo sound data and the clock.
9. POWER part
DC 5V is applied to the main part from the power module through CONN AS by operating SMPS.
The power LED is turned ON/OFF by receiving signals from the power module.

Detailed description should be added.
10. MODEM part
Data needs to be added by the vendor.

Picture of the external appearance and the wiring diagram

Main parts and PIN location

If the telephone function does not operate

If INTERNET connection does not operate

If the wireless keyboard/remote control do(es) not operate

If the PC input picture is flowing vertically.

If the wired keyboard/remote control do(es) not operate

If the power LED has on-and-off failure

9
ARM 7500
The ARM 7500 is used for the basic processor in Daewoo INTERNET Settop box DSN-300A.
The ARM 7500 is a multimedia processorimplemented on a chip. A chip is composed ofimage and sound
treatment part, and otherI/O treatmentparts,centering the ARM 710C CPU core. The image treatment part
can display the screens of monitors, TVs or LCDs.
The I/O treatment part is used for interfaces of keyboards or joysticks.
The block diagram of the ARM 7500 is as follow:
The ARM 710C is a 32-bitRISC microprocessormodule. This has a 4Kbyte cache,write buffer and ARM7
processor core with Memory Management Unit (MMU). The image block can drive high-level CDTs or low-
voltage LCD displaying devices. The image module can obtain many kinds of frequencies because it is de-
signed to drive a Voltage Controlled Oscillator (VCO) in order to supply the master frequency. The sound
block has an 8-bit analogue stereo system and a 32-bit serial sound interface suitable to drive the external
CD DAC. The clock controlis flexibly designed and is divided into a CPU core clock inputand the input/output
system clock including the memory system clock and image input. The power control has two modes. The
clock inputting into the CPU is suspended but display function is on in the SUSPEND mode, All clocks are
suspended in the STOP mode.
Interrupts & Timers
Clock & Power
Timing & Clock
Serial portl
Serial portl
DMA DRAM
Decode ROM
4xA/DI/O Ctl
Arbitration
Data Buffer
MMU
4KB Cache
ARM7
Write Buffer
Data Latch
Sound
FIFO Video FIFO Cursor FIFO
Sound
DACs Video
Palette Cursor
Palette
Sterep
Digital RGB DACs LCD
MUX
IO & Memory
ARM704
CPUCLK
VidCLK
SndCLK
MemCLK
Reset
D[31:0]
DAC Ref
L/R DACs
Mute
Timing
RGB DACs
LCD
Serial
Wakeup
OSC Ctl
DRAM
ROMCS
Analogue
IOP[7:0]
A[28:0]
I/O Chip Select
PCMCIA XIF
IOD[15:0]
Interrupts

10
This micro-controller uses a reformed memory interface, ensuring both lower costs and high quality.
The memory interface control logic is designed perfectly asynchronously to the I/O control logic.
A 32-bit or 16-bit memory system can be used.
The DRAM controller is designed to drive even 4-bank DRAM directly.
The DMA channel, in which 3 programs can be operated, includes image, CRT and sound data.
There are 3 I/O cycle types as follows:

Simple I/O - fixed 8 MHz timing

Module I/O variable 8 MHz timing

PC bus style I/O 32-bit, 16 MHz timing
Other characteristics are the AD converter channel and two serialkeyboard mouse ports.
ARM7500
Top View
Pin 240 Pin 181
Pin 120Pin 61
Pin 60
Pin 121
Pin 1
Pin 180

11
6. PIN
PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME
1 LA[15] 41 VDD 81 ED[3]
2 LA[16] 42 D[12] 82 ED[2]
3 LA[17] 43 D[11] 83 ED[2]
4 LA[18] 44 D[10] 84 ED[0]
5 LA[19] 45 D[9] 85 VSS
6 LA[20] 46 D[8] 86 VSYNC
7 LA[21] 47 VSS 87 VSS_CORE
8 VDD 48 D[7] 88 HSYNC
9 LA[22] 49 D[6] 89 VDD_CORE
10 VSS 50 D[5] 90 VIREF
11 LA[23] 51 D[4] 91 VDD_ANALOG
12 LA[24] 52 D[3] 92 ROUT
13 LA[25] 53 D[2] 93 BOUT
14 LA[26] 54 D[1] 94 GOUT
15 LA[27] 55 D[0] 95 VSS_ANALOG
16 LA[28] 56 VDD 96 nTEST
17 D[31] 57 PCOMP 97 nINT8
18 D[30] 58 VSS 98 nINT3
19 D[29] 59 VCLKI 99 nINT6
20 D[28] 60 VCLKO 100 INT7
21 VSS 61 VDD_SOUND 101 RA[11]
22 D[27] 62 LP 102 RA[10]
23 D[26] 63 RP 103 RA[9]
24 VDD 64 RM 104 VSS
25 D[25] 65 LM 105 RA[9]
26 D[24] 66 VSS_SOUND 106 VDD
27 D[23] 67 SIREF 107 RA[7]
28 D[22] 68 SDO_MUTE 108 RA[6]
29 D[21] 69 SCLK 109 RA[5]
30 VSS_CORE 70 SDCLK 110 RA[4]
31 D[20] 71 WS_LNR 111 RA[3]
32 VDD_CORE 72 SINK 112 RA[2]
33 D[19] 73 ECLK 113 RA[1]
34 D[18] 74 VSS 114 RA[0]
35 VSS 75 HCLK 115 VSS
36 D[17] 76 ED[7] 116 nRAS[3]
37 D[16] 77 ED[6] 117 VDD
38 D[15] 78 ED[5] 118 nRAS[2]
39 D[14] 79 VDD 119 nRAS[1]
40 D[13] 80 ED[4] 120 nRAS[0]

12
121
vdd_atod
161
BD(3)
201
nMSCS
122
ATODREF
162
BD(2)
202
nBLO
123
ATOD(3)
163
BD(1)
203
nRBE
124
TOD(2)
164
BD(0)
204
nWBE
125
ATOD(1)
165
MSCLK
205
CLK2
126
ATOD(0)
166
VDD
206
REF8M
127
VS_ATOD
167
MSDATA
207
CLK8
128
nCAS(3)
168
KBCLK
208
CLK16
129
nCAS(1)
169
nPOR
209
nIOR
130
VSS
170
VSS
210
VSS
131
nCAS(1)
171
nPOR
211
nIOR
132
VDD
172
IOP(7)
212
VSS_CORE
133
nCAS(0)
173
IOP(6)
213
CPUCLK
134
nWE
174
IOP(5)
214
VDD_CORE
135
OSCPOWER
175
IOP(4)
215
nIOW
136
OSCDELAY
176
IOP(3)
216
VDD
137
SnA
177
IOP(2)
217
nCCS
138
RESET
178
IOP(1)
218
nCDACK
139
nRESET
179
IOP(0)
219
IORNW
140
nROMCS
180
ID
220
nPCCS2
141
BD(15)
181
OD(1)
221
nPCCSI
142
BD(14)
182
OD(0)
222
LNBW
143
I_OCLK
183
SETCS
223
LA(0)
144
VSS
184
INT9
224
LA(1)
145
nEVENT2
185
nINT4
225
LA(2)
146
BD(13)
186
INT5
226
VSS
147
BD(12)
187
READY
227
LA(3)
148
BD(11)
188
nIOGT
228
LA(4)
149
VDD
189
nBLI
229
LA(5)
150
BD(11)
190
nXIPMUX16
230
LA(6)
151
VSS_CORE
191
nINT1
231
LA(7)
152
MEMCLK
192
INT2
232
LA(8)
153
VDD_CORE
193
VSS
233
VDD
154
BD(9)
194
nEVENT1
234
LA(9)
155
BD(8)
195
nXIPLATCH
235
LA(10)
156
BD(7)
196
TC
236
LA(11)
157
BD(6)
197
nSIOCS2
237
LA(12)
158
BD(5)
198
VDD
238
VSS
159
VSS
199
nSIOCS1
239
LA(13)
160
BD(4)
200
nEASCS
240
LA(14)
PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME

13
6-1. MBM29F040A-90PD4 PLCC
6-2. AT27C4096-12JC-44J PLCC
Pin Function
A
0
TO A
18
Addess Inputs
DQ0 TO DQ7 Data Inputs/Outputs
CE Chip Enable
OE Output Enable
WE Write Enable
Vss Device Ground
V
CC
Device Power Supply
(5.0V, 10%)
Pin Function
A
0
TO A
17
Addess
O
0
TO O
15
Outputs
CE Chip Enable
OE Output Enable
NC No Connect
GND Device Ground
V
CC
Device Power Supply
(5.0V, 10%)
A12 A15 A16 A18 Vcc WE A17
DQ1 DQ2
Vss
DQ3
DQ4 DQ5 DQ6
4 3 2 1 32 31 30
5
6
7
8
9
10
13
12
11
A7
A6
A5
A4
A3
A2
DQ0
A0
A1
29
28
27
26
25
24
21
22
23
A14
A13
A8
A9
A11
OE
DQ7
CE
A10
14 15 16 17 18 19 20
O13 O14 O15 CE VPP NC VCC A17 A16 A15 A14
6 5 4 3 2 1 44 43 42 41 40
O3 O2 O1 O0
OE
NC
A0 A1 A2 A3 A4
18 19 20 21 22 23 24 25 26 27 28
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17

14
6-3. 74HC377D
6-4. CS4333K-S
6-5. GMS 97C52
20 Vcc
Q7 D7 D6 Q6 Q5 D5 D4 Q4 Cp
E
Q0
D0 D1
Q1
Q2
D2
D3
Q3
GND
19 18 17
377
16 15 14 13 12 11
1 2 3 4 5 6 7 8 9
10
1
2
3
4
SDATA
DEM/SCLK
LRCK
MCLK
AOUTL
VA+
AGND
AOUTR
8
7
6
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
(T2) P1.0
(T2 EX)P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD)P3.1
(INTO) P3.2
(IMT1) P3.3
(TO) P3.4
(T1) P3.5
(WR) P3.6
(RD)P3.7
XTAL2
XTAL1
GND
Vcc
P0.0 (AD0)
P0.1 (AD1)
P0.2(AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

15
6-6. AT89C2051
6-7. CH7001A
1
2
3
4
5
6
7
8
9
10
RST
(RXD) P3.0
(TXD) P3.1
XTAL2
XTAL1
(INTO) P3.2
(INT1) P3.3
(TO) P3.4
(T1) P3.5
GND
VCC
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1 (AIN1)
P1.0 (AIN0)
P3.7
20
19
18
17
16
15
14
13
12
11
STROBE AGND R AVDD G AGND B AVDD AGND VREF1 AGND
6 5 4 3 2 1 44 43 42 41 40
VDD
RSET
GND
Y
CVBS
C
GND
VDD
UP
DOWN
LEFT
18 19 20 21 22 23 24 25 26 27 28
CLKEN*
CLKOUT
DVDD
DGND
MS0
MS1
DVDD
DGND
XI
XO/FIN
PD1
VREF2
AVDD
PD0
TEST*
H
V
UNDERSCAN
DVDD
DGND
NTSC/PAL*
RIGHT
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
CHRONTEL
CH7001A

16
6-8. CH9294G-S
1
2
3
4
5
6
7
8
9
10
XO/FIN
XI
MS2
FS0
FS1
STROBE
FS2
FS3
MS0
GND
VDD
VCLK
XOUT
GND
AGND
AVDD
GND
VDD
MCLK
MS1
20
19
18
17
16
15
14
13
12
11

17
7. MODEM COM PORT SETTING
YES-581CLX
1 2 3 4
JP13
23361FX(C)3420
14
13
12
11
10
9
8
7
6
5
4
3
2
1
IRQ - 3 4 5 7 12 11 10
P1
CE
FIX COM2 IRQ3

18
8. TROUBLE SHOOTING CHARTS
8-1. NO DISPLAY
VIDEO CONNECTOR
CHECK
CH7001A IN/OUT
CHECK
CH9294G XOUT
CHECK
VGA OUT
CHECK
ARM7500
RGB CHECK
CH9294G
VIDCLK CHECK
ROM BOOTING
CHECK
DRAM REPLACE
CHECK
ARM7500
REPLACE
CH7001A
CHECK/REPLACE
CH9294G REPLACE
SOFT UPGRADE
FLASH ROM
REPLACE
DRAM
REPLACE
N.G.
N.G.
N.G.
N.G.

19
8-2. ROM BOOTING TROUBLE
8-3. NO PC INPUT DISPLAY
FLASH ROM
CHECK
ROM SOCKET
CHECK
SOFTWARE UPGRADE
CHECK
FLASH ROM
REPLACE CHECK FLASH ROM REPLACE
ARM7500/BOARD
CHECK
SOFTWARE
UPGRADE
SOCKET
RETOUCH/REPLACE
N.G.
N.G.
N.G.
PC SIGNAL
640

480, TV ENCODER
PC SIGNAL
CHECK
CABLE
CHECK
SW PUSH
CHECK SW PUSH REPLACE
RECONNECTION
NOT AVAILABLE
N.G.
N.G.
N.G.