Dallas DS87C550 Owner's manual

1 of 93 3/09/00
DS87C550
High-Speed Microcontroller
User’s Guide Supplement
www.dalsemi.com
Section 1:Introduction
This document is provided as a supplement to the High-Speed Microcontrollers User’s Guide, covering
new or modified features specific to the DS87C550. This document must be used in conjunction with
the High-Speed Microcontroller User’s Guide, available from Dallas Semiconductor. Addenda are
arranged by section number, which correspond to sections in the High-Speed Microcontroller User’s
Guide.
The following additions and changes, with respect to the High-Speed Microcontroller User’s Guide, are
contained in this document. This document is a work in progress, and updates/additions will be added as
available.
Section 2:Ordering Information
Information on new members of the High-Speed Microcontroller family has been added.
Section 3:Architecture
No Changes. Information containing new architectural features is contained in the DS87C550 data sheet.
Section 4:Programming Model
Descriptions of new and modified Special Function Registers in the DS87C550 have been included.
Section 5:CPU Timing
Descriptions of the clock multiply/divide modes have been added.
Section 6:Memory Access
Information on EPROM size and the DPTR auto-select feature have been added.
Section 7:Power Management
Changes in the power management clock divisor are discussed.
Section 8:Reset Conditions
A discussion of the reset output has been included.
Section 9: Interrupts
The interrupt structure found on the DS87C550 is described.
Section 10:Parallel I/O
Descriptions of the new I/O ports have been added.
Section 11:Programmable Timers
New clock multiply and divide functions added to the DS87C550’s Timers are described.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
2 of 93
Section 12:Serial I/O
No changes.
Section 13:Timed Access Protection
Additional/modified Timed Access bits in the DS87C550 are listed.
Section 14:Real-Time Clock
No changes.
Section 15:Battery Backup
No changes.
Section 16:Instruction Set Details
No changes.
Section 17:Troubleshoooting
No changes.
Section 18:Analog-to-Digital Converter
This is a new section describing the A/D converter found on the DS87C550.
Section 19:Pulse Width Modulator
This is a new section describing the PWM functions found on the DS87C550.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
3 of 93
SECTION 2:ORDERING INFORMATION
The High-Speed Microcontroller family follows the part numbering convention shown below. Note that
not all combinations of devices are planned to be made available. Refer to individual data sheet for
available versions.
DS87C550-QCL
SPEED: D 18 MHz
G 25 MHz
L 33 MHz
R 40 MHz
S 50 MHz
TEMPERATURE: C 0 °C to 70 °C
PACKAGE: M DIP
QPLCC
E Thin Quad Flat Pack (TQFP)
F Quad Flat Pack (QFP)
W Windowed Ceramic DIP
K Windowed Ceramic PLCC
OPERATING VOLTAGE: 0 +5V
3+3V OR WIDE VOLTAGE
MEMORY TYPE: 0 ROMLESS
3FACTORY PROGRAMMED MASK ROM
7EPROM (WINDOWED OR OTP
PACKAGES)
9FLASH

DS87C550 High-Speed Microcontroller User’s Guide Supplement
4 of 93
SECTION 3:ARCHITECTURE
No changes.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
5 of 93
SECTION 4:PROGRAMMING MODEL
SPECIAL FUNCTION REGISTERS
The following table identifies the complete SFR map for the DS87C550.
DS87C550 SPECIAL FUNCTION REGISTER LOCATIONS : Table 550UG-1
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS
P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 80h
SP 81h
DPL 82h
DPH 83h
DPL1 84h
DPH1 85h
DPS ID1 ID0 TSL - - - - SEL 86h
PCON SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLE 87h
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h
TMOD GATE T/C M1 M0 GATE T/C M1 M0 89h
TL0 8Ah
TL1 8Bh
TH0 8Ch
TH1 8Dh
CKCON WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh
P1 P1.7
TXD1 P1.6 RXD1 P1.5 T2EX P1.4 T2 P1.3 INT5/CT3 P1.2 INT4/CT2 P1.1 INT3/CT1 P1.0 INT2/CT0 90h
RCON - - - - CKRDY RGMD RGSL BGS 91h
SCON0 SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h
SBUF0 99h
PMR CD1 CD0 SWB CTM X2/X4 ALEOFF DME1 DME0 9Fh
P2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A0
SADDR0 A1h
SADDR1 A2h
IE EA EAD ES1 ES0 ET1 EX1 ET0 EX0 A8h
CMPL0 A9h
CMPL1 AAh
CMPL2 ABh
CPTL0 ACh
CPTL1 ADh
CPTL2 AEh
CPTL3 AFh
P3 P3.7
RD P3.6
WR P3.5
T1 P3.4 T0 P3.3
1INT P3.2 0INT P3.1
TXD0 P3.0 RXD0 B0h
ADCON1 BS
Y
/
S
TRT EOC SS/CONT ADEX WCQ WCM ADON WCIO B2h
ADCON2 OUTCF MUX2 MUX1 MUX0 APS3 APS2 APS1 APS0 B3h
ADMSB B4h
ADLSB B5h
WINHI B6h
WINLO B7h
IP - PAD PS1 PS0 PT1 PX1 PT0 PX0 B8h
SADEN0 B9h
SADEN1 BAh
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 2T/C 2RL BEh
T2MOD - - - - - - T2OE DCEN BFh

DS87C550 High-Speed Microcontroller User’s Guide Supplement
6 of 93
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS
P4 P4.7
CMT1 P4.6 CMT0 P4.5 CMSR5 P4.4 CMSR4 P4.3 CMSR3 P4.2 CMSR2 P4.1 CMSR1 P4.0 CMSR0 C0h
ROMSIZE - - - - - RMS2 RMS1 RMS0 C2h
STATUS PIP HIP LIP - SPTA1 SPRA1 SPTA0 SPRA0 C5h
TA 1 1 1 1 1 1 1 1 C7h
T2IR - CM2F CM1F CM0F IE5/CF3 IE4/CF2 IE3/CF1 IE2/CF0 C8h
CMPH0 C9h
CMPH1 CAh
CMPH2 CBh
CPTH0 CCh
CPTH1 CDh
CPTH2 CEh
CPTH3 CFh
PSW CY AC F0 RS1 RS0 OV F1 P D0h
PW0FG D2h
PW1FG D3h
PW2FG D4h
PW3FG D5h
PWMADR ADRS - - - - - PWE1 PWE0 D6h
SCON1 SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 D8h
SBUF1 D9h
PWM0 DCh
PWM1 DDh
PWM2 DEh
PWM3 DFh
ACC E0h
PW01CS PW0S2 PW0S1 PW0S0 PW0EN PW1S2 PW1S1 PW1S0 PW1EN E1h
PW23CS PW2S2 PW2S1 PW2S0 PW2EN PW3S2 PW3S1 PW3S0 PW3EN E2h
PW01CON PW0F PW0DC PW0OE PW0T/C PW1F PW1DC PW1OE PW1T/C E3h
PW23CON PW2F PW2DC PW2OE PW2T/C PW3F PW3DC PW3OE PW3T/C E4h
RLOADL E6h
RLOADH E7h
EIE ET2 ECM2 ECM1 ECM0 EX5/EC3 EX4/EC2 EX3/EC1 EX2/EC0 E8h
T2SEL TF2S TF2BS - TF2B - - T2P1 T2P0 EAh
CTCON 3CT CT3 2CT CT2 1CT CT1 0CT CT0 EBh
TL2 ECh
TH2 EDh
SETR TGFF1 TGFF0 CMS5 CMS4 CMS3 CMS2 CMS1 CMS0 EEh
RSTR CMT1 CMT0 CMR5 CMR4 CMR3 CMR2 CMR1 CMR0 EFh
BFOh
P6 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 F1h
EIP PT2 PCM2 PCM1 PCM0 PX5/PC3 PX4/PC2 PX3/PC1 PX2/PC0 F8h
WDCON SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT FFh
Note: Registers and bits in bold are new to the DS87C550. Registers and bits in bold AND Italic existed in
previous high-speed microcontrollers, but at different locations.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
7 of 93
DS87C550 SPECIAL FUNCTION REGISTER RESET VALUES : Table 550UG-2
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS
P0 1111111180h
SP 0000011181h
DPL 0000000082h
DPH 0000000083h
DPL1 0000000084h
DPH1 0 0 0 0 0 0 0 0 85h
DPS 0000010086h
PCON 0 0 Special 0 0 0 0 0 87h
TCON 0000000088h
TMOD 0000000089h
TL0 000000008Ah
TL1 000000008Bh
TH0 000000008Ch
TH1 000000008Dh
CKCON 000000018Eh
P1 1111111190h
RCON - - - - Special Special Special 0 91h
SCON0 0 0 0 0 0 0 0 0 98h
SBUF0 0000000099h
PMR 100000009Fh
P2 11111111A0
SADDR0 0 0 0 0 0 0 0 0 A1h
SADDR1 0 0 0 0 0 0 0 0 A2h
IE 00000000A8h
CMPL0 00000000A9h
CMPL1 00000000AAh
CMPL2 00000000ABh
CPTL0 0 0 0 0 0 0 0 0 ACh
CPTL1 00000000ADh
CPTL2 0 0 0 0 0 0 0 0 AEh
CPTL3 00000000AFh
P3 11111111B0h
ADCON1 0 0 0 0 0 0 0 0 B2h
ADCON2 0 0 0 0 0 0 0 0 B3h
ADMSB 00000000B4h
ADLSB 00000000B5h
WINHI 0 0 0 0 0 0 0 0 B6h
WINLO 00000000B7h
IP - 0 0 0 0 0 0 0 B8h
SADEN0 0 0 0 0 0 0 0 0 B9h
SADEN1 0 0 0 0 0 0 0 0 BAh
T2CON 00000000BEh
T2MOD ------00BFh
P4 11111111C0h
ROMSIZE00001100C2h
P5 11111111C4h
STATUS00010000C5h
TA 11111111C7h
T2IR - 0 0 0 0 0 0 0 C8h
CMPH0 00000000C9h
CMPH1 00000000CAh
CMPH2 00000000CBh
CPTH0 00000000CCh
CPTH1 00000000CDh

DS87C550 High-Speed Microcontroller User’s Guide Supplement
8 of 93
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS
CPTH2 00000000CEh
CPTH3 00000000CFh
PSW 00000000D0h
PW0FG 0 0 0 0 0 0 0 0 D2h
PW1FG 0 0 0 0 0 0 0 0 D3h
PW2FG 0 0 0 0 0 0 0 0 D4h
PW3FG 0 0 0 0 0 0 0 0 D5h
PWMADR0 - ----00D6h
SCON1 0 0 0 0 0 0 0 0 D8h
SBUF1 00000000D9h
PWM0 00000000DCh
PWM1 00000000DDh
PWM2 00000000DEh
PWM3 00000000DFh
ACC 00000000E0h
PW01CS00000000E1h
PW23CS00000000E2h
PW01CON00000000E3h
PW23CON00000000E4h
RLOADL 0 0 0 0 0 0 0 0 E6h
RLOADH00000000E7h
EIE 00000000E8h
T2SEL 0 0 -0--00EAh
CTCON 0 0 0 0 0 0 0 0 EBh
TL2 00000000ECh
TH2 00000000EDh
SETR 1 10 0 0 0 0 0 EEh
RSTR 00000000EFh
B 00000000FOh
P6 1 - 1 1 1 1 1 1 F1h
EIP 00000000F8h
WDCON 0 Special 0 Special 0 Special Special 0 FFh

DS87C550 High-Speed Microcontroller User’s Guide Supplement
9 of 93
Port 0 (P0) 76543210
SFR 80h P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
P0.7-0 Port 0. This port functions as a multiplexed address/data bus during external
memory access, and as a general purpose I/O port on devices with internal
program memory. During external memory cycles, this port drives the LSB of the
address when ALE is high, and data when ALE is low. When used as a general
purpose I/O, this port is open-drain and requires pull-ups. Writing a 1 to any pin
of this port places it in a high impedance mode, which is required if the pin is to
be used as an input. Pull-ups are not required when used as a memory interface.
Stack Pointer (SP)
76543210
SFR 81h SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-1 RW-1 RW-1
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SP.7-0
Bits 7-0 Stack Pointer. This stack pointer identifies the location where the stack will
begin. The stack pointer is incremented before every PUSH operation. This
register defaults to 07h after reset.
Data Pointer Low 0 (DPL)
76543210
SFR 82h DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
DPL.7-0
Bits 7-0 Data Pointer Low 0. This register is the low byte of the standard 80C32 16-bit
data pointer. DPL and DPH are used to point to non-scratchpad data RAM.
Data Pointer High 0 (DPH)
76543210
SFR 83h DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
DPH.7-0
Bits 7-0 Data Pointer High 0. This register is the high byte of the standard 80C32 16-bit
data pointer. DPL and DPH are used to point to non-scratchpad data RAM.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
10 of 93
Data Pointer Low 1 (DPL1)
76543210
SFR 84h DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DL1H.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
DPL1.7-0
Bits 7-0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data
pointer. When the SEL bit (DPS.0) is set, DPL1 and DPH1 are used in place of
DPL and DPH during DPTR operations.
Data Pointer High 1 (DPH1)
76543210
SFR 85h DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
DPH1.7-0
Bits 7-0 Data Pointer High 1. This register is the high byte of the auxiliary 16-bit data
pointer. When the SEL bit (DPS.0) is set, DPL1 and DPH1 are used in place of
DPL and DPH during DPTR operations.
Data Pointer Select (DPS)
76543210
SFR86hID1ID0TSL0----SEL
RW-0 RW-0 RW-0 R-0 R-0 R-0 R-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
ID1, ID0
Bits 7-6 Increment/Decrement Select Bits These bits define how the INC DPTR instruction functions in relation to the current DPTR as selected by SEL.
ID1 ID0 SEL = 0 SEL = 1
0 0 Increment DPTR Increment DPTR1
0 1 Decrement DPTR Increment DPTR1
1 0 Increment DPTR Decrement DPTR1
1 1 Decrement DPTR Decrement DPTR1
TSL
Bit 5 Toggle Select Bit Enable This bit allows any instruction involving the data
pointer to toggle the SEL bit automatically. When this bit is logic 1, the SEL
bit will automatically toggle, otherwise it will not.
Bits 4-1 Reserved. Read will be indeterminate.
SEL
Bit 0 Data Pointer Select. This bit selects the active data pointer. 0 = Instructions that use the DPTR will use DPL and DPH.
1= Instructions that use the DPTR will use DPL1 and DPH1.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
11 of 93
Power Control (PCON)
76543210
SFR 87h SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLE
RW-0 RW-0 RW-* RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset; *=see description
SMOD_0
Bit 7 Serial Port 0 Baud Rate Doubler Enable. This bit enables/disables the
serial baud rate doubling function for Serial Port 0.
0 = Serial Port 0 baud rate will be that defined by baud rate generation
equation.
1 = Serial Port 0 baud rate will be double that defined by baud rate generation
equation.
SMOD0
Bit 6
Framing Error Detection Enable. This bit selects function of the
SCON0.7 and SCON1.7 bits.
0 = SCON0.7 and SCON1.7 control the SM0 function defined for the
SCON0 and SCON1 registers.
1 = SCON0.7 and SCON1.7 are converted to the Framing Error (FE) flag for
the respective Serial Port.
OFDF
Bit 5
Oscillator Fail Detect Flag. This bit is set if a reset is caused by oscillator
failure and must be cleared by software.
OFDE
Bit 4 Oscillator Fail Detect Enable. This bit enables the oscillator fail detect circuitry
when 1 and disables the feature when 0.
GF1
Bit 3 General Purpose User Flag 1. This is a general purpose flag for software
control.
GF0
Bit 2 General Purpose User Flag 0. This is a general purpose flag for software
control.
STOP
Bit 1 Stop Mode Select. Setting this bit will stop program execution, halt the CPU
oscillator and internal timers, and place the CPU in a low-power mode. This bit
will always be read as a 0. Setting this bit while the Idle bit is set will place the
device in an undefined state.
IDLE
Bit 0 Idle Mode Select. Setting this bit will stop program execution but leave the CPU
oscillator, timers, serial ports, and interrupts active. This bit will always be read
as a 0.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
12 of 93
Timer/Counter Control (TCON)
76543210
SFR 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
TF1
Bit 7 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its
maximum count as defined by the current mode. This bit can be cleared by
software and is automatically cleared when the CPU vectors to the Timer 1
interrupt service routine.
0 = No Timer 1 overflow has been detected.
1 = Timer 1 has overflowed its maximum count.
TR1
Bit 6 Timer 1 Run Control. This bit enables/disables the operation of Timer 1.
0 = Timer 1 is halted.
1 = Timer 1 is enabled.
TF0
Bit 5 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its
maximum count as defined by the current mode. This bit can be cleared by
software and is automatically cleared when the CPU vectors to the Timer 0
interrupt service routine or by software.
0 = No Timer 0 overflow has been detected.
1 = Timer 0 has overflowed its maximum count.
TR0
Bit 4 Timer 0 Run Control. This bit enables/disables the operation of Timer 0.
Halting this timer will preserve the current count in THO and TL0.
0 = Timer 0 is halted.
1 = Timer 0 is enabled.
IE1
Bit 3 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined
by IT1 is detected. If IT1=1, this bit will remain set until cleared in software or
the start of the External Interrupt 1 service routine. If IT1=0, this bit will
inversely reflect the state of the INT1 pin.
IT1
Bit 2 Interrupt 1 Type Select. This bit selects whether the INT1pin will detect edge
or level triggered interrupts.
0 = INT1 is level triggered.
1 = INT1 is edge triggered.
IE0
Bit 1 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined
by IT0 is detected. If IT0=1, this bit will remain set until cleared in software or
the start of the External Interrupt 0 service routine. If IT0=0, this bit will
inversely reflect the state of the 0INT pin
IT0
Bit 0 Interrupt 0 Type Select. This bit selects whether the 0INT pin will detect edge
or level triggered interrupts.
0 = 0INT is level triggered.
1 = 0INT is edge triggered.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
13 of 93
Timer Mode Control (TMOD)
76543210
SFR 89h GATE T/C M1 M0 GATE T/C M1 M0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
GATE
Bit 7 Timer 1 Gate Control. This bit enable/disables the ability of Timer 1 to
increment.
0 = Timer 1 will clock when TR1=1, regardless of the state of INT1.
1 = Timer 1 will clock only when TR1=1 and INT1=1.
T/C
Bit 6 Timer 1 Counter/Timer Select.
0 = Timer 1 is incremented by internal clocks (timer).
1 = Timer 1 is incremented by pulses on T1 when TR1 (TCON.6) is 1 (counter).
M1, M0
Bits 5-4 Timer 1 Mode Select. These bits select the operating mode of Timer 1.
M1 M0 Mode
0 0 Mode 0: 8 bit with 5-bit prescale
0 1 Mode 1: 16 bit with no prescale.
1 0 Mode 2: 8 bit with auto-reload
1 1 Mode 3: Timer 1 is halted, but holds its count.
GATE
Bit 3 Timer 0 Gate Control. This bit enables/disables that ability of Timer 0 to
increment.
0 = Timer 0 will clock when TR0=1, regardless of the state of 0INT .
1 = Timer 0 will clock only when TR0=1 and 0INT = 1.
T/C
Bit 2 Timer 0 Counter/Timer Select.
0 = Timer incremented by internal clocks (timer).
1 = Timer 1 is incremented by pulses on T0 when TR0 (TCON.4) is 1 (counter).
M1, M0
Bits 1-0 Timer 0 Mode Select. These bits select the operating mode of Timer 0.
When Timer 0 is in mode 3, TL0 is started/stopped by TR0 and TH0 is
started/stopped by TR1. Run control for Timer 1 is then provided via the
Timer 1 mode selection.
M1 M0 Mode
0 0 Mode 0: 8 bit with 5-bit prescale
0 1 Mode 1: 16 bit no prescale
1 0 Mode 2: 8 bit with auto-reload
1 1 Mode 3: Timer 0 is two 8 bit counters.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
14 of 93
Timer 0 LSB (TL0)
76543210
SFR 8Ah TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
TL0.7-0
Bits 7-0 Timer 0 LSB. This register contains the least significant byte of Timer 0.
Timer 1 LSB (TL1)
76543210
SFR 8Bh TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
TL1.7-0
Bits 7-0 Timer 1 LSB. This register contains the least significant byte of Timer 1.
Timer 0 MSB (TH0)
76543210
SFR 8Ch TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
TH0.7-0
Bits 7-0 Timer 0 MSB. This register contains the most significant byte of Timer 0.
Timer 1 MSB (TH1)
76543210
SFR 8Dh TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
TH1.7-0
Bits 7-0 Timer 1 MSB. This register contains the most significant byte of Timer 1.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
15 of 93
Clock Control (CKCON)
76543210
SFR 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
WD1, WD0
Bits 7-6 Watchdog Timer Mode Select 1-0. These bits determine the watchdog timer
time-out period. The timer divides the crystal (or external oscillator) frequency
by a programmable value as shown below. The divider value is expressed in
crystal (oscillator) cycles. The settings of the system clock control bits X2/X4
(PMR.3) and CD1:0 (PMR.7-6) will affect the clock input to the watchdog
timer and therefore its time-out period as shown below. All Watchdog Timer
reset time-outs follow the setting of the interrupt flag by 512 clocks. The
DS87C550 does not incorporate a watchdog interrupt, but a similar effect may
be achieved by polling its flag.
Watchdog Interrupt Flag Time-Out Periods (in crystal clocks)
X2/X4 CD1:0 WD1:0=00 WD1:0=01 WD1:0=10 WD1:0=11
100 2
15 218 221 224
000 2
16 219 222 225
X01 2
17 220 223 226
X10 2
17 220 223 226
X11 2
25 228 231 234
T2M
Bit 5 Timer 2 Clock Select. This bit controls the division of the system clock that
drives Timer 2. This bit has no effect when the timer is in baud rate generator or
clock output modes. Clearing this bit to 0 maintains 80C32 compatibility. This
bit has no effect on instruction cycle timing.
0 = Timer 2 uses a divide by 12 of the crystal frequency.
1 = The divide ratio of Timer 2 is determined by the CD1, CD0, and 4X/ X2 as
shown below.
T1M
Bit 4 Timer 1 Clock Select. This bit controls the division of the system clock that
drives Timer 1. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 1 uses a divide by 12 of the crystal frequency.
1 = The divide ratio of Timer 1 is determined by the CD1, CD0, and 4X/ X2 as
shown below.
T0M
Bit 3 Timer 0 Clock Select. This bit controls the division of the system clock that
drives Timer 0. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 0 uses a divide by 12 of the crystal frequency.
1 = The divide ratio of Timer 0 is determined by the CD1, CD0, and 4X/ X2 as
shown below.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
16 of 93
Timer 0, 1, and 2 values as a function of various clock control settings
OSC CYCLES
PER TIMER 0/1/2
CLOCK.
OSC CYCLES PER
SERIAL PORT CLK,
MODE 0
OSC CYCLES PER
SERIAL PORT CLK,
MODE 2
CD1:0 4X/2X
OSCILLATOR
CYCLES PER
MACHINE.
CYCLE TxM=0 TxM=1
OSC CYCLES
PER TIMER 2
CLK, BAUD
RATE GEN. SM2=0 SM2=1 SMOD=0 SMOD=1
00 1 1 12 1 2 3 1 64 32
00 0 2 12 2 2 6 2 64 32
01 x Reserved
10 x 4 12 4 2 12 4 64 32
11 x 1024 3072 1024 512 3072 1024 64 32
MD2, MD1, MD0
Bits 2-0 Stretch MOVX Select 2-0. These bits select the time by which external MOVX
cycles are to be stretched. This allows slower memory or peripherals to be
accessed without using ports or manual software intervention. The RD or
WR strobe will be stretched by the specified interval, which will be transparent to
the software except for the increased time to execute to MOVX instruction. All
internal MOVX instructions on devices containing MOVX SRAM are performed
at the 2 machine cycle rate.
MD2 MD1 MD0 Stretch Value MOVX Duration
0 0 0 0 2 Machine Cycles
0 0 1 1 3 Machine Cycles (reset default)
0 1 0 2 4 Machine Cycles
0 1 1 3 5 Machine Cycles
1 0 0 4 9 Machine Cycles
1 0 1 5 10 Machine Cycles
1 1 0 6 11 Machine Cycles
1 1 1 7 12 Machine Cycles

DS87C550 High-Speed Microcontroller User’s Guide Supplement
17 of 93
Port 1 (P1) 76543210
SFR 90h P1.7
TXD1 P1.6 RXD1 P1.5 T2EX P1.4 T2 P1.3 3CT/5INT P1.2 2CT/4INT P1.1 1CT/3INT P1.0 0CT/2INT
RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
P1.7-0
Bits 7-0 General Purpose I/O Port 1. This register functions as a general purpose I/O
port. In addition, all the pins have an alternative function listed below. P1.2-7
contain functions that are new to the 80C32 architecture. The Timer 2 functions
on pins P1.1-0 are available on the 80C32, but not the 80C31. Each of the
functions is controlled by several other SFRs. The associated Port 1 latch bit
must contain a logic one before the pin can be used in its alternate function
capacity.
TXD1
Bit 7 Serial Port 1 Transmit. This pin transmits the serial port 1 data in serial port
modes 1, 2, 3 and emits the synchronizing clock in serial port mode 0.
RXD1
Bit 6 Serial Port 1 Receive. This pin receives the serial port 1 data in serial port
modes 1, 2, 3 and is a bi-directional data transfer pin in serial port mode 0.
T2EX
Bit 5 Timer 2 Capture/Reload Trigger. A 1 to 0 transition on this pin will cause the value in the T2 registers to be transferred into the capture registers if enabled by
EXEN2 (T2CON.3). When in auto–reload mode, a 1 to 0 transition on this pin
will reload the timer 2 registers with the value in RCAP2L and RCAP2H if
enabled by EXEN2 (T2CON.3).
T2
Bit 4 Timer 2 External Input. A 1 to 0 transition on this pin will cause timer 2
increment or decrement depending on the timer configuration. This mode of
operation is enabled by setting the 2T/C bit (T2CON.1).
3CT/5INT
Bit 3
External Interrupt 5/Capture 3 Input. In normal operation, a falling edge on
this pin will cause an external interrupt 5 (if enabled). If capture channel 3 is
enabled, this pin acts as a capture command input.
2CT/4INT
Bit 2
External Interrupt 4/Capture 2 Input. In normal operation, a falling edge on
this pin will cause an external interrupt 4 (if enabled). If capture channel 2 is
enabled, this pin acts as a capture command input.
1CT/3INT
Bit 1 External Interrupt 3/Capture 1 Input. In normal operation, a falling edge on
this pin will cause an external interrupt 3 (if enabled). If capture channel 1 is
enabled, this pin acts as a capture command input.
0CT/2INT
Bit 0 External Interrupt 2/Capture 0 Input. In normal operation, a falling edge on
this pin will cause an external interrupt 2 (if enabled). If capture channel 0 is
enabled, this pin acts as a capture command input.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
18 of 93
Ring Oscillator Control (RCON)
76543210
SFR 91h - - - - CKRDY RGMD RGSL BGS
R-* R-* RW-* RT-0
R=Unrestricted Read, W=Unrestricted Write, T=Timed Access Write Only, -n =Value after
Reset, * = See Description
Bits 7 – 4 Reserved. Read data will be indeterminate.
CKRDY
Bit 3 Clock Ready This bit indicates the status of the start-up period delay used to
establish the crystal oscillator or crystal multiplier warm-up period of 65536
crystal oscillator periods. A 1 indicates that the period is complete otherwise it is
not. This bit is cleared after a reset or when exiting STOP mode. It is also cleared
when the clock multiplier is enabled (CTM bit of the PMR register set). Once the
CKRDY bit is set, the lockout preventing CD1:CD0 from being modified is
removed, and clock multiplier may then be selected as the clock source.
RGMD
Bit 2 Ring Oscillator Mode This bit indicates the status of the ring oscillator. If 0, the
ring is not being used, and if 1, the system is running from the ring. This bit must
be cleared before the RGSL can be modified, before the Clock Control divider
bits (CD1:CD0) can be changed to any condition other than divide by 4 mode,
and before enabling the clock multiplier (setting the CTM bit).
RGSL
Bit 1 Ring Oscillator Select This bit enables (1) or disables (0) the ring oscillator. If enabled, the ring oscillator will be used as the system clock source after exiting
STOP mode until the end of start-up period delay (65536 crystal oscillator
periods). At the end of this delay, the crystal oscillator will automatically be
switched in as the system clock source. This bit is reset only by a Power-On
Reset.
BGS
Bit 0 Band Gap Select This bit enables (1) or disables (0) the band-gap voltage reference in STOP mode.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
19 of 93
Serial Port 0 Control (SCON0)
76543210
SFR 98h SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 T1_0 R1_0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SM0-2
Bits 7-5 Serial Port Mode These bits control the mode of serial port 0. In addition the
SM0 and SM2_0 bits have secondary functions as shown below.
SM0 SM1 SM2 MODE FUNCTION LENGTH PERIOD
0 0 0 0 Synchronous 8 bits 12 tCLK
0 0 1 0 Synchronous 8 bits 4 tCLK
0 1 X 1 Asynchronous 10 bits Timer 1 or 2 baud rate equation
1 0 0 2 Asynchronous 11 bits 64 tCLK (SMOD=0)
32 tCLK (SMOD=1)
1 0 1 1 Asynchronous w/
Multiprocessor
communication
11 bits 64 tCLK (SMOD=0)
32 tCLK (SMOD=1)
1 1 0 3 Asynchronous 11 bits Timer 1 or 2 baud rate equation
1 1 1 3 Asynchronous w/
Multiprocessor
communication
11 bits Timer 1 or 2 baud rate equation
SM0/FE_0
Bit 7 Framing Error Flag. When SMOD0 (PCON.6)=0, this bit (SM0) is used to
select the mode for serial port 0. When SMOD0=1, this bit (FE) will be set upon
detection of an invalid stop bit. When used as FE, this bit must be cleared in
software. Once the SMOD0 bit is set, modifications to this bit will not affect the
serial port mode settings. Although accessed from the same register, internally the
data for bits SM0 and FE are stored in different locations.
SM1_0
Bit 6 No alternate function.
SM2_0
Bit 5 Multiple CPU Communications. The function of this bit is dependent on the
serial port 0 mode.
Mode 0: Selects 12 tCLK or 4 tCLK period for synchronous serial port 0 data
transfers.
Mode 1: When set, reception is ignored (RI_0 is not set) if invalid stop bit
received.
Mode 2/3: When this bit is set, multiprocessor communications are enabled in
modes 2 and 3. This will prevent the RI_0 bit from being set, and an
interrupt being asserted, if the 9th bit received is not 1.

DS87C550 High-Speed Microcontroller User’s Guide Supplement
20 of 93
REN_0
Bit 4 Receiver Enable. This bit enable/disables the serial port 0 receiver shift register.
0 = Serial port 0 reception disabled.
1= Serial port 0 receiver enabled (modes 1, 2, 3). Setting this bit will initiate
synchronous reception in mode 0.
TB8_0
Bit 3 9th Transmission Bit State. This bit defines the state of the 9th transmission bit
in serial port 0 modes 2 and 3.
RB8_0
Bit 2 9th Received Bit State. This bit identifies that state of the 9th reception bit of
received data in serial port 0 modes 2 and 3. In serial port mode 1, when
SM2_0=0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.
TI_0
Bit 1 Transmitter Interrupt Flag. This bit indicates that data in the serial port 0
buffer has been completely shifted out. In serial port mode 0, TI_0 is set at the
end of the 8th data bit. In all other modes, this bit is set at the end of the last data
bit. This bit must be manually cleared by software.
RI_0
Bit 0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received
in the serial port 0 buffer. In serial port mode 0, RI_0 is set at the end of the 8th
bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit
subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample
of RB8_0. This bit must be manually cleared by software.
Serial Data Buffer 0 (SBUF0)
76543210
SFR 99h SBUF0.7 SBUF0.6 SBUF0.5 SBUF0.4 SBUF0.3 SBUF0.2 SBUF0.1 SBUF0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SBUF0.7-0
Bits 7-0 Serial Data Buffer 0. Data for serial port 0 is read from or written to this
location. The serial transmit and receive buffers are separate registers, but both
are addressed at this location.