Avnet Xilinx virtex-ii User manual

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user’s guide

Xilinx Virtex-II Development Kit

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Table of Contents

Xilinx Virtex-II Development Kit.................................................................................................................................................................1

Table of Contents.............................................................................................................................................................................................2

Figures ................................................................................................................................................................................................................3

Tables..................................................................................................................................................................................................................3

1.0 Introduction.....................................................................................................................................................................................4

1.1 Description..................................................................................................................................................................................4

1.2 Features:.......................................................................................................................................................................................4

1.3 Demo Applications:...................................................................................................................................................................4

1.4 Ordering Information: ..............................................................................................................................................................5

2.0 User Information............................................................................................................................................................................5

2.1 Power...........................................................................................................................................................................................5

2.2 Configuration..............................................................................................................................................................................5

2.2.1 Boundary scan Configuration..............................................................................................................................................6

2.2.2 System ACE MPM Configuration......................................................................................................................................6

2.2.3 SelectMAP and Custom Configuration Methods.............................................................................................................6

2.2.4 Configuration Modes............................................................................................................................................................7

2.2.5 JTAG Chain...........................................................................................................................................................................8

2.3 Jumper Settings...........................................................................................................................................................................9

3.0 Hardware........................................................................................................................................................................................11

3.1 Virtex-II FPGA........................................................................................................................................................................12

3.1.1 LVDS.....................................................................................................................................................................................12

3.2 Memory......................................................................................................................................................................................12

3.2.1 DDR SDRAM .....................................................................................................................................................................12

3.2.2 Flash.......................................................................................................................................................................................12

3.3 Communication........................................................................................................................................................................12

3.3.1 RS232 Transceiver...............................................................................................................................................................12

3.4 LED ...........................................................................................................................................................................................13

3.5 Dip Switches.............................................................................................................................................................................13

3.6 Connectors................................................................................................................................................................................13

3.6.1 General I/O Interface........................................................................................................................................................14

3.6.1.1 LVDS ...........................................................................................................................................................................16

3.6.2 Memory Expansion Connector Interface........................................................................................................................17

3.6.3 Auxiliary Connectors(Available only with FF1152 package) .......................................................................................19

3.6.4 Miscellaneous Connectors .................................................................................................................................................20

3.7 PCI/PCIX.................................................................................................................................................................................21

3.8 Evaluation Boards....................................................................................................................................................................23

3.9 Extender Card Board ..............................................................................................................................................................23

3.10 Power.........................................................................................................................................................................................23

3.10.1 FPGA I/O Voltage (Vcco)...........................................................................................................................................23

3.10.2 FPGA Reference Voltage (Vref)..................................................................................................................................23

3.11 Configuration Modes...............................................................................................................................................................23

4.0 Test Designs..................................................................................................................................................................................24

4.1 On-board Flash Test...............................................................................................................................................................25

4.2 PCI/PCI-X Test.......................................................................................................................................................................25

4.3 Switch/LED Test ....................................................................................................................................................................25

4.4 Avbus Connector Test............................................................................................................................................................25

4.5 DDR SDRAM Test.................................................................................................................................................................25

5.0 Example VHDL Project..............................................................................................................................................................25

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Figures

Figure 1 - Fly Wire Connection J2.................................................................................................................................................................6

Figure 2 - JTAG Chain.....................................................................................................................................................................................8

Figure 3 – JP1....................................................................................................................................................................................................9

Figure 4 - I/O Voltage Selection....................................................................................................................................................................9

Figure 5 - Virtex-II Development Board Block Diagram........................................................................................................................11

Figure 6 - Virtex-II Development Board....................................................................................................................................................11

Figure 7 - Barrel Power Connector "J4".....................................................................................................................................................23

Tables

Table 1: Ordering Information.......................................................................................................................................................................5

Table 2 - JTAG Headers (JTAG3 & JTAG4) Pin-Out..............................................................................................................................6

Table 3 - Virtex-II Power-up Configuration Modes...................................................................................................................................7

Table 4 - JTAG Boundary-Scan Description Language (BSDL) files......................................................................................................8

Table 5 - RS232 Connector Pin-out ............................................................................................................................................................12

Table 6 – LED Pin Assignment @ the FPGA..........................................................................................................................................13

Table 7 –Switch Pin Assignment @ the FPGA.........................................................................................................................................13

Table 8 – General I/O AvBus Connector P2 & P3.................................................................................................................................15

Table 9 – Low Voltage Differential Signaling Pairs (P3)..........................................................................................................................16

Table 10 – Memory I/O AvBus Connector P4 & P5 ..............................................................................................................................18

Table 11 – Auxiliary AvBus Connector P6 & P7......................................................................................................................................20

Table 12 – PCI/PCI-X Connector Pin Assignment and Interface Signals...........................................................................................22

Table 13 – Virtex-II Power-up Configuration Modes..............................................................................................................................24

Table 14 – System ACE Test Designs.........................................................................................................................................................24

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1.0 Introduction

The purpose of this manual is to describe the functionality and contents of the Virtex-II Development Kit from Avnet Design

Services. This document includes instructions for operating the board, descriptions of the hardware features and explanations

of the example projects.

1.1 Description

The Virtex-II Development Kit provides a complete hardware environment for designers to accelerate their time to market.

The kit delivers a stable platform to develop and test designs targeted to the highly advanced Xilinx Virtex-II FPGA family.

The installed XC2V1500 device offers a 1.5M system gate prototyping environment to effectively demonstrate the enhanced

benefits of the leading edge Xilinx FPGA solution. Embedded multipliers, advanced digital clock management, built-in

impedance matching, IP immersion, and other exciting features can be implemented with advanced Xilinx design tools.

Demonstration VHDL code is included with the kit to exercise standard peripherals on the evaluation board for a quick start

to device familiarization.

1.2 Features:

! FPGA

! Xilinx Virtex-II XC2V1500-FF896

! Board I/O Connectors

! Four 140-pin general purpose I/O expansion connectors (AvBus)

! +3.3V/+5V, 64-bit 66/100 MHz PCI/PCI-X interface

! 50 – Pin 0.1” Header

! Memory

! Micron DDR SDRAM DIMM (128MB)

! Flash Memory (16MB)

! Communication

! RS-232 serial ports

! Power

! Regulated 3.3V, 2.5V, 1.8V and 1.5V supply voltages generated from external 5V supply

! Configuration

! Xilinx XCCACEMxx-BG388I System ACE MPM Solution

! Parallel IV Cable support for JTAG

! Fly-wire support for Parallel-III and Multilinx.

1.3 Demo Applications:

The Virtex-II Development Kit from Avnet Design Services comes with test application designs used as base tests for the

peripherals on the board. The peripheral example designs, listed below, are discussed in detail in section 4.0.

! Flash test

! PCIX test

! LED test

! Connector Test

! DDR SDRAM Memory test

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1.4 Ordering Information:

The following table lists the Development system part numbers and available software options. Internet link at:

http://www.ads.avnet.com

Part Number Hardware

ADS-XLX-V2-DEV1500 Xilinx Virtex-II Development Kit populated

with an XC2V1500 device

ADS-XLX-MB-DEV1500 Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module and

MicroBlaze Core License

ADS-XLX-V2-DEV1500XP Xilinx Virtex-II Development Kit populated

with an XC2V1500 device & high-current

power supply

ADS-V2-MB-DEV1500XP

Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module,

MicroBlaze Core License & high-current

power supply

ADS-XLX-V2-DEV4000 Xilinx Virtex-II Development Kit populated

with an XC2V4000 device

ADS-XLX-MB-DEV4000 Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module and

MicroBlaze Core License

ADS-XLX-V2-DEV4000XP Xilinx Virtex-II Development Kit populated

with an XC2V4000 device & high-current

power supply

ADS-V2-MB-DEV4000XP

Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module,

MicroBlaze Core License & high-current

power supply

ADS-XLX-V2-DEV6000XP Xilinx Virtex-II Development Kit populated

with an XC2V6000 device & high-current

power supply

ADS-V2-MB-DEV6000XP

Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module,

MicroBlaze Core License & high-current

power supply

Table 1: Ordering Information

2.0 User Information

This section provides the user with information on how to get started using the Virtex-II Development board. It discusses

how to apply power to the board, configure the FPGA devices and set-up the jumpers.

2.1 Power

The Virtex-II Development Board is powered via the +5.0 volt PCI. However, it may be operated in stand-alone mode. In

stand-alone mode the Virtex-II board may be powered by an external power supply connected to the J1 barrel socket

connector. The supply should have a minimum of 2 AMP, +5.0 Volts regulated to +/- 5%. The current requirements for

the board are application specific.

2.2 Configuration

The Virtex-II Development board supports Boundary-scan as well as System ACE Multi-Package Module (MPM) solution. All

configuration pins are brought out to “J2”, should the user wish to program with an alternate method.

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2.2.1 Boundary scan Configuration

Programming the Virtex-II FPGA via Boundary-scan requires a JTAG download cable (not included in the kit). The Virtex-II

Development board has connectors to support both the flying leads connection of the Parallel Cable III and MultiLINX

cables, and the ribbon cable connection of the Parallel Cable IV. These connectors are labeled “J2” and “U25” respectively.

For more information about JTAG download cables see the Xilinx web page http://www.xilinx.com. Click on the

“Products” tab and then click on the “Configuration” link. Scroll down to “Desktop Programmers and Download Cables”

and select the download cable of interest.

When using the flying leads connection of the Parallel Cable III or MultiLINX, connect the leads as indicated for “J2”. These

connections are shown in Table 2 below.

Signal Name JTAG3 (J2) pin JTAG4 (JU25) pin

VCC 20 2

TDI 9 10

TDO 15 8

TMS 13 4

TCK 11 6

GND 19, 21 1,3,5,7,9,11 or 13

Table 2 - JTAG Headers (JTAG3 & JTAG4) Pin-Out

If the Parallel Cable IV is used, the ribbon cable connector mates with the JTAG4 (U25) connector. The connectors are keyed

to ensure the connections are made correctly. Table 2 also shows the pin-out of the JTAG4 connector..

2.2.2 System ACE MPM Configuration

The System ACE Multi-Package Module (MPM) is a configuration solution for high density FPGAs. Configuration files

for the target FPGA are programmed into the MPM using the iMPACT software and a JTAG download cable. The MPM

is a combination of three devices: a configuration PROM, a small Virtex-E FPGA and an industry-standard Flash device.

The PROM contains the configuration controller design that is loaded into the Virtex-E “controller” on power-up. The

controller handles reading the selected configuration file out of the Flash and programming the target FPGA, in this case,

the Virtex-II FPGA. The System ACE MPM can hold multiple bitstreams. The iMPACT software is used to generate a

single configuration file for the System ACE that contains all of the bitstreams and their corresponding controller address.

The MPM can hold 8 different designs, which are selected by setting the controller address. The address is set by

installing shunts/jumpers on JP103. For a description of the test files see Section 4.0.

2.2.3 SelectMAP and Custom Configuration Methods

The Viretx-II Development Board provides the user with an interface to the FPGA dedicated and dual function programming

pins. This provides fly-wire support for SelectMAP programming with MultiLINX, and gives flexibility for developing a

custom programming solution. Programming pins are provided with J2 as shown in Figure 1.

TDI

TCK

TMS

TDO

GND

GND VCC

CS_B

DONE

PROG_B

INIT_B

BUSY/DOUT

RDWR_B

CCLK

Figure 1 - Fly Wire Connection J2

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2.2.4 Configuration Modes

Upon power-up the FPGA will be enabled in a configuration mode defined by jumper header JP1. The default

configuration mode is “Master-Serial” mode, which will allow the FPGA to be programmed from the System ACE MPM.

The System ACE has been programmed with basic test application code to test the on-board peripherals. Section 4.0

describes the various tests included with the System ACE. Table 3 describes the various configuration modes available by

setting the appropriate jumper/mode select.

Configuration

Mode

JP1

(1-2)

JP1

(3-4)

JP1

(5-6)

* Master serial OPEN OPEN OPEN

Slave serial JUMPERED JUMPERED JUMPERED

Master SelectMAP OPEN JUMPERED JUMPERED

Slave SelectMAP JUMPERED JUMPERED OPEN

Boundary-scan JUMPERED OPEN JUMPERED

* = Default assembled state

Table 3 - Virtex-II Power-up Configuration Modes

JP1

Mode 0

Mode 1

Mode 2

JP1

Mode 0

Mode 1

Mode 2

Master Serial Mode:

No Jumpers on JP2

Master SelectMAP mode:

place jumpers at JP2

positions 1-2 & 3-4.

JP1

Mode 0

Mode 1

Mode 2

For Boundary Scan mode,

place jumpers at JP2

positions 1-2 & 5-6.

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2.2.5 JTAG Chain

The Virtex-II development board has two (2) devices in its JTAG chain (FPGA and System ACE MPM). The JTAG chain is

implemented as shown in Figure 2. The BSDL files for each device in the chain are given on Table 4.

* = Bypassed

Virtex

II JTAG Scan Chain Path

FPGA PROM No. 1

PROM No. 5

GEN IO CONNMEM CONN

FPGA_TDI

PCIX_TDO

MEM IO GEN IO 1

PCI/PCIX

FPGASystem ACE

J2 *

FPGA TDO

AV1_TDI

AV1_TDO

JTAG_TDO

(U25)

** = Jumper selectable w/ JP100

PROM No. 1

JP100

JTAG Chain Selection

JTAG_TDI

AV2_TDIAV2_TDO

Figure 2 - JTAG Chain

File Name Device Device Reference

Designator

XC2V1500_FF896.bsd FPGA U1

XC2V4000_FF1152.bsd FPGA U1

XCCACEMxx_BG388.bsd SYSTEM

ACE U5

Table 4 - JTAG Boundary-Scan Description Language (BSDL) files

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2.3 Jumper Settings

This section provides a description of the jumper settings for the Development board. The board is ready to use out of the

box with the default jumper settings.

JP1 – Configuration mode selection. Use to select the configuration mode for the FPGA. By default, these pins are pulled

low enabling Master Serial mode. Installing jumpers on JP1 will pull the corresponding mode pin high, as indicated in Figure 3.

See the Configuration section of this document or Chapter 3 of the Virtex-II Platform FPGA Handbook for further

information.

JP1

Mode 0

Mode 1

Mode 2

1-2 M1

3-4 M2

5-6

Master Serial

Slave Serial

Master SelectMAP

Slave SelectMAP

Boundary Scan

JP1

ConfigMode

Figure 3 – JP1

U25 – Parallel IV connector. See the Boundary scan section of this document for more information

JP2, JP12, & JP13 – Vcco selectable voltages are available on the Virtex-II Development Board to support the FPGAs various

voltage standards. The Virtex-II Development Board provides various selectable I/O voltages for FPGA banks 0,1,4 & 5,

independent of each other, to support the various I/O standards. The I/O voltages available are +3.3V, +2.5V, +1.8V and

+1.5V. JP2 selects I/O voltage for Banks 4&5; JP12 for Bank0, and JP13 for Bank1. Only one jumper should be placed at

each connector. Valid placements, per connector, are 1-2, 3-4, 5-6 or 7-8 as indicated in Figure 4

JP2

3.3V

2.5V

1.8V

2.5V

3-4 1.8V

5-6 1.5V

7-8

Jumper Position

I/O Voltage 3.3V

1-2

1.5V

Figure 4 - I/O Voltage Selection

JP4 – HSWAP_EN, Enables pull-ups on the Virtex-II I/O pins during configuration. Install a jumper to enable the

configuration pull-ups. Default: Open; pull-ups disabled.

JP5 – Access to temperature sensing diode pins of FPGA (DXP, DXN)

JP6, JP7, & JP8 - The PCI power jumper. When the jumpers are installed, they configure the board for PCI power mode, and

utilizes the +5Vdc from the PCI motherboard.

JP14 – Bank 0 Voltage Reference(Vref) selection. Selects Vref voltage for FPGA banks 0. The reference voltages available are

+1.65V, +1.25V, +.9V, +.75V and +1.5V (half the I/O voltage, and +1.5V which is jumper selected). Jumper 1-2 assigns

+1.5V as Bank0 Vref. Jumper 2-3 assigns half of I/O voltage selected with JP12 as Bank 0 Vref.

JP15 – Bank 1 Voltage Reference(Vref) selection. Selects Vref voltage for FPGA banks 1. The reference voltages available are

+1.65V, +1.25V, +.9V, +.75V and +1.5V (half the I/O voltage, and +1.5V which is jumper selected). Jumper 1-2 assigns

+1.5V as Bank1 Vref. Jumper 2-3 assigns half of I/O voltage selected with JP13 as Bank 1 Vref.

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JP16 – 50-pin FPGA general purpose header I/O.

JP17 – 20-pin FPGA general purpose 2.5V I/O header.

JP18 – 20-pin FPGA general purpose 3.3V I/O header.

JP19– 20-pin FPGA general purpose memory header.

JP100- JTAG Chain configuration. Selects the JTAG chain configuration. Install a jumper across pins 2-3 for standalone

mode (3 devices in chain: System ACE, Virtex-II, and PCIX). Install jumpers across pins 1-2 and pins 4-5 to add the AvBus

connector labeled “P2” on to the standalone chain. Install jumpers across pins 1-2, pins 3-4 and pins 5-6 to add the AvBus

connector labeled “P3” on to the standalone chain. These settings are described in detail in the Hardware section of this

manual (see section 3.11).

Default: Installed across pins 2-3; standalone chain mode.

JP101 – JTAG TCK Enable for JTAG Connector "P2". Default Closed.

JP102 – JTAG TCK Enable for JTAG Connector "P4". Default Closed.

JP103 – System ACE Test Control Address. The MPM file in the System ACE can hold 8 different designs, which are selected

by setting the controller address. The address is set by installing shunts/jumpers on JP103. For a description of the test files

see Section 4.0

JP104– System ACE Device Disable. Default Open.

JP904 – JTAG bypass ties board TDI to TDO, bypassing all devices. Default Open, JTAG chain enabled.

J100 – Active Heatsink Power.

J102 – 50-pin general purpose System ACE header.

J103 – Connector for Power Supply Daughter board.

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3.0 Hardware

The Virtex-II Development board is part of the Avalon Reference Design System™, provides a baseline development

backplane, which incorporates a high density; high I/O Virtex-II FPGA, memory functionality, basic I/O functionality, and

interface connections for development module installation. The intent is to provide a functional baseline development card

with optimal circuit functionality while providing the interface capability to allow the user to add, via the connector interfaces,

evaluation boards containing their desired/unique circuit functionality to integrate. The capability to install evaluation boards

onto the Virtex-II Development board allows FPGA integration between multiple platforms and I/O standards if desired.

The block diagram of the development board is shown in Figure 5.

PCI/PCI-X

JTAG/

SelectMAP

System ACE

MPM

Oscillators

+5V

Power

Supply

Power Regulation

RS-232

Xilinx

Virtex-II

XC2V1500,

XC2V4000

XC2V6000

Switches/

LEDs

DCI

Memory I/O AvBus

Connector

FLASH

Gen I/O AvBus

Connector

Header Connector

SODIMM

Micron

MT8VDDT1664HG

Gen I/O AvBus

Connector/LVDS

241I/O Lines

64 Bit Data

Memory I/O AvBus

Connector

I/O Expansion

Connector

I/O Expansion

Connector

Available with XC2V4000 & greater

541I/O Lines

Figure 5 - Virtex-II Development Board Block Diagram

Figure 6 - Virtex-II Development Board

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3.1 Virtex-II FPGA

The Virtex-II Development board was designed to support the Virtex-II FPGA in multiple packages and densities. The board

supports three different Virtex-II densities: XC2V1500, XC2V4000 or XC2V6000. The schematic symbol used for the Virtex-

II device indicates the specific I/O pins available in each density (XC2V1500-5FG896C (528 total I/O) in a FF896 fine pitch

BGA package or the XC2V4000/6000-4FF1152C (824 total I/O) in a FF1152 fine pitch package. Configuration information

is provided from two sources; the Xilinx Serial/Parallel Download Connectors (JTAG/SelectMAP), or System ACE MPM

configuration solution.

3.1.1 LVDS

The Virtex-II Evaluation board uses one of the AvBus connectors (P3) to provide up to 38 LVDS pairs. These pairs, labeled

LVDS_IN_P/N(1:11) and LVDS_OUT_P/N(1:27) are matched length. Each pair _P and _N are routed as differential pairs

and are tightly coupled. Each transmit or receive pair should be configured accordingly because by default, the receive pairs

termination resistors are installed on the board. A receive pair can be reconfigured as a transmit pair by removing the

termination resistor or a termination resistor can be installed for a transmit pair to convert it to a receive pair.

3.2 Memory

The Virtex-II Development board is populated with Micron SODIMM DDR memory and Intel StrataFlash. Additional

memory including FLASH, SDRAM, and SRAM are available with the purchase of the Avnet Communications/Memory

Module.

3.2.1 DDR SDRAM

The DDR SDRAM consists of one 128 MB DIMM module (expandable to 512 MB), accessible in a 64-bit configuration and

housed in a SODIMM packages. These are SSTL2 Class II interface devices running at a maximum 133 MHz (266 Mbits/S).

By using the Virtex-II Digital Clock Manager (DCM) the onboard 125.00 MHz frequency can be adjusted to support the DDR

SDRAM.

3.2.2 Flash

The FLASH memory consists of one 8 MB device in a 16-bit configuration. The device package is a 56-pin TSOP Type. The

current configuration utilizes 120 nanosecond devices, but the Virtex-II FPGA will support much faster devices.

3.3 Communication

The Virtex-II FPGA has access to an RS232 transceiver for communication purposes. The channel uses a DB9 (P1)

connector and an RS232 transceiver.

3.3.1 RS232 Transceiver

The RS232 transceiver is a 3222 available from Harris/Intersil (ICL3222CA) and Analog Devices (ADM3222). This

transceiver is operating at 3.3V for VCC. The FPGA transmit/receive signals are connected to an I/O voltage selectable

bank of the FPGA (Bank 2). Because the 3222 minimum logic threshold high is 2V, the recommended VCCO for the

FPGA are 2.5V or 3.3V. The internal charge pump creates the RS232 compatible output levels. See Table 5 for RS-232

connector pin assignment.

Signal

Name DB9 Connector Def.

TX out 2

RX in 3

GND 5

Table 5 - RS232 Connector Pin-out

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3.4 LED

The “DONE” LED (D3) is controlled by the DONE pin on the FPGA. The DONE pin on the FPGA is a bidirectional

signal with an internal pullup. Upon power-up the pin is driven LOW, and tri-states after the device is configured. Tri-

stating the pin after configuration turns the DONE LED on via the pullup resistor.

8 LED’s are provided for testing purposes. The pin assignment for the LEDs is provided in Table 6 .

LED 1500 Pin 4000 Pin Pin Description

LED0 L7 N9 LED0

LED1 M6 P8 LED1

LED2 L6 N8 LED2

LED3 L5 N7 LED3

LED4 K4 M6 LED4

LED5 K1 M3 LED5

LED6 J4 L6 LED6

LED7 J1 L3 LED7

Table 6 – LED Pin Assignment @ the FPGA

3.5 Dip Switches

An 8-position DIP-switch is mounted on the board and labeled “S1”.

SWITCH 1500 Pin 4000 Pin Pin Description

SWITCH0 AJ1 AL3 SWITCH0

SWITCH1 AH1 AK3 SWITCH1

SWITCH2 AG3 AJ5 SWITCH2

SWITCH3 AF4 AH6 SWITCH3

SWITCH4 AE5 AG7 SWITCH4

SWITCH5 AD5 AF7 SWITCH5

SWITCH6 AD9 AF11 SWITCH6

SWITCH7 AC9 AE11 SWITCH7

Table 7 –Switch Pin Assignment @ the FPGA

3.6 Connectors

The Virtex-II Development board is an Avalon compliant motherboard that incorporates board-to-board connectors to

support Avalon expansion boards. The connection between the Virtex-II Development board and the Avalon compliant

daughter boards is via the Avnet standard AvBus connectors (P2, P3, P4 and P5). All the connectors on the board are host

connectors, AMP part number 179031-6, which realize an effective I/O count of 241 signals with the X2V1500 part or 541

signals with the X2V4000/X2V6000. The host connectors allow the development board to serve as a motherboard and can

mate with an expansion board in an Avalon system. The board can mate with any expansion board with a mating connector,

AMP part number 5-179010-6. When interfacing to other boards care must be taken to tri-state any signals that could

interfere with those of the other board.

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3.6.1 General I/O Interface

A general I/O interface allows the user to adapt any desired functionality to the development kit backplane for research

and development. The FPGA connections to these connectors utilize a high I/O interface, thus allowing the user to select

the installation requirements for the development module. Two 140-pin connectors are paired to provide this interface.

See Table 8 for general I/O AvBus connector pin assignment. Signal routing from the FPGA to connector P3 is routed

as LVDS pairs, allowing connector P3 to supports LVDS signaling.

Name P2

Connector

Pin # Name Name P3

Connector

Pin # Name

GEN_IO1_0 71 1 +5V GEN_IO2_0 71 1 +5V

GND 72 2 GEN_IO1_1 GND 72 2 GEN_IO2_1

GEN_IO1_3 73 3 GEN_IO1_2 GEN_IO2_3 73 3 GEN_IO2_2

GEN_IO1_4 74 4 GND GEN_IO2_4 74 4 GND

GND 75 5 GEN_IO1_5 GND 75 5 GEN_IO2_5

GEN_IO1_7 76 6 GEN_IO1_6 GEN_IO2_7 76 6 GEN_IO2_6

GEN_IO1_8 77 7 GND GEN_IO2_8 77 7 GND

+3.3V 78 8 GEN_IO1_9 +3.3V 78 8 GEN_IO2_9

GEN_IO1_11 79 9 GEN_IO1_10 GEN_IO2_11 79 9 GEN_IO2_10

GEN_IO1_12 80 10 GND GEN_IO2_12 80 10 GND

GND 81 11 GEN_IO1_13 GND 81 11 GEN_IO2_13

GEN_IO1_15 82 12 GEN_IO1_14 GEN_IO2_15 82 12 GEN_IO2_14

GEN_IO1_16 83 13 +5V GEN_IO2_16 83 13 +5V

GND 84 14 GEN_IO1_17 GND 84 14 GEN_IO2_17

GEN_IO1_19 85 15 GEN_IO1_18 GEN_IO2_19 85 15 GEN_IO2_18

GEN_IO1_20 86 16 GND GEN_IO2_20 86 16 GND

GND 87 17 GEN_IO1_21 GND 87 17 GEN_IO2_21

GEN_IO1_23 88 18 GEN_IO1_22 GEN_IO2_23 88 18 GEN_IO2_22

GEN_IO1_24 89 19 GND GEN_IO2_24 89 19 GND

+3.3V 90 20 GEN_IO1_25 +3.3V 90 20 GEN_IO2_25

GEN_IO1_27 91 21 GEN_IO1_26 GEN_IO2_27 91 21 GEN_IO2_26

GEN_IO1_28 92 22 GND GEN_IO2_28 92 22 GND

GND 93 23 GEN_IO1_29 GND 93 23 GEN_IO2_29

GEN_IO1_31 94 24 GEN_IO1_30 GEN_IO2_31 94 24 GEN_IO2_30

GEN_IO1_32 95 25 +5V GEN_IO2_32 95 25 +5V

GND 96 26 GEN_IO1_33 GND 96 26 GEN_IO2_33

GEN_IO1_35 97 27 GEN_IO1_34 GEN_IO2_35 97 27 GEN_IO2_34

GEN_IO1_36 98 28 GND GEN_IO2_36 98 28 GND

GND 99 29 GEN_IO1_37 GND 99 29 GEN_IO2_37

GEN_IO1_39 100 30 GEN_IO1_38 GEN_IO2_39 100 30 GEN_IO2_38

GEN_IO1_40 101 31 GND GEN_IO2_40 101 31 GND

+3.3V 102 32 GEN_IO1_41 +3.3V 102 32 GEN_IO2_41

GEN_IO1_43 103 33 GEN_IO1_42 GEN_IO2_43 103 33 GEN_IO2_42

GEN_IO1_44 104 34 GND GEN_IO2_44 104 34 GND

GND 105 35 GEN_IO1_45 GND 105 35 GEN_IO2_45

GEN_IO1_47 106 36 GEN_IO1_46 GEN_IO2_47 106 36 GEN_IO2_46

GEN_IO1_48 107 37 +5V GEN_IO2_48 107 37 +5V

GND 108 38 GEN_IO1_49 GND 108 38 GEN_IO2_49

GEN_IO1_51 109 39 GEN_IO1_50 GEN_IO2_51 109 39 GEN_IO2_50

GEN_IO1_52 110 40 GND GEN_IO2_52 110 40 GND

GND 111 41 GEN_IO1_53 GND 111 41 GEN_IO2_53

GEN_IO1_55 112 42 GEN_IO1_54 GEN_IO2_55 112 42 GEN_IO2_54

GEN_IO1_56 113 43 GND GEN_IO2_56 113 43 GND

+3.3V 114 44 GEN_IO1_57 +3.3V 114 44 GEN_IO2_57

GEN_IO1_59 115 45 GEN_IO1_58 GEN_IO2_59 115 45 GEN_IO2_58

GEN_IO1_60 116 46 GND GEN_IO2_60 116 46 GND

GND 117 47 GEN_IO1_61 GND 117 47 GEN_IO2_61

GEN_IO1_63 118 48 GEN_IO1_62 GEN_IO2_63 118 48 GEN_IO2_62

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Released Literature # ADS-xxxx04

Name P2

Connector

Pin # Name Name P3

Connector

Pin # Name

GEN_IO1_64 119 49 +5V GEN_IO2_64 119 49 +5V

GND 120 50 GEN_IO1_65 GND 120 50 GEN_IO2_65

GEN_IO1_67 121 51 GEN_IO1_66 GEN_IO2_67 121 51 GEN_IO2_66

GEN_IO1_68 122 52 GND GEN_IO2_68 122 52 GND

GND 123 53 GEN_IO1_69 GND 123 53 GEN_IO2_69

GEN_IO1_71 124 54 GEN_IO1_70 GEN_IO2_71 124 54 GEN_IO2_70

GEN_IO1_72 125 55 GND GEN_IO2_72 125 55 GND

+3.3V 126 56 GEN_IO1_73 +3.3V 126 56 GEN_IO2_73

GEN_IO1_75 127 57 GEN_IO1_74 GEN_IO2_75 127 57 GEN_IO2_74

GEN_IO1_76 128 58 GND GEN_IO2_76 128 58 GND

GND 129 59 GEN_IO1_77 GND 129 59 GEN_IO2_77

GEN_IO1_79 130 60 GEN_IO1_78 GEN_IO2_79 130 60 GEN_IO2_78

GEN_IO1_80 131 61 +5V GEN_IO2_80 131 61 +5V

GND 132 62 GEN_IO1_81 GND 132 62 GEN_IO2_81

GEN_IO1_83 133 63 GEN_IO1_82 GEN_IO2_83 133 63 GEN_IO2_82

GEN_IO1_84 134 64 GND GEN_IO2_84 134 64 GND

GND 135 65 GEN_IO1_CLK_O

UT GND 135 65 GEN_IO2_CLK_OUT

GEN_IO1_CLKIN 136 66 GEN_IO1_CLK_F

B GEN_IO2_CLK

IN 136 66 GEN_IO2_CLK_FB

TMS 137 67 GND 137 67 GND

+3.3V 138 68 AV1_TDO +3.3V 138 68

AV1_TDI 139 69 TCK 139 69

TRST# 140 70 GND 140 70 GND

Table 8 – General I/O AvBus Connector P2 & P3

Avnet Design Services 16 of 25 Rev 1.0 06/08/2004

Released Literature # ADS-xxxx04

3.6.1.1 LVDS

Low Voltage Differential Signaling (LVDS) is available on connector P3. Eleven LVDS driver pairs and eleven LVDS

receiver pairs (optional drivers) are available. An additional thirteen LVDS driver pairs (two of which are optional

receivers) are available with a larger FPGA package – FF1152. See Table 9

Name P3

Connector

Drivers Name Name P3

Connector

Receivers Name

GEN_IO2_3 GEN_IO2_57 GEN_IO2_1

GEN_IO2_4 1 15 GEN_IO2_58 GEN_IO2_2 * 1

GEN_IO2_7 GEN_IO2_59 GEN_IO2_5

GEN_IO2_8 2 * 16 GEN_IO2_60 GEN_IO2_6 * 2

GEN_IO2_11 GEN_IO2_61 GEN_IO2_9

GEN_IO2_12 3 17 GEN_IO2_62 GEN_IO2_10 * 3

GEN_IO2_15 GEN_IO2_63 GEN_IO2_13

GEN_IO2_16 4 * 18 GEN_IO2_64 GEN_IO2_14 * 4

GEN_IO2_19 GEN_IO2_65 GEN_IO2_17

GEN_IO2_20 5 * 19 GEN_IO2_66 GEN_IO2_18 * 5

GEN_IO2_23 GEN_IO2_67 GEN_IO2_21

GEN_IO2_24 6 * 20 GEN_IO2_68 GEN_IO2_22 * 6

GEN_IO2_27 GEN_IO2_69 GEN_IO2_25

GEN_IO2_28 7 * 21 GEN_IO2_70 GEN_IO2_26 * 7

GEN_IO2_31 GEN_IO2_71 GEN_IO2_29

GEN_IO2_32 8 * 22 GEN_IO2_72 GEN_IO2_30 * 8

GEN_IO2_35 GEN_IO2_73 GEN_IO2_33

GEN_IO2_36 9 * 23 GEN_IO2_74 GEN_IO2_34 * 9

GEN_IO2_39 GEN_IO2_75 GEN_IO2_37

GEN_IO2_40 10 * 24 GEN_IO2_76 GEN_IO2_38 * 10

GEN_IO2_43 GEN_IO2_77 GEN_IO2_41

GEN_IO2_44 11 * 25 GEN_IO2_78 GEN_IO2_42 * 11

GEN_IO2_51 GEN_IO2_79

GEN_IO2_52 12 * 26

GEN_IO2_80

GEN_IO2_53 GEN_IO2_81

GEN_IO2_54 13 * 27

GEN_IO2_82

GEN_IO2_55

GEN_IO2_56 14

* = Optional Driver/Receiver

Table 9 – Low Voltage Differential Signaling Pairs (P3)

Avnet Design Services 17 of 25 Rev 1.0 06/08/2004

Released Literature # ADS-xxxx04

3.6.2 Memory Expansion Connector Interface

A memory expansion interface interconnects the memory signals to the development module for the option to implement

increased memory capabilities, different memory technologies or a host controller. In addition to the standard memory

signals, additional spare I/O signals are routed to the connector to allow for arbitration and control. Unknown bus

loading from the development module must be considered to ensure the local memory bus functionality with all types of

development modules installed. Two 140-pin connectors are paired to provide this interface. See Table 10 for memory

AvBus connector pin assignment.

Name P4

Connector

Pin # Name Name P5

Connector

Pin # Name

ADDR_AV0 71 1 +5V DATA_AV32 71 1 +5V

GND 72 2 ADDR_AV1 GND 72 2 DATA_AV33

ADDR_AV3 73 3 ADDR_AV2 DATA_AV35 73 3 DATA_AV34

ADDR_AV4 74 4 GND DATA_AV36 74 4 GND

GND 75 5 ADDR_AV5 GND 75 5 DATA_AV37

ADDR_AV7 76 6 ADDR_AV6 DATA_AV39 76 6 DATA_AV38

ADDR_AV8 77 7 GND DATA_AV40 77 7 GND

+3.3V 78 8 ADDR_AV9 +3.3V 78 8 DATA_AV41

ADDR_AV11 79 9 ADDR_AV10 DATA_AV43 79 9 DATA_AV42

ADDR_AV12 80 10 GND DATA_AV44 80 10 GND

GND 81 11 ADDR_AV13 GND 81 11 DATA_AV45

ADDR_AV15 82 12 ADDR_AV14 DATA_AV47 82 12 DATA_AV46

ADDR_AV16 83 13 +5V DATA_AV48 83 13 +5V

GND 84 14 ADDR_AV17 GND 84 14 DATA_AV49

ADDR_AV19 85 15 ADDR_AV18 DATA_AV51 85 15 DATA_AV50

ADDR_AV20 86 16 GND DATA_AV52 86 16 GND

GND 87 17 ADDR_AV21 GND 87 17 DATA_AV53

ADDR_AV23 88 18 ADDR_AV22 DATA_AV55 88 18 DATA_AV54

ADDR_AV24 89 19 GND DATA_AV56 89 19 GND

+3.3V 90 20 ADDR_AV25 +3.3V 90 20 DATA_AV57

ADDR_AV27 91 21 ADDR_AV26 DATA_AV59 91 21 DATA_AV58

ADDR_AV28 92 22 GND DATA_AV60 92 22 GND

GND 93 23 ADDR_AV29 GND 93 23 DATA_AV61

ADDR_AV31 94 24 ADDR_AV30 DATA_AV63 94 24 DATA_AV62

DATA_AV0 95 25 +5V FLASH_CE2# 95 25 +5V

GND 96 26 DATA_AV1 GND 96 26 FLASH_CE3#

DATA_AV3 97 27 DATA_AV2 SDRAM_BYTE5 97 27 SDRAM_BYTE4

DATA_AV4 98 28 GND SDRAM_BYTE6 98 28 GND

GND 99 29 DATA_AV5 GND 99 29 SDRAM_BYTE7

DATA_AV7 100 30 DATA_AV6 MEM_IO_7 100 30 MEM_IO_6

DATA_AV8 101 31 GND MEM_IO_8 101 31 GND

+3.3V 102 32 DATA_AV9 +3.3V 102 32 MEM_IO_9

DATA_AV11 103 33 DATA_AV10 MEM_IO_11 103 33 MEM_IO_10

DATA_AV12 104 34 GND MEM_IO_12 104 34 GND

GND 105 35 DATA_AV13 GND 105 35 MEM_IO_13

DATA_AV15 106 36 DATA_AV14 MEM_IO_15 106 36 MEM_IO_14

DATA_AV16 107 37 +5V MEM_IO_16 107 37 +5V

GND 108 38 DATA_AV17 GND 108 38 MEM_IO_17

DATA_AV19 109 39 DATA_AV18 MEM_IO_19 109 39 MEM_IO_18

DATA_AV20 110 40 GND MEM_IO_20 110 40 GND

GND 111 41 DATA_AV21 GND 111 41 MEM_IO_21

DATA_AV23 112 42 DATA_AV22 MEM_IO_23 112 42 MEM_IO_22

DATA_AV24 113 43 GND MEM_IO_24 113 43 GND

+3.3V 114 44 DATA_AV25 +3.3V 114 44 MEM_IO_25

Avnet Design Services 18 of 25 Rev 1.0 06/08/2004

Released Literature # ADS-xxxx04

Name P4

Connector

Pin # Name Name P5

Connector

Pin # Name

DATA_AV27 115 45 DATA_AV26 MEM_IO_27 115 45 MEM_IO_26

DATA_AV28 116 46 GND MEM_IO_28 116 46 GND

GND 117 47 DATA_AV29 GND 117 47 MEM_IO_29

DATA_AV31 118 48 DATA_AV30 MEM_IO_31 118 48 MEM_IO_30

FLASH_CE0# 119 49 +5V MEM_IO_32 119 49 +5V

GND 120 50 FLASH_CE1# GND 120 50 MEM_IO_33

FLASH_WE# 121 51 FLASH_OE# MEM_IO_35 121 51 MEM_IO_34

FLASH_RST# 122 52 GND MEM_IO_36 122 52 GND

GND 123 53 SDRAM_CS# +3.3V 123 53 MEM_IO_37

SDRAM_WE# 124 54 SDRAM_CAS# MEM_IO_39 124 54 MEM_IO_38

SDRAM_CLK 125 55 GND MEM_IO_40 125 55 GND

+3.3V 126 56 SDRAM_RAS# GND 126 56 MEM_IO_41

SDRAM_BYTE0 127 57 SDRAM_CLKEN MEM_IO_43 127 57 MEM_IO_42

SDRAM_BYTE1 128 58 GND MEM_IO_44 128 58 +5V

GND 129 59 SDRAM_BYTE2 GND 129 59 MEM_IO_45

MEM_IO_0 130 60 SDRAM_BYTE3 MEM_IO_47 130 60 MEM_IO_46

MEM_IO_1 131 61 +5V MEM_IO_48 131 61 GND

GND 132 62 MEM_IO_2 GND 132 62 MEM_IO_49

MEM_IO_4 133 63 MEM_IO_3 MEM_IO_51 133 63 MEM_IO_50

MEM_IO_5 134 64 GND MEM_IO_52 134 64 GND

GND 135 65 MEM_IO_CLKOUT +3.3V 135 65 MEM_IO_53

MEM_IO_CLKIN 136 66 MEM_IO_CLK_FB MEM_IO_55 136 66 MEM_IO_54

TMS 137 67 GND MEM_IO_56 137 67 GND

+3.3V 138 68 AV2_TDO GND 138 68 MEM_IO_57

AV2_TDI 139 69 TCK MEM_IO_59 139 69 MEM_IO_58

TRST# 140 70 GND MEM_IO_60 140 70 GND

Table 10 – Memory I/O AvBus Connector P4 & P5

Avnet Design Services 19 of 25 Rev 1.0 06/08/2004

Released Literature # ADS-xxxx04

3.6.3 Auxiliary Connectors(Available only with FF1152 package)

The additional auxilary I/O interface allows the user to adapt any desired functionality to the development kit backplane

for research and development. Connector P6 is configured for a I/O voltage (VCCO) of 2.5V and connector P7 for a

I/O voltage (VCCO) of 3.3V. The FPGA connections to these connectors utilize a high I/O interface, thus allowing the

user to select the installation requirements for the development module. Two 140-pin connectors are paired to provide

this interface. See Table 11 for general I/O AvBus connector pin assignment.

Name P6

Connector

Pin # Name Name P7

Connector

Pin # Name

V25_IO_0 71 1 +5V V33_IO_0 71 1 +5V

GND 72 2 V25_IO_1 GND 72 2 V33_IO_1

V25_IO_3 73 3 V25_IO_2 V33_IO_3 73 3 V33_IO_2

V25_IO_4 74 4 GND V33_IO_4 74 4 GND

GND 75 5 V25_IO_5 GND 75 5 V33_IO_5

V25_IO_7 76 6 V25_IO_6 V33_IO_7 76 6 V33_IO_6

V25_IO_8 77 7 GND V33_IO_8 77 7 GND

+3.3V 78 8 V25_IO_9 +3.3V 78 8 V33_IO_9

V25_IO_11 79 9 V25_IO_10 V33_IO_11 79 9 V33_IO_10

V25_IO_12 80 10 GND V33_IO_12 80 10 GND

GND 81 11 V25_IO_13 GND 81 11 V33_IO_13

V25_IO_15 82 12 V25_IO_14 V33_IO_15 82 12 V33_IO_14

V25_IO_16 83 13 +5V V33_IO_16 83 13 +5V

GND 84 14 V25_IO_17 GND 84 14 V33_IO_17

V25_IO_19 85 15 V25_IO_18 V33_IO_19 85 15 V33_IO_18

V25_IO_20 86 16 GND V33_IO_20 86 16 GND

GND 87 17 V25_IO_21 GND 87 17 V33_IO_21

V25_IO_23 88 18 V25_IO_22 V33_IO_23 88 18 V33_IO_22

V25_IO_24 89 19 GND V33_IO_24 89 19 GND

+3.3V 90 20 V25_IO_25 +3.3V 90 20 V33_IO_25

V25_IO_27 91 21 V25_IO_26 V33_IO_27 91 21 V33_IO_26

V25_IO_28 92 22 GND V33_IO_28 92 22 GND

GND 93 23 V25_IO_29 GND 93 23 V33_IO_29

V25_IO_31 94 24 V25_IO_30 V33_IO_31 94 24 V33_IO_30

V25_IO_32 95 25 +5V V33_IO_32 95 25 +5V

GND 96 26 V25_IO_33 GND 96 26 V33_IO_33

V25_IO_35 97 27 V25_IO_34 V33_IO_35 97 27 V33_IO_34

V25_IO_36 98 28 GND V33_IO_36 98 28 GND

GND 99 29 V25_IO_37 GND 99 29 V33_IO_37

V25_IO_39 100 30 V25_IO_38 V33_IO_39 100 30 V33_IO_38

V25_IO_40 101 31 GND V33_IO_40 101 31 GND

+3.3V 102 32 V25_IO_41 +3.3V 102 32 V33_IO_41

V25_IO_43 103 33 V25_IO_42 V33_IO_43 103 33 V33_IO_42

V25_IO_44 104 34 GND V33_IO_44 104 34 GND

GND 105 35 V25_IO_45 GND 105 35 V33_IO_45

V25_IO_47 106 36 V25_IO_46 V33_IO_47 106 36 V33_IO_46

V25_IO_48 107 37 +5V V33_IO_48 107 37 +5V

GND 108 38 V25_IO_49 GND 108 38 V33_IO_49

V25_IO_51 109 39 V25_IO_50 V33_IO_51 109 39 V33_IO_50

V25_IO_52 110 40 GND V33_IO_52 110 40 GND

GND 111 41 V25_IO_53 GND 111 41 V33_IO_53

V25_IO_55 112 42 V25_IO_54 V33_IO_55 112 42 V33_IO_54

V25_IO_56 113 43 GND V33_IO_56 113 43 GND

+3.3V 114 44 V25_IO_57 +3.3V 114 44 V33_IO_57

V25_IO_59 115 45 V25_IO_58 V33_IO_59 115 45 V33_IO_58

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Released Literature # ADS-xxxx04

Name P6

Connector

Pin # Name Name P7

Connector

Pin # Name

V25_IO_60 116 46 GND V33_IO_60 116 46 GND

GND 117 47 V25_IO_61 GND 117 47 V33_IO_61

V25_IO_63 118 48 V25_IO_62 V33_IO_63 118 48 V33_IO_62

V25_IO_64 119 49 +5V V33_IO_64 119 49 +5V

GND 120 50 V25_IO_65 GND 120 50 V33_IO_65

V25_IO_67 121 51 V25_IO_66 V33_IO_67 121 51 V33_IO_66

V25_IO_68 122 52 GND V33_IO_68 122 52 GND

GND 123 53 V25_IO_69 GND 123 53 V33_IO_69

V25_IO_71 124 54 V25_IO_70 V33_IO_71 124 54 V33_IO_70

V25_IO_72 125 55 GND V33_IO_72 125 55 GND

+3.3V 126 56 V25_IO_73 +3.3V 126 56 V33_IO_73

V25_IO_75 127 57 V25_IO_74 V33_IO_75 127 57 V33_IO_74

V25_IO_76 128 58 GND V33_IO_76 128 58 GND

GND 129 59 V25_IO_77 GND 129 59 V33_IO_77

V25_IO_79 130 60 V25_IO_78 V33_IO_79 130 60 V33_IO_78

V25_IO_80 131 61 +5V V33_IO_80 131 61 +5V

GND 132 62 V25_IO_81 GND 132 62 V33_IO_81

V25_IO_83 133 63 V25_IO_82 V33_IO_83 133 63 V33_IO_82

V25_IO_84 134 64 GND V33_IO_84 134 64 GND

GND 135 65 GND 135 65 V33_IO_85

136 66 LED0 136 66 V33_IO_86

137 67 GND LED1 137 67 GND

+3.3V 138 68 +3.3V 138 68 LED2

139 69 LED4 139 69 LED3

140 70 GND LED5 140 70 GND

GND

Table 11 – Auxiliary AvBus Connector P6 & P7

3.6.4 Miscellaneous Connectors

• Various support connectors are installed for I/O, power, and programming for the backplane.

• Power connectors include a +5V barrel type connector for sourcing the power regulators and on board circuitry.

• For programming the FPGA, a Xilinx parallel/serial connector (Parallel III & MultiLINX) and a JTAG connector

(Parallel IV) are provided.

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