Avnet Xilinx virtex-ii User manual

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user’s guide

Xilinx Virtex-II Development Kit

Avnet Design Services 2 of 25 Rev 1.0 06/08/2004

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Table of Contents

Xilinx Virtex-II Development Kit.................................................................................................................................................................1

Table of Contents.............................................................................................................................................................................................2

Figures ................................................................................................................................................................................................................3

Tables..................................................................................................................................................................................................................3

1.0 Introduction.....................................................................................................................................................................................4

1.1 Description..................................................................................................................................................................................4

1.2 Features:.......................................................................................................................................................................................4

1.3 Demo Applications:...................................................................................................................................................................4

1.4 Ordering Information: ..............................................................................................................................................................5

2.0 User Information............................................................................................................................................................................5

2.1 Power...........................................................................................................................................................................................5

2.2 Configuration..............................................................................................................................................................................5

2.2.1 Boundary scan Configuration..............................................................................................................................................6

2.2.2 System ACE MPM Configuration......................................................................................................................................6

2.2.3 SelectMAP and Custom Configuration Methods.............................................................................................................6

2.2.4 Configuration Modes............................................................................................................................................................7

2.2.5 JTAG Chain...........................................................................................................................................................................8

2.3 Jumper Settings...........................................................................................................................................................................9

3.0 Hardware........................................................................................................................................................................................11

3.1 Virtex-II FPGA........................................................................................................................................................................12

3.1.1 LVDS.....................................................................................................................................................................................12

3.2 Memory......................................................................................................................................................................................12

3.2.1 DDR SDRAM .....................................................................................................................................................................12

3.2.2 Flash.......................................................................................................................................................................................12

3.3 Communication........................................................................................................................................................................12

3.3.1 RS232 Transceiver...............................................................................................................................................................12

3.4 LED ...........................................................................................................................................................................................13

3.5 Dip Switches.............................................................................................................................................................................13

3.6 Connectors................................................................................................................................................................................13

3.6.1 General I/O Interface........................................................................................................................................................14

3.6.1.1 LVDS ...........................................................................................................................................................................16

3.6.2 Memory Expansion Connector Interface........................................................................................................................17

3.6.3 Auxiliary Connectors(Available only with FF1152 package) .......................................................................................19

3.6.4 Miscellaneous Connectors .................................................................................................................................................20

3.7 PCI/PCIX.................................................................................................................................................................................21

3.8 Evaluation Boards....................................................................................................................................................................23

3.9 Extender Card Board ..............................................................................................................................................................23

3.10 Power.........................................................................................................................................................................................23

3.10.1 FPGA I/O Voltage (Vcco)...........................................................................................................................................23

3.10.2 FPGA Reference Voltage (Vref)..................................................................................................................................23

3.11 Configuration Modes...............................................................................................................................................................23

4.0 Test Designs..................................................................................................................................................................................24

4.1 On-board Flash Test...............................................................................................................................................................25

4.2 PCI/PCI-X Test.......................................................................................................................................................................25

4.3 Switch/LED Test ....................................................................................................................................................................25

4.4 Avbus Connector Test............................................................................................................................................................25

4.5 DDR SDRAM Test.................................................................................................................................................................25

5.0 Example VHDL Project..............................................................................................................................................................25

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Figures

Figure 1 - Fly Wire Connection J2.................................................................................................................................................................6

Figure 2 - JTAG Chain.....................................................................................................................................................................................8

Figure 3 – JP1....................................................................................................................................................................................................9

Figure 4 - I/O Voltage Selection....................................................................................................................................................................9

Figure 5 - Virtex-II Development Board Block Diagram........................................................................................................................11

Figure 6 - Virtex-II Development Board....................................................................................................................................................11

Figure 7 - Barrel Power Connector "J4".....................................................................................................................................................23

Tables

Table 1: Ordering Information.......................................................................................................................................................................5

Table 2 - JTAG Headers (JTAG3 & JTAG4) Pin-Out..............................................................................................................................6

Table 3 - Virtex-II Power-up Configuration Modes...................................................................................................................................7

Table 4 - JTAG Boundary-Scan Description Language (BSDL) files......................................................................................................8

Table 5 - RS232 Connector Pin-out ............................................................................................................................................................12

Table 6 – LED Pin Assignment @ the FPGA..........................................................................................................................................13

Table 7 –Switch Pin Assignment @ the FPGA.........................................................................................................................................13

Table 8 – General I/O AvBus Connector P2 & P3.................................................................................................................................15

Table 9 – Low Voltage Differential Signaling Pairs (P3)..........................................................................................................................16

Table 10 – Memory I/O AvBus Connector P4 & P5 ..............................................................................................................................18

Table 11 – Auxiliary AvBus Connector P6 & P7......................................................................................................................................20

Table 12 – PCI/PCI-X Connector Pin Assignment and Interface Signals...........................................................................................22

Table 13 – Virtex-II Power-up Configuration Modes..............................................................................................................................24

Table 14 – System ACE Test Designs.........................................................................................................................................................24

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1.0 Introduction

The purpose of this manual is to describe the functionality and contents of the Virtex-II Development Kit from Avnet Design

Services. This document includes instructions for operating the board, descriptions of the hardware features and explanations

of the example projects.

1.1 Description

The Virtex-II Development Kit provides a complete hardware environment for designers to accelerate their time to market.

The kit delivers a stable platform to develop and test designs targeted to the highly advanced Xilinx Virtex-II FPGA family.

The installed XC2V1500 device offers a 1.5M system gate prototyping environment to effectively demonstrate the enhanced

benefits of the leading edge Xilinx FPGA solution. Embedded multipliers, advanced digital clock management, built-in

impedance matching, IP immersion, and other exciting features can be implemented with advanced Xilinx design tools.

Demonstration VHDL code is included with the kit to exercise standard peripherals on the evaluation board for a quick start

to device familiarization.

1.2 Features:

! FPGA

! Xilinx Virtex-II XC2V1500-FF896

! Board I/O Connectors

! Four 140-pin general purpose I/O expansion connectors (AvBus)

! +3.3V/+5V, 64-bit 66/100 MHz PCI/PCI-X interface

! 50 – Pin 0.1” Header

! Memory

! Micron DDR SDRAM DIMM (128MB)

! Flash Memory (16MB)

! Communication

! RS-232 serial ports

! Power

! Regulated 3.3V, 2.5V, 1.8V and 1.5V supply voltages generated from external 5V supply

! Configuration

! Xilinx XCCACEMxx-BG388I System ACE MPM Solution

! Parallel IV Cable support for JTAG

! Fly-wire support for Parallel-III and Multilinx.

1.3 Demo Applications:

The Virtex-II Development Kit from Avnet Design Services comes with test application designs used as base tests for the

peripherals on the board. The peripheral example designs, listed below, are discussed in detail in section 4.0.

! Flash test

! PCIX test

! LED test

! Connector Test

! DDR SDRAM Memory test

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1.4 Ordering Information:

The following table lists the Development system part numbers and available software options. Internet link at:

http://www.ads.avnet.com

Part Number Hardware

ADS-XLX-V2-DEV1500 Xilinx Virtex-II Development Kit populated

with an XC2V1500 device

ADS-XLX-MB-DEV1500 Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module and

MicroBlaze Core License

ADS-XLX-V2-DEV1500XP Xilinx Virtex-II Development Kit populated

with an XC2V1500 device & high-current

power supply

ADS-V2-MB-DEV1500XP

Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module,

MicroBlaze Core License & high-current

power supply

ADS-XLX-V2-DEV4000 Xilinx Virtex-II Development Kit populated

with an XC2V4000 device

ADS-XLX-MB-DEV4000 Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module and

MicroBlaze Core License

ADS-XLX-V2-DEV4000XP Xilinx Virtex-II Development Kit populated

with an XC2V4000 device & high-current

power supply

ADS-V2-MB-DEV4000XP

Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module,

MicroBlaze Core License & high-current

power supply

ADS-XLX-V2-DEV6000XP Xilinx Virtex-II Development Kit populated

with an XC2V6000 device & high-current

power supply

ADS-V2-MB-DEV6000XP

Xilinx Virtex-II Development Kit bundled

with Communications/Memory Module,

MicroBlaze Core License & high-current

power supply

Table 1: Ordering Information

2.0 User Information

This section provides the user with information on how to get started using the Virtex-II Development board. It discusses

how to apply power to the board, configure the FPGA devices and set-up the jumpers.

2.1 Power

The Virtex-II Development Board is powered via the +5.0 volt PCI. However, it may be operated in stand-alone mode. In

stand-alone mode the Virtex-II board may be powered by an external power supply connected to the J1 barrel socket

connector. The supply should have a minimum of 2 AMP, +5.0 Volts regulated to +/- 5%. The current requirements for

the board are application specific.

2.2 Configuration

The Virtex-II Development board supports Boundary-scan as well as System ACE Multi-Package Module (MPM) solution. All

configuration pins are brought out to “J2”, should the user wish to program with an alternate method.

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2.2.1 Boundary scan Configuration

Programming the Virtex-II FPGA via Boundary-scan requires a JTAG download cable (not included in the kit). The Virtex-II

Development board has connectors to support both the flying leads connection of the Parallel Cable III and MultiLINX

cables, and the ribbon cable connection of the Parallel Cable IV. These connectors are labeled “J2” and “U25” respectively.

For more information about JTAG download cables see the Xilinx web page http://www.xilinx.com. Click on the

“Products” tab and then click on the “Configuration” link. Scroll down to “Desktop Programmers and Download Cables”

and select the download cable of interest.

When using the flying leads connection of the Parallel Cable III or MultiLINX, connect the leads as indicated for “J2”. These

connections are shown in Table 2 below.

Signal Name JTAG3 (J2) pin JTAG4 (JU25) pin

VCC 20 2

TDI 9 10

TDO 15 8

TMS 13 4

TCK 11 6

GND 19, 21 1,3,5,7,9,11 or 13

Table 2 - JTAG Headers (JTAG3 & JTAG4) Pin-Out

If the Parallel Cable IV is used, the ribbon cable connector mates with the JTAG4 (U25) connector. The connectors are keyed

to ensure the connections are made correctly. Table 2 also shows the pin-out of the JTAG4 connector..

2.2.2 System ACE MPM Configuration

The System ACE Multi-Package Module (MPM) is a configuration solution for high density FPGAs. Configuration files

for the target FPGA are programmed into the MPM using the iMPACT software and a JTAG download cable. The MPM

is a combination of three devices: a configuration PROM, a small Virtex-E FPGA and an industry-standard Flash device.

The PROM contains the configuration controller design that is loaded into the Virtex-E “controller” on power-up. The

controller handles reading the selected configuration file out of the Flash and programming the target FPGA, in this case,

the Virtex-II FPGA. The System ACE MPM can hold multiple bitstreams. The iMPACT software is used to generate a

single configuration file for the System ACE that contains all of the bitstreams and their corresponding controller address.

The MPM can hold 8 different designs, which are selected by setting the controller address. The address is set by

installing shunts/jumpers on JP103. For a description of the test files see Section 4.0.

2.2.3 SelectMAP and Custom Configuration Methods

The Viretx-II Development Board provides the user with an interface to the FPGA dedicated and dual function programming

pins. This provides fly-wire support for SelectMAP programming with MultiLINX, and gives flexibility for developing a

custom programming solution. Programming pins are provided with J2 as shown in Figure 1.

TDI

TCK

TMS

TDO

GND

GND VCC

CS_B

DONE

PROG_B

INIT_B

BUSY/DOUT

RDWR_B

CCLK

Figure 1 - Fly Wire Connection J2

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2.2.4 Configuration Modes

Upon power-up the FPGA will be enabled in a configuration mode defined by jumper header JP1. The default

configuration mode is “Master-Serial” mode, which will allow the FPGA to be programmed from the System ACE MPM.

The System ACE has been programmed with basic test application code to test the on-board peripherals. Section 4.0

describes the various tests included with the System ACE. Table 3 describes the various configuration modes available by

setting the appropriate jumper/mode select.

Configuration

Mode

JP1

(1-2)

JP1

(3-4)

JP1

(5-6)

* Master serial OPEN OPEN OPEN

Slave serial JUMPERED JUMPERED JUMPERED

Master SelectMAP OPEN JUMPERED JUMPERED

Slave SelectMAP JUMPERED JUMPERED OPEN

Boundary-scan JUMPERED OPEN JUMPERED

* = Default assembled state

Table 3 - Virtex-II Power-up Configuration Modes

JP1

Mode 0

Mode 1

Mode 2

JP1

Mode 0

Mode 1

Mode 2

Master Serial Mode:

No Jumpers on JP2

Master SelectMAP mode:

place jumpers at JP2

positions 1-2 & 3-4.

JP1

Mode 0

Mode 1

Mode 2

For Boundary Scan mode,

place jumpers at JP2

positions 1-2 & 5-6.

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2.2.5 JTAG Chain

The Virtex-II development board has two (2) devices in its JTAG chain (FPGA and System ACE MPM). The JTAG chain is

implemented as shown in Figure 2. The BSDL files for each device in the chain are given on Table 4.

* = Bypassed

Virtex

II JTAG Scan Chain Path

FPGA PROM No. 1

PROM No. 5

GEN IO CONNMEM CONN

FPGA_TDI

PCIX_TDO

MEM IO GEN IO 1

PCI/PCIX

FPGASystem ACE

J2 *

FPGA TDO

AV1_TDI

AV1_TDO

JTAG_TDO

(U25)

** = Jumper selectable w/ JP100

PROM No. 1

JP100

JTAG Chain Selection

JTAG_TDI

AV2_TDIAV2_TDO

Figure 2 - JTAG Chain

File Name Device Device Reference

Designator

XC2V1500_FF896.bsd FPGA U1

XC2V4000_FF1152.bsd FPGA U1

XCCACEMxx_BG388.bsd SYSTEM

ACE U5

Table 4 - JTAG Boundary-Scan Description Language (BSDL) files

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2.3 Jumper Settings

This section provides a description of the jumper settings for the Development board. The board is ready to use out of the

box with the default jumper settings.

JP1 – Configuration mode selection. Use to select the configuration mode for the FPGA. By default, these pins are pulled

low enabling Master Serial mode. Installing jumpers on JP1 will pull the corresponding mode pin high, as indicated in Figure 3.

See the Configuration section of this document or Chapter 3 of the Virtex-II Platform FPGA Handbook for further

information.

JP1

Mode 0

Mode 1

Mode 2

1-2 M1

3-4 M2

5-6

Master Serial

Slave Serial

Master SelectMAP

Slave SelectMAP

Boundary Scan

JP1

ConfigMode

Figure 3 – JP1

U25 – Parallel IV connector. See the Boundary scan section of this document for more information

JP2, JP12, & JP13 – Vcco selectable voltages are available on the Virtex-II Development Board to support the FPGAs various

voltage standards. The Virtex-II Development Board provides various selectable I/O voltages for FPGA banks 0,1,4 & 5,

independent of each other, to support the various I/O standards. The I/O voltages available are +3.3V, +2.5V, +1.8V and

+1.5V. JP2 selects I/O voltage for Banks 4&5; JP12 for Bank0, and JP13 for Bank1. Only one jumper should be placed at

each connector. Valid placements, per connector, are 1-2, 3-4, 5-6 or 7-8 as indicated in Figure 4

JP2

3.3V

2.5V

1.8V

2.5V

3-4 1.8V

5-6 1.5V

7-8

Jumper Position

I/O Voltage 3.3V

1-2

1.5V

Figure 4 - I/O Voltage Selection

JP4 – HSWAP_EN, Enables pull-ups on the Virtex-II I/O pins during configuration. Install a jumper to enable the

configuration pull-ups. Default: Open; pull-ups disabled.

JP5 – Access to temperature sensing diode pins of FPGA (DXP, DXN)

JP6, JP7, & JP8 - The PCI power jumper. When the jumpers are installed, they configure the board for PCI power mode, and

utilizes the +5Vdc from the PCI motherboard.

JP14 – Bank 0 Voltage Reference(Vref) selection. Selects Vref voltage for FPGA banks 0. The reference voltages available are

+1.65V, +1.25V, +.9V, +.75V and +1.5V (half the I/O voltage, and +1.5V which is jumper selected). Jumper 1-2 assigns

+1.5V as Bank0 Vref. Jumper 2-3 assigns half of I/O voltage selected with JP12 as Bank 0 Vref.

JP15 – Bank 1 Voltage Reference(Vref) selection. Selects Vref voltage for FPGA banks 1. The reference voltages available are

+1.65V, +1.25V, +.9V, +.75V and +1.5V (half the I/O voltage, and +1.5V which is jumper selected). Jumper 1-2 assigns

+1.5V as Bank1 Vref. Jumper 2-3 assigns half of I/O voltage selected with JP13 as Bank 1 Vref.

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JP16 – 50-pin FPGA general purpose header I/O.

JP17 – 20-pin FPGA general purpose 2.5V I/O header.

JP18 – 20-pin FPGA general purpose 3.3V I/O header.

JP19– 20-pin FPGA general purpose memory header.

JP100- JTAG Chain configuration. Selects the JTAG chain configuration. Install a jumper across pins 2-3 for standalone

mode (3 devices in chain: System ACE, Virtex-II, and PCIX). Install jumpers across pins 1-2 and pins 4-5 to add the AvBus

connector labeled “P2” on to the standalone chain. Install jumpers across pins 1-2, pins 3-4 and pins 5-6 to add the AvBus

connector labeled “P3” on to the standalone chain. These settings are described in detail in the Hardware section of this

manual (see section 3.11).

Default: Installed across pins 2-3; standalone chain mode.

JP101 – JTAG TCK Enable for JTAG Connector "P2". Default Closed.

JP102 – JTAG TCK Enable for JTAG Connector "P4". Default Closed.

JP103 – System ACE Test Control Address. The MPM file in the System ACE can hold 8 different designs, which are selected

by setting the controller address. The address is set by installing shunts/jumpers on JP103. For a description of the test files

see Section 4.0

JP104– System ACE Device Disable. Default Open.

JP904 – JTAG bypass ties board TDI to TDO, bypassing all devices. Default Open, JTAG chain enabled.

J100 – Active Heatsink Power.

J102 – 50-pin general purpose System ACE header.

J103 – Connector for Power Supply Daughter board.

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