Denon DN-C680 User manual

SERVICE MANUAL
CD PLAYER
For U.S.A., Canada &
Europe model
16-11, YUSHIMA 3-CHOME, BUNKYOU-KU, TOKYO 113-0034 JAPAN
X0179V.01 DE/CDM 0308
Some illustrations using in this service manual are
slightly different from the actual set.
●
Please use this service manual with referring to the
operating instructions without fail.
●
●
本文中に使用しているイラストは、説明の都合上現物
と多少異なる場合があります。
●
修理の際は、必ず取扱説明書を参照の上、作業を行っ
てください。
サービスをおこなう前に、このサービスマニュアルを
必ずお読みください。本機は、火災、感電、けがなど
に対する安全性を確保するために、さまざまな配慮を
おこなっており、また法的には「電気用品安全法」に
もとづき、所定の許可を得て製造されております。
従ってサービスをおこなう際は、これらの安全性が維
持されるよう、このサービスマニュアルに記載されて
いる注意事項を必ずお守りください。
注 意
SUPPLEMENT
MODEL DN-C680
Ver. 1
We have two version of DN-C680. The new version of
DN-C680 is replaced discontinued parts of the old ver-
sion. (CD mechanism, microprocessor and D/A conver-
ter etc.)
Serial number of new version are renumbered from
*****50001.
This service manual is supplement for new version of
DN-C680 and only mentioned difference between old
and new version. So, please refer to previously issued
service manual of DN-C680 when servicing.
DN‑C680には新旧の2つのバージョンがあります。
旧 バージョン( 製造番号*****50000以前)で生産中止に
なった部品(CDメカ、マイコン等)を置き換えたものが
新バージョン (製造番号*****50001以降)です。
本書は、
新バージョンで 変更された内容のみを記載し
ていますので、
サービスの際は本書と共に 既発行のサ
ービスマニュアル
DN‑C680を ご用意願います。
●
本機の仕様は性能改良のため、予告なく変更すること
があります。
●
新バージョン用の補修用性能部品の保有期間は、製造
打切後8年です。
For purposes of improvement, specifications and
design are subject to change without notice.
●

2
2DN-C680
SAFETY PRECAUTIONS
The following check should be performed for the continued protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the
power cord is less than 460 kohms, the unit is defective.
LASER RADIATION
Do not stare into beam or view directly with optical instruments, class 3A laser product.
(1)
(2)
500V
1M
(1)
(2)

3
3DN-C680
BLOCK DIAGRAM
M66005AFP
AN22002A
ACD25
ACD27
RS-232C
RS-232C
RS-422ARS-422A
MN102H60KDA
XCS05XL PCM1738
4M DRAM
YM3437
Not use
NJM5532
HD26C32A
HD26LS31FP
NJM5532
+7V_D1 +6V
+3.3V_D1 +3.3V
+5V_A2
+5V_A1
- 12V_A
+12V_A +16V_A
FOR DSP, MECHA
GU-3578-1
GU-3578-2
GU-3578-3

4
4DN-C680
CONFIRMING THE SERVO
CAUTION:
The Optical Pick-up used for CD player may invite defection by an external noise, such as electrostatic, etc.,
please pay the following attention.
1. Use a conductive mat on a working table to avoid electrostatic damage.
2. A working personnel should use a wrist strap to ground human body.
3. Tools, etc., specially for a soldering iron must use with its tip grounded and without leakage of electricity.
Utmost care must be taken to your clothes for electrostatic damaging in a low humidity environment.
Required Measuring Implement
1. Dual trace oscilloscope
2. Reference disc (TCD784 or CO-74176)
1. Actuating the Service Program and Servo Confirming Method
1. Turn the power switch off.
2. While simultaneously pushing the STANDBY/CUE button and PLAY/PAUSE button, turn the power on.
3. Displayed indication is version number of microcomputer program.
4 figures on the left are program version of remote control, and 4 figures on the right are program version of main body
mechanism.
4. Turn SELECT knob. Display shows " " and each pressing of PLAY button opens or closes the tray.
5. As the tray opens, set the adjustment disc (TCD784 or CO-74176)
6. Turn SELECT knob (" " is displayed), also, press PLAY/PAUSE button.
Tracking error signal can be observed with the connection below. (Fig1)
7. Turn SELECT knob (" " is displayed), also, press PLAY/PAUSE button.
HF signal can be observed with the connection below. (Fig2)
8. Turn SELECT knob (" " is displayed), also, press PLAY/PAUSE button.
By pressing button servo automatic adjustment value can be called. (Ref. Table below)
TP101
1
2
3
4
Oscilloscope
5
6
NC
VREF
HF
TE
NC
FE
TP101
1
2
3
4
Oscilloscope
5
6
NC
VREF
HF
TE
NC
FE
Fig1 Fig2
TRACK Portion
Indication
Ad
j
ustment
Item
Ad
j
ustment Value
indication
at S and F
p
ortions.
Ad
j
ustment Item
No. indication
at M
p
ortion.
Error Code 00
Focus Gain (FG) 125 ~728 01
Focus Balance (FBAL) 120~ 12002
Focus Offset (FOFS) 57 ~ 57 03
Tracking Gain (TG) 101~ 808 04
Tracking Balance (TBAL) 105 ~ 105 05
04
Tracking Offset (TOFS) 31 ~ 31 06
* When adjustment range exceeds, replace pick-up.
3. Turn SELECT knob. Display shows " " and each pressing of PLAY button opens or closes the tray.
4. As the tray opens, set the adjustment disc (TCD784 or CO-74176)
5. Turn SELECT knob (" " is displayed), also, press PLAY/PAUSE button.
Tracking error signal can be observed with the connection below. (Fig1)
6. Turn SELECT knob (" " is displayed), also, press PLAY/PAUSE button.
HF signal can be observed with the connection below. (Fig2)
7. Turn SELECT knob (" " is displayed), also, press PLAY/PAUSE button.
By pressing button servo automatic adjustment value can be called. (Ref. Table below)
TP101
1
2
3
4
Oscilloscope
5
6
NC
VREF
HF
TE
NC
FE
TP101
1
2
3
4
Oscilloscope
5
6
NC
VREF
HF
TE
NC
FE
Fig1 Fig2
TRACK Portion
Indication
Ad
j
ustment
Item
Ad
j
ustment Value
indication
at S and F
p
ortions.
Ad
j
ustment Item
No. indication
at M
p
ortion.
Error Code 00
Focus Gain (FG) 125 ~728 01
Focus Balance (FBAL) 120~ 12002
Focus Offset (FOFS) 57 ~ 57 03
Tracking Gain (TG) 101~ 808 04
Tracking Balance (TBAL) 105 ~ 105 05
04
Tracking Offset (TOFS) 31 ~ 31 06
* When adjustment range exceeds, replace pick-up.

5
5DN-C680
2. What is Service Program
Service program is a special program intended for confirming servo.
3. Contents of Service Program
While simultaneously pushing the STANDBY/CUE and PLAY/PAUSE buttons, turn the power on. (TRACK Indication “00”)
After actuating the service program, select an aiming process number with the SELECT KNOB, PITCH button, and TIME
button, and push the PLAY/PAUSE button to execute processing, The process number is then displayed on the TRACK
indication portion.
Work No.
(TRACK
Indication)
Function Contents
01 OPEN/CLOSE Performs OPEN/CLOSE each tome when the PLAY/PAUSE button is pushed.
02 Tracking Error Check tracking error signal, then performs the Automatic Adjustment.
03 HF Signal Check HF signal.
04 Automatic
Adjustment call Turn the Search dial to display the Automatic adjustment data.
05 Cleaning of
Pick-up Lens Tray opens and pick-up moves out of mechanism, and clean the lens.
06
Focus Gain Changing Select Gain with search dial. Press PLAY/PAUSE button, the display lights that will
be newly memory in EEPROM.
when select data becomes big or small, the Gain is up or down.
In normally, do not change the data that is setted by 750.0.
The set No. and frequency in the EEPROM are storred as below:
No. Frequency No. Frequency
(SEC indicator) (FRAME indicator) (SEC indicator) (FRAME indicator)
- 7 477 Hz 1 847 Hz
- 6 509 Hz 2 956 Hz
- 5 543 Hz 3 1079 Hz
- 4 579 Hz 4 1218 Hz
- 3 618 Hz 5 1375 Hz
- 2 659 Hz 6 1552 Hz
- 1 703 Hz 7 1753 Hz
0 750 Hz 8 1978 Hz
SELECT knob
07
Tracking Gain
Changing
Select Gain with Search dial. Press PLAY/PAUSE button, the display lights that will
be newly memory in EEPROM.
When select data becomes big or small, the Gain is up or down.
In normally, do not change the data that is setted by 1000.0.
When sound out is occured by oscillation, please raise gain.
But there is sound out easily by defective disc.
The set No. and frequency in the EEPROM are storred as below:
No. Frequency No. Frequency
(SEC indicator) (FRAME indicator) (SEC indicator) (FRAME indicator)
- 7 637 Hz 1 1129 Hz
- 6 679 Hz 2 1274 Hz
- 5 724 Hz 3 1439 Hz
- 4 772 Hz 4 1624 Hz
- 3 824 Hz 5 1834 Hz
- 2 879 Hz 6 2070 Hz
- 1 938 Hz 7 2337 Hz
0 1000 Hz 8 2638 Hz
PITCH 08 CHUCKING Test Repeats OPEN/CLOSE of tray, servo ON, and TOC read and displays the number
of the tray OPEN/CLOSE times with the Time indicator.
TIME 09 Heat Run
(No Skip Check)
Repeats OPEN/CLOSE of tray, repeats playing the first and the last programs of
music on the disc. When an error occurs, displays error code and stops.
REPEAT 11 Error code check
Turn the search dial to display the logging error codes in the occurred order.
Kinds of displayed Error Code
(1) Error Code Table (Appears only at Heat Run and Chucking Test function)
(2) E204 Servo down during Cue
(3) E205 Servo down during pause
(4) E206 Servo down during manual search and scan
(5) E214 Unable to read the subcode during CUE
(6) E215 Unable to read the subcode during PAUSE
(7) E216 Unable to read the subcode during the manual serach and scan

6
6DN-C680
Error Code Table (Appears only at Heat Run and Chucking Test function
Error Code at TRACK portion Contents No. at m portion Contents
E1
00
01
02
03
04
05
06
Automatic Adjustment Error
Unable to detect disc
Unable to adjust tracking offset
Unable to adjust focus offset
Unable to adjust focus fine gain
Unable to actuate focus
Unable to actuate tracking
Unable to adjust tracking fine gain
E2
00
01
02
03
10
11
12
Servo down during playback
Servo down during search
Servo down during automatic adjustment
Servo down during TOC read
Unable to read the subcode between 500 msec. during the playback
Unable to read the subcode between 1 sec. during the search
Unable to read the subcode between 500 msec. during the TOC read
E3 Unable to read TOC
E4 00
01
Unable to close the disc holder in the regular time
Unable to open the disc holder in the regular time
E5 Slide error
E6 Sound skip error (only at the sound skip check)
Detailed error can be display by select knob when error occurs.
Error indication
TR MIN SEC FRAM
Error Code Contents No.
Accumulated number of open/close
function of the tray prior to Error
occures.
Indication state when error occurs
01 FG data
02 FBAL data
03 FOFS data
04 TG data
05 TBAL data
06 TOFS data

7
7DN-C680
CONFIRMING THE AUDIO
1. Necessary Equipment for Adjustment
Distortion--Factor Meter
VTVM
Low-Pass Filter (20kHz)
Reference Disc; DENON Audio Technical CD (38C39-7174)
2. Prior to Starting the Adjustment
1) Audio circuit shall be adjusted after adjustment of servo circuit.
3. Output Level Adjustment
1) Connect VTVM to the output connector of DN-C680.
Use 1:1 600 ohm Audio Transformer between the unit and VTVMs in order for matching the unbalanced input of VTVM
and the active bakanced output of DN-C680 as shown in figure.
LPF
(20kHz)
Audio Transformer
1:1
600ohm
Distortion Mete
r
Line Out
DN-C680
Connection for Output Level Adjustment
2) Play track number "49".
3) While reading VTVM indication, adjust VR407 (L-ch) and VR408 (R-ch) so that the output level attains +18dBm
(or desired level).
RL
VR408 VR407
Location of Level Adjustment VRs

8
8DN-C680
SEMICONDUCTORS
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
主な半導体を記載しています。汎用の半導体は記載を省略しています。
1. IC’s
Note : Abbreviation ahead of IC No. indicates the name of P.W.B., etc.
注 ): ICNo. の前の記号は、基板の名称を表します。
MA : Main P.W.B.
DK : Display/Key P.W.B.
MN102H60KDA (MA: IC137)
MN102H60KDA Terminal Function
Pin
No. Port Name Symbol I/O DET Ext Res Ini Note
1 P60,WAIT,SBT2 CDMUTE O Lv Pu H H DSP(MN662724) control signal:Mute 'H':Mute
2 -RE -RE O - Pu H - Read signal
3 -WEL,P62 -WE O - Pu H - Write signal
4 -WE,P63 -SMRDY I Lv Pu H - ACD27(SMPTE option unit) control signal:Ready
5 -CS0 -CS0 O - Pu H L Chip select signal(CS0:Flash ROM)
6 -CS1,P51,TMI30B -CS1 O - Pu H - Chip select signal(CS1:IO Expander port0-3)
7 -CS2,P52,TMI40A -CS2 O - Pu H - Chip select signal(CS2:IO Expander port4-7)
8 -CS3,P53,TMI40B -CS3 O - Pu H - Chip select signal(CS3:ACD27(SMPTE option unit))
9 P54,-BREQ ROMCLK O - Pu H - EEPROM(S24C04) control signal:Clock
10 P55,-BRACK ROMDAT I/O - Pu H - EEPROM(S24C04) control signal:Data
11 P56,-BSTRE,TMI51A P56 - - - - - Not used. Open
12 -WORD -WORD IN - H H H Data bit bus width select 'H':8bit
13 A0 A0 O - - Unfix - Address bus
14 A1 A1 O - - Unfix - Address bus
15 A2 A2 O - - Unfix - Address bus
16 A3 A3 O - - Unfix - Address bus
17 Vdd VDD - - - - - Power supply(+3.3V)
18 fosc,PB0,BIBT1,BIBT2 TRCK O - - fosc - DIT(YM3437C) control signal:Clock
19 Vss Vss - - - - - GND(0V)
20 XI,PB1 TRDAT O - Pu H - DIT(YM3437C) control signal:Data
21 XO XO - - - - - Not used. Open
22 Vdd Vdd - - - - - Power supply(+3.3V)
23 OSCI OSCI I - - - - X'tal input(12.288MHz)
24 OSCO OSCO O - - - - X'tal output(12.288MHz)
25 MODE MODE I - L L L Mode select 'L':Processor mode
26 A4 A4 O - - Unfix - Address bus
27 A5 A5 O - - Unfix - Address bus
28 A6 A6 O - - Unfix - Address bus
75
76
100
125
26
50
51

9
9DN-C680
29 A7 A7 O - - Unfix - Address bus
30 A8 A8 O - - Unfix - Address bus
31 A9 A9 O - - Unfix - Address bus
32 A10 A10 O - - Unfix - Address bus
33 A11 A11 O - - Unfix - Address bus
34 AVdd AVdd - - - - - Analog power supply(+3.3V)
35 A12 A12 O - - Unfix - Address bus
36 A13 A13 O - - Unfix - Address bus
37 A14 A14 O - - Unfix - Address bus
38 A15 A15 O - - Unfix - Address bus
39 A16,P40 A16 O - - Unfix - Address bus
40 A17,P41 A17 O - - Unfix - Address bus
41 A18,P42 A18 O - - Unfix - Address bus(Not used.)
42 A19,P43 A19 O - - Unfix - Address bus(Not used.)
43 VREF- VREF- - - - - - Analog reference voltage supply
44 A20,P44,AN4 A20 O - - Unfix - Address bus
45 A21,P45,AN5 A21 O - - Unfix - Address bus
46 A22,P46,AN6,STOP CCLK O - - - H FL DRIVER(M66005),LED DRIVER(NJU3713),PARALLEL
DRIVER(NJU3715) control signal:Clock
47 A23,P47,AN7,WDOUT CDAT O - - - H FL DRIVER(M66005),LED DRIVER(NJU3713),PARALLEL
DRIVER(NJU3715) control signal:Data
48 P80,TMI40A -LDC I - - - - FPGA(XCS05XL) control signal:Ldc(not used)
49 P81,TMI40B DONE I - Pu L - FPGA(XCS05XL) control signal:Done
50 P82,TMOIO,SBT3,
SCL3,SBI2
-PSTB0 O - Pu H H NJU3713 control signal:Strobe
51 P83,TM4IO,SBI3 SYSRSTO O - Pu H - System reset output 'L':Reset
52 P84,TM7IO,SBO3,SDA3 TRCL0 O - - - H DIT(YM3437C) control signal:Strobe
53 P85,TM9IOA,SBT4,
SCL4,SBO2
TRCL1 O - - - - FPGA(XCS05XL) initialize status
('L':While initializing,'H':Operation(*1))
54 VREF+ VREF+ - - - - - Analog reference voltage supply
55 P86,TM9IOB,SBI4 RXD I - Pu H - Serial port(Receive)
56 P87,TM9IC,SB04,SDA4 TXD O - - - - Serial port(Transmission)
57 P90,TM8IOA,BIBT1,
-DMAREQ1
SUBQ I - Pu H - DSP(MN662724) subcode data input
58 P91,TMIOIOA,BIBT2,
-DMAACK1
SENSE I - Pu H - DSP(MN662724) servo status input
59 P92,TMIOIOB,
-DMAREQ0
-FLOCK I - Pu H - DSP(MN662724) status input 'L':focus on
60 P93,TMIOIC,
-DMAACK0
-TLOCK I - Pu H - DSP(MN662724) status input 'L':tracking servo on input
61 AVss AVss - - - - - Analog GND(0V)
62 P94,AN0 STAT I - Pu H - DSP(MN662724) status input
63 P95,AN1 SQCK O - - - H DSP(MN662724) control signal:SQCK(subcode read clock)
64 P96,AN2 -INIT I - Pu H - FPGA(XCS05XL) control signal:Init
65 P97,AN3 -PGM O - Pu H - FPGA(XCS05XL) control signal:Program
66 Vdd VDD - - - - - Power supply(+3.3V)
67 P70,SBT0,-RAS MDAT O - - - - DSP(MN662724),DAC(PCM1738) control signal:Data
68 P71,SBIO,-LCAS,-CAS -CSEN O - Pu H H KEY MATRIX(74HC138) control signal:enable
69 P72,SBD0 -PRST O Lv Pd L - Round IC reset signal
70 P73,SBT1,DMUX CCLK O - - - - FPGA(XCS05XL) control signal:Clock
71 P74,SBI1 MCLK O - - - - DSP(MN662724),DAC(PCM1738) control signal:Clock
72 P75,SBO1 SPDATA O - - - - FPGA(XCS05XL) control signal:Data
73 PULLUP PULLUP I - Pu H - Pull up 33-50K
74 PULLUP PULLUP I - Pu H - Pull up 33-50K
75 -NMI -NMI I - Pu H - Not used. Open
76 PA0,-IRQ0 BLKCK I Ed Pu - - DSP(MN662724) subcode input(interrupt)
77 PA1,-IRQ1 RFDET I Ed Pu H - DSP(MN662724) HF detect signal(not used)
Pin
No. Port Name Symbol I/O DET Ext Res Ini Note

10
10DN-C680
*1: LED (LD101) lights up during initialization of FPGA (IC112) (it is less than 1 second at the time of normal), and LED puts out the
light after initialization.
When LED is carrying out continuation lighting even of after initialization, please check whether the control signal line for FPGA
initialization (pin 49, 64, 65, and 70) is carrying out the electrical connection, or it does not short-circuit with other signal lines,
and correct fault.
When LED is still carrying out continuation lighting, please correct in order of exchange of FLASH ROM (IC106), exchange of
FPGA (IC112), and exchange of a microcomputer (IC137).
*1: FPGA(IC112) の初期化の間、LED(LD101) が点灯 ( 正常時は 1 秒以内 ) し、初期化後に LED が消灯します。
もし、LED が初期完了後も連続点灯している場合は FPGA 初期化のための制御信号線 (pin49,64,65,70) が導通しているか、他
の信号線とショートしていないか確認し、修正して下さい。
それでも LED が連続点灯している場合は、FLASHROM(IC106) の交換、FPGA(IC112) の交換、マイコン (IC137) の交換の順で
修正を行って下さい。
78 PA2,-IRQ2 -SMIRQ I Ed Pu H - ACD27(SMPTE option unit) control signal:Interrupt request
79 PA3,-IRQ3 -TRSLA I Ed Pu - - Track select signal input(interrupt)
80 PA4,-IRQ4,TMI51B -TRSLB I Ed Pu - - Track select inverted signal(interrupt)
81 ADSEP ADSEP I - H H H Mode select 'H':Address data separation mode
82 -RST -RST I Lv - L - Reset signal 'L':Reset
83 Vdd Vdd - - - - - Power supply(+3.3V)
84 D0 D0 I/O - Pu H - Data bus
85 D1 D1 I/O - Pu H - Data bus
86 D2 D2 I/O - Pu H - Data bus
87 D3 D3 I/O - Pu H - Data bus
88 D4 D4 I/O - Pu H - Data bus
89 D5 D5 I/O - Pu H - Data bus
90 D6 D6 I/O - Pu H - Data bus
91 D7 D7 I/O - Pu H - Data bus
92 Vss Vss - - - - - GND(0V)
93 P10,TM810B -MLE O - - - - DAC(PCM1738) control signal:Latch
94 P11,TM81C -MLD O - - - - DSP(MN662724) control signal:Latch
95 P12,TM11IOA -MRST O Lv Pd L L DSP(MN662724) control signal:Reset
96 P13,TM11IOB P13 I Lv Pu H - ASP(MN19412A) status0 input
97 P14,TM11IOC P14 I Lv Pu H - ASP(MN19412A) status1 input
98 P15,TM12IOA P15 O Lv - - H ASP(MN19412A) ext.dram/disc data compare start signal
'L':start
99 P16,TM12IOB MSCL O - - - H ASP(MN19412A) control signal:Clock
100 P17,TM12IC MSDA O - - - H ASP(MN19412A) control signal:Data
Pin
No. Port Name Symbol I/O DET Ext Res Ini Note

11
11DN-C680
XCS05XL-5VQ100C (MA: IC112)
XCS05XL-5VQ100C Terminal Function
Pin
No. Port Name Symbol I/O Ext Note
1 GND GND - - GND(0V)
2 I/O,GCK1 I/O - - Not used. Open
3 I/O -PRST I Pd Reset signal 'L':Reset(internal register cleared)
4 I/O,TDI I/O - - Not used. Open
5 I/O,TCK I/O - - Not used. Open
6 I/O,TMS I/O - - Not used. Open
7 I/O -R I Pu Read signal
8 I/O -W I Pu Write signal
9 I/O -CS1 I Pu Chip select signal
10 I/O -CS2 I Pu Chip select signal
11 GND GND - - GND(0V)
12 VCC VCC - - Power supply(+3.3V)
13 I/O D0 I/O Pu Data bus
14 I/O D1 I/O Pu Data bus
15 I/O D2 I/O Pu Data bus
16 I/O D3 I/O Pu Data bus
17 I/O D4 I/O Pu Data bus
18 I/O D5 I/O Pu Data bus
19 I/O D6 I/O Pu Data bus
20 I/O D7 I/O Pu Data bus
21 I/O,GCK2 CHGOFT O - Off track detect sensitivity select signal
22 M1 M1 I - FPGA(XCS05XL) Mode select 'H':Slave serial mode
23 GND GND - - GND(0V)
24 M0 M0 I - FPGA(XCS05XL) Mode select 'H':Slave serial mode
25 VCC VCC - - Power supply(+3.3V)
26 -PWRDWN -PWRDWN I - FPGA(XCS05XL) control signal:Power down(Not used. Internal pullup)
27 I/O,GCK3 A20 I - Address bus
28 I/O(HDC) CHGICO O - RF equalizer specification select signal
29 I/O A21 I - Address bus
30 I/O(-LDC) I/O O Pu FPGA(XCS05XL) control signal:-LDC(Not used)
31 I/O PDI0 I Pu Parallel port 'L':Play command input
32 I/O PDI1 I Pu Parallel port 'L':Pause command input
33 I/O PDI2 I Pu Parallel port 'L':Standby/cue command input
34 I/O PDI3 I Pu Parallel port 'L':Track+ command input
35 I/O PDI4 I Pu Parallel port 'L':Track- command input
75
76
100
125
26
50
51

12
12DN-C680
36 I/O(-INIT) -INIT O Pu FPGA(XCS05XL) control signal:-INIT
37 VCC VCC - - Power supply(+3.3V)
38 GND GND - - GND(0V)
39 I/O PDI5 I Pu Parallel port 'L':Forward search command input
40 I/O PDI6 I Pu Parallel port 'L':Reverse search command input
41 I/O PDI7 I Pu Parallel port 'L':Fader start command input
42 I/O PDI8 I Pu Parallel port(Reserved)
43 I/O PDI9 I Pu Parallel port(Reserved)
44 I/O PDI10 I Pu Parallel port(Reserved)
45 I/O -CLOSE O Pu Loading motor driver(BA6287) control signal 'L':Close
46 I/O -OPEN O Pu Loading motor driver(BA6287) control signal 'L':Open
47 I/O -LIMITSW+ I Pu Laser pickup position status signal 'L':pickup is most inside position
48 I/O,GCK4 -LDIN I Pu Loading status singal 'L':Close operation finished
49 GND GND - - GND(0V)
50 DONE DONE O Pu FPGA(XCS05XL) control signal:DONE
51 VCC VCC - - Power supply(+3.3V)
52 -PROGRAM -PGM I Pu FPGA(XCS05XL) control signal:-PROGRAM
53 I/O(D7) -LDOUT I Pu Loading status singal 'L':Open operation finished
54 I/O,GCK5 -JOG0 I Pu Jog dial status detect signal
55 I/O(D6) -JOG1 I Pu Jog dial status detect signal
56 I/O -SHTL0 I Pu Shuttle status detect signal
57 I/O(D5) -SHTL1 I Pu Shuttle status detect signal
58 I/O -SHTL2 I Pu Shuttle status detect signal
59 I/O -SHTL3 I Pu Shuttle status detect signal
60 I/O -TRSLC I Pu Select knob status signal
61 I/O(D4) -PUSH I Pu Select button(PUSH) status signal
62 I/O AMUTE O Pu Analog Audio control signal:Mute 'H':Mute
63 VCC VCC - - Power supply(+3.3V)
64 GND GND - - GND(0V)
65 I/O(D3) DMUTE O Pu Digital Audio control signal:Mute 'H:Mute
66 I/O FSI0 O Pu X'tal(8.192MHz for FS converter unit) control signal:Enable 'L':Enable
67 I/O FSI1 O Pu X'tal(12.288MHz for FS converter unit) control signal:Enable 'L':Enable
68 I/O(D2) SEL0 O - Key matrix scan signal
69 I/O SEL1 O - Key matrix scan signal
70 I/O(D1) SEL2 O - Key matrix scan signal
71 I/O DYCON O Pu Serial Driver(HD26LS31) control signal:Enable 'H':Enable
72 I/O(D0,DIN) DIN I - FPGA(XCS05XL) control signal:DIN
73 I/O,GCK6(DOUT) I/O - - Not used. Open
74 CCLK CCLK I - FPGA(XCS05XL) control signal:CCLK
75 VCC VCC - - Power supply(+3.3V)
76 O,TDO O O - Not used. Open
77 GND GND - - GND(0V)
78 I/O -TRRST0 O Pd DIT(YM3437) and FS unit control signal:Reset 'L':Reset
79 I/O,GCK7 V/-W O Pd PLL circuit of Ext.sync.unit control signal
80 I/O(CS1) FSNOO O Pd Digital audio control signal:Data select 'L':DSP data 'H':FS unit data
81 I/O FSSEL O Pd FS unit control signal:FSSEL 'L':FS=32kHz 'H':FS=48kHz
82 I/O -FSIN I Pu FS unit status signal 'L':FS unit detected
83 I/O -SUBON O - Digital audio control signal:Subcode ON/OFF
84 I/O -SMIN I Pu Ext.sync.unit status signal 'L':Ext.sync.unit detected
85 I/O -CLKIN I Pu Ext.sync.unit status signal 'L':Video/word clock detected
86 I/O PITCH O Pd Not used. Open
87 I/O GSEL O - RF amprifier gain control signal
88 GND GND - - GND(0V)
89 VCC VCC - - Power supply(+3.3V)
90 I/O CKSEL O - Master clock(384FS) control signal 'L':Ext.sync.unit
Pin
No. Port Name Symbol I/O Ext Note

13
13DN-C680
Note: FS unit:FS converter unit(ACD25,option)
Ext.sync.unit:External video synchronizing unit(ACD27CS,Option)
91 I/O KI0 I Pu Key matrix data bus
92 I/O KI1 I Pu Key matrix data bus
93 I/O KI2 I Pu Key matrix data bus
94 I/O KI3 I Pu Key matrix data bus
95 I/O KI4 I Pu Key matrix data bus
96 I/O KI5 I Pu Key matrix data bus
97 I/O KI6 I Pu Key matrix data bus
98 I/O KI7 I Pu Key matrix data bus(Not used)
99 I/O,GCK8 I/O - - Not used. Open
100 VCC VCC - - Power supply(+3.3V)
Pin
No. Port Name Symbol I/O Ext Note

14
14DN-C680
MN19412A (MA: IC126)
MN19412A (Mecha Unit)
(IC104)
MN19412A Terminal Function
Pin No. Symbol I/O/T Function
1N.C. —Non connection.
2 SOEN2 I Output enable for serial output 2.
3 SCKO2 I Serial clock for serial output 2.
4 SDO3 O/T Data for serial output 3.
5 WSO3 I Word select for serial output 3.
6 SCKO3 I Serial clock for serial output 3.
7 SOEN3 I Output enable for serial output 3.
8Vss —GND terminal (0V).
9Vss —GND terminal (0V).
10 XCAS O Column address strobe for external DRAM. Open when not used.
11 XOE O Output enable for external RAM.
12 A14 O Address 14 for external RAM.
13 A13 O Address 13 for external RAM.
14 A12 O Address 12 for external RAM.
15 A11 O Address 11 for external RAM.
16 A10 O Address 10 for external RAM.
17 A9 O Address 9 for external RAM.
18 A8 O Address 8 for external RAM.
19 A7 O Address 7 for external RAM.
20 A6 O Address 6 for external RAM.
21 N.C. —Non connection.
22 A5 O Address 5 for external RAM.
23 A4 O Address 4 for external RAM.
24 A3 O Address 3 for external RAM.
25 A2 O Address 2 for external RAM.
26 A1 O Address 1 for external RAM.
27 A0 O Address 0 for external RAM.
28 XCE2 O Chip enable 2 for external SRAM.
29 XCE1 O Chip enable 1 for external SRAM.
30 XRAS O Row address strobe for external DRAM. Open when not used.
1
21
22
42
43
63
64
84

15
15DN-C680
Pin No. Symbol I/O/T Function
31 XWE O Write enable for external RAM.
32 VSS —GND terminal (0V).
33 VSS —GND terminal (0V).
34 D7 I/O Data 7 for external RAM (Connect to D4~7 when one DRAM is used).
35 D6 I/O Data 6 for external RAM.
36 D5 I/O Data 5 for external RAM.
37 D4 I/O Data 4 for external RAM.
38 D3 I/O Data 3 for external RAM.
39 D2 I/O Data 2 for external RAM.
40 D1 I/O Data 1 for external RAM.
41 D0 I/O Data 0 for external RAM.
42 P7 I/O/T General purpose port 7.
43 P6 I/O/T General purpose port 6.
44 P5 I/O/T General purpose port 5.
45 P4 I/O/T General purpose port 4.
46 P3 I/O/T General purpose port 3.
47 P2 I/O/T General purpose port 2.
48 P1/PT1 I/O/T General purpose port 1/Flag 1 for condition dividing.
49 P0/PT0 I/O/T General purpose port 0/Flag 0 for condition dividing.
50 N.C. —Non connection.
51 SYNC I Input for program sync (condition input).
52 VDD —Power supply terminal.
53 INT0 I Interrupt input 0.
54 INT1 I Interrupt input 1.
55 XRESET I System reset input.
56 Vss —GND terminal (0V).
57 CLKI I System clock input.
58 CLKO O System clock output.
59 VDD —Power supply terminal.
60 VDD —Power supply terminal.
61 ADDR0 I Address select 0 for IIC bus.
62 ADDR1 I Address select 1 for IIC bus.
63 XCE I Chip enable for IIC bus.
64 IICSEL I IIC/IC switching for IIC bus.
65 XTRANS I Data transfer control for IIC bus.
66 SDA I/O Serial data for IIC bus.
67 SCL I/O Serial clock for IIC bus.
68 MATCH O Address match at coefficient input for IIC bus.
69 SDI1 I Data for serial input 1.
70 WSI1 I Word select for serial input 1.
71 N.C. —Non connection.
72 SCKI1 I Serial clock for serial input 1.
73 SDI2 I Data for serial input 2.
74 WSI2 I Word select for serial input 2.
75 SCKI2 I Serial clock for serial input 2.
76 VDD —Power supply terminal.
77 VDD —Power supply terminal.
78 SDO1 O/T Data for serial output 1.
79 WSO1 I Word select for serial output 1.
80 N.C. —Non connection.
81 SCKO1 I Serial clock for serial output 1.
82 SOEN1 I Output enable for serial output 1.
83 SDO2 O/T Data for serial output 2.
84 WSO2 I Word select for serial output 2.

16
16DN-C680
MN662724 (MA: IC114)
MN662724 Terminal Function
Pin No. Symbol I/O Function
1 BCLK O Bit clock output for SRDATA.
2 LRCK O L,R discrimination signal output.
3 SRDATA O Serial data output.
4 DVDD1 Power supply for digital circuit.
5 DVSS1 GND for digital circuit.
6 TX O Digital audio interface output signal.
7 MCLK I Microcomputer command clock signal input (latches data at rising edge).
8 MDATA I Microcomputer command data input.
9 MLD I Microcomputer command load signal input. ("L": load)
10 SENSE O Sens signal output (OFT, FESL, NACEND, NAJEND, POSAD, SFG).
11 FLOCK O Focus servo draw in signal ("L": draw in state).
12 TLOCK O Tracking servo draw in signal ("L": draw in state).
13 BLKCK O Subcode block clock signal (fBLKCK=75Hz).
14 SQCK I External clock input for subcode Q register.
15 SUBQ O Subcode Q code output.
16 DMUTE I Muting input ("H": mute).
17 STAT O Status signal (CRC, CUE, CLVS, TTSTOP, FCLV, SQOK).
18 RST I Reset input ("L": reset).
19 SMCK O 8.4672MHz clock signal output at MSEL="H". 4.2336MHz clock signal output at MSEL="L".
20 PMCK O 88.2kHz clock output.
21 TRV O Traverse forcible sending output. 3-state.
22 TVD O Traverse drive output.
23 PC O Spindle motor ON signal ("L": ON).
24 ECM O Spindle motor drive signal (forcible mode output). 3-state.
25 ECS O Spindle motor drive signal (servo error signal output).
26 KICK O Kick pulse output. 3-state.
27 TRD O Tracking drive output.
28 FOD O Focus drive output.
29 VREF I Reference voltage for DA output portion (TVD,BCS,TRD,FOD,FBAL,TBAL).
30 FBAL O Focus balance adjusting output.
31 TBAL O Tracking balance adjusting output.
32 FE I Focus error signal input (analog input).
33 TE I Tracking error signal input (analog input).
34 RFENV I RF envelope signal input (analog input).
35 VDET I Vibration detecting signal input ("H": detect).
60
61
8
0
120
21
40
41

17
17DN-C680
Pin No. Symbol I/O Function
36 OFT I Off track signal input ("H": off track).
37 TRCRS I Track cross signal input.
38 RFDET I RF detecting signal input ("L": detect).
39 BDO I Drop out signal input ("H": drop out).
40 LDON O Laser ON signal output ("H": ON).
41 PLLF2 I/O Loop filter terminal for PLL.
42 PLAY O Play signal output ("H": play).
43 WVEL O Double speed status signal output.
44 ARF I RF signal input.
45 IREF I Reference current input terminal.
46 DRF I Bias terminal for DSL.
47 DSLF I/O Loop filter terminal for DSL.
48 PLLF I/O Loop filter terminal for PLL.
49 VCOF I/O Loop filter terminal for VCO.
50 AVDD2 Power supply for analog circuit (for DSL, PLL, DA output sections).
51 AVSS2 GND for analog circuit (for DSL, PLL, DA output sections).
52 CK384 O 384 fs clock output.
53 PCK O PLL extract clock output (fPCK=4.321MHz).
54 TOFS O Tracking offset adjust signal output.
55 SUBC O Subcode serial output data output.
56 SBCK I Clock input for subcode serial output.
57 VSS GND for osc. circuit.
58 X1 I X'tal osc. circuit input terminal. f=16.9344MHz or 33.8688MHz.
59 X2 O X'tal osc. circuit output terminal.
60 VDD Power supply for osc. circuit.
61 BYTCK O Byte clock output.
62 CLDCK O Subcode frame clock signal output (fCLDCK=7.35kHz).
63 FCLK O X'tal frame clock output (fFCLK=7.35kHz).
64 IPFLAG O Interpolation flag output ("H": interpolation).
65 FLAG O Flag output.
66 CLVS O Spindle servo phase sync state signal output ("H":CLV, "L":rough servo).
67 CRC O Subcode CRC check result output ("H":OK, "L":NG).
68 DEMPH O Deemphasis detecting signal output ("H":ON).
69 RESY O
Flag 6 output at SSEL:"H"(RAM address reset generating signal by Jitter margin over of CLV servo.
"L":address reset generates). RESY output at SSBL:"L"(Re-sync signal output of frame sync. "H": sync,
"L":out sync).
70 SDAT48 O 48 fs serial data output.
71 TEST I Test terminal (normally "H").
72 AVDD1 Power supply for digital circuit.
73 LRCK48 O 48 fs L, R discrimination signal output.
74 AVSS1 GND for digital circuit.
75 BCLK48 O 48 fs bit clock output for SDAT48.
76 RSEL I RF signal polarity specify terminal (RSEL="H" at brightness level "H". RSEL="L" at brightness level "L").
77 CSEL I X'tal osc. frequency specify terminal,, X'tal osc. freq. 33.8688MHz:CSEL"H", 16.9344MHz:CSEL"L".
78 PSEL I Test terminal (normally "L").
79 MSEL I SMCK terminal. Output frequency shifting terminal ("H":SMCK=8.4672MHz,"L":SMCK=4.2336MHz).
80 SSEL I Sub Q teminal. Output mode shifting terminal ("H":Q code buffer using mode).

18
18DN-C680
M66005AFP (DK: IC502)
AN22002A (MA: IC110)
E
45
32
31
30
29
27
28
17
67811 12 13 14
9
10
15
22
23
21
20
19
18
2
1
3
16
25
26
24
RF_EQ
NRFDET
RFOUT
RFN
CAGC ARF CBD0 BD0 C0FTR 0FTR
AGC BD0 0FTR
CEA
3TOUT
NRFDET
FEN
TEN
TEBPF
VDET
TEOUT
FEOUT
3TENV
RFIN
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
AMP GCA BCA
SUB
SUB
VDET
AMP GCA BCA
AMP GCA
AMP GCA
BCA
BCA
A
C
B
D
F
B
+
D
A
+
C
F
E
VREF
VCCGND
FBAL
TBAL
GCTL
LD
PD
1
16
32
17

19
19DN-C680
W29C020C-90B (MA: IC106)
W29C020C-90B Terminal Function
PCM1738-1 (MA: IC123)
1
2
3
4
5
6
7
8
9
10
11
12
1
3
14
15
1
6
32
3
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DQ0
DQ1
DQ2
GND
A7
A6
A5
A4
A3
A2
A1
A0
NC
A16
A15
A12
V
WE
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DD
A17
SYMBOL PIN NAME
A0−A17 Address Inputs
DQ0−DQ7 Data Inputs/Outputs
CE Chip Enable
OE Output Enable
WE Write Enable
VDD Power Supply
GND Ground
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RST
ZEROL
ZEROR
LRCK
DATA
BCK
SCKI
DGND
V
DD
SCKO
MDO
MDI
MC
CS
V CC 3
AGND2
I
OUT
L -
I OUT L+
V
CC 2
V
CC 1
V
COM 3
I
REF
V COM 2
V
COM 1
AGND1
I
OUT R+
I
OUT R -
MUTE
1 RST I Reset (1)
2 ZEROL O Zero-flag for Lch
3 ZEROR O Zero-flag for Rch
L/R clock (fs) input (1)
4 LRCK I
5 DATA I Serial audio data input (1)
6 BCK I Bit clock input (1)
7 SCKI I System clock input (1)
8 DGND Digital GND
9VDD Digital power +3.3V
10 SCKO O System clock output
11 MDO O Function control register serial data output (2)
12 MDI I Function control register serial data input (1)
13 MC I Function control register shift clock (1)
14 CS I Mode control chip select and latch signal (1)
15 MUTE I Analog output mute control (1)
16 LOUTR - O Rch analog current output ( - )
17 LOUTR+ O Rch analog current output (+)
18 AGND1 Analog GND
19 VCOM1 Internal bias de-coupling pin
20 VCOM2 Common mode voltage of I/V
21 IREF Output current reference bias pin
22 VCOM3 Internal bias de-coupling pin
23 VCC1 Analog power +5.0V
24 VCC2 Analog power +5.0V
25 IOUTL+ O Lch analog current output (+)
26 IOUTL - O Lch analog current output ( - )
27 AGND2 Analog GND
28 VCC3 Analog power +5.0V
Pin Name Function
Pin No. I/O
PCM1738-1 Terminal Function
Note: (1) Schmitt trigger input, 5V input possible (2) Tri-state output

20
20DN-C680
AN8389 (MA: IC111)
AN8389 Terminal Function
PVCC2
PGND2 D4+
D4
-
D3+
D3
-
D2+
D2
-
D1+
D1
-
PGND1 PVCC1
VCC
VREF
IN4 IN3
GND
NC
VRESET
GND
IN2
PC2
IN1
PC1
BLT Linear
Driver
ch4
BLT Linear
Driver
ch3
BLT Linear
Driver
ch2
BLT Linear
Driver
ch1
Absolute
V
- I
Direction
Det
Absolute
V
- I
Direction
Det
Absolute
V
- I
Direction
Det
Absolute
V
- I
Direction
Det
thermal
Protect
Vcc
Monitor
VREF
Monitor
RESET
ch4 ch3 ch2 ch1
123456789
24 23 22 21 20 19 18 17 16 15 14 13
12
11
10
Pin No. Symbol I/O Function
1 Vcc Power supply.
2 VREF I VREF input terminal.
3 IN4 I Motor driver 4 input terminal.
4 IN3 I Motor driver 3 input terminal.
5 GND GND.
6NC
7 NRESET O Reset output terminal.
8 GND GND.
9 IN2 I Motor driver 2 input terminal.
10 PC2 I PC2 (Power cut) input terminal.
11 IN1 I Motor driver 1 input terminal.
12 PC1 I PC1 (Power cut) input terminal.
13 PVCC1 Power supply terminal 1 for driver.
14 PGND1 GND terminal 1 for driver.
15 D1 - O Motor driver 1 reversal output terminal, spindle motor drive.
16 D1+ O Motor driver 1 obverse output terminal, spindle motor drive.
17 D2 - O Motor driver 2 reversal output terminal, tracking actuator drive.
18 D2+ O Motor driver 2 obverse output terminal, tracking actuator drive.
19 D3 - O Motor driver 3 reversal output terminal, focus actuator drive.
20 D3+ O Motor driver 3 obverse output terminal, focus actuator drive.
21 D4 - O Motor driver 4 reversal output terminal, slide motor drive.
22 D4+ O Motor driver 4 obverse output terminal, slide motor drive.
23 PGND2 GND terminal 2 for driver.
24 PVCC2 Power supply terminal 2 for driver.