Digital Equipment DM01 User manual

DATA MULTIPLEXER
DM01
INSTRUCTION MANUAL
DIGITAL EQUIPMENT CORPORATION •MAYNARD. MASSACHUSETTS

Ist Printing September 1967
2nd Printing September 1968
Copyright (C) 1968 by Digital Equipment Corporati on
The following are registered trademarks of Digital
Equipment Corporation, Maynard, Massachusetts:
DEC PDP
FLIP CHIP FOCAL
DIGITAL COMPUTER LAB

DM01 DATA MULTIPLEXER
CONTENTS
Chapter Page
1INTRODUCTION 1-1
2SCOPE 2-1
3OPERATION 3-1
3.1 General 3-1
3.2 Log ic Operation 3-1
3.2.1 Multiplexer Control (BS-D-DMOl -0-2) 3-1
3.2.2 Level Production from Multiplexer Control (BS-D-DMOl-0-1 1)3-3
3.2.3 Data Address Line Selector (BS-D-DMOl -0-4) 3-4
3.2.4 Data Bits Line Selector (BS-D-DMOl -0-3) 3-4
4INTERFACE 4-1
5POWER SUPPLY 5-1
6MAINTENANCE 6-1
6.1 Preventive Maintenance 6-1
6.1 .1 Power Supply Checks 6-1
6.2 Corrective Maintenance 6-1
7INSTALLATION 7-1
7.1 Mounting 7-1
7.2 Environmental Conditions 7-1
7.3 Power Requirements 7-1
8SCHEMATICS 8-1
8.1 Semiconductor Substitution 8-1
TABLES
Table
6-1 Type 728 Power Supply Output Checks (Drawing CS-B-728) 6-1
8-1 Semiconductor Substitution 8-1
ILLUSTRATIONS
Figure
1-1 DM01 General Block Diagram 1-1
3-1 DM01 Data Break Signals 3-2
3-2 PDP-8 -DM01 Timing Diagram 3-3

DM01 DATA MULTIPLEXER
CONTENTS (continued)
Figure Page
8-1 Power Supply (CS-B-728) 8-2
8-2 Diode Gate (CS-B-B141) 8-2
8-3 Diode Cluster (RS-B-R002) 8-3
8-4 Dual Flip-Flop (RS-B-R202) 8-3
8-5 Inverter (CS-B-S107) 8-4
8-6 Diode Gate (CS-B-Sl 11) 8-4
8-7 DC Carry Chain (RS-B-S181
)
8-5
8-8 Dual Flip-Flop (CS-B-S202) 8-5
8-9 Clamped Loads (CS-B-W005) 8-6
8-1 Signal Cable Connector (RS-B-W021 )8-6
8-11 Pulse Amplifier (CS-B-W640) 8-7
8-12 Utilization Module List (UML-D-DMOl-0-8) 8-9
8-13 Multiplexer Control (BS-D-DMOl-0-2) 8-11
8-14 Level Production from Multiplexer Control (BS-D-DMOl-0-1 1) 8-13
8-15 Data Address Line Selector (BS-D-DMOl-0-4) 8-15
8-16 Data Bits Line Selector (BS-D-DMOl -0-3) 8-17
8-1 7DM01 Interconnecting Cable Diagram (IC-DMOl -0-1 3) 8-19
8-18 I/O Connectors (BS-D-DMOl-0-6) 8-21
8-19 Data Multiplexer Connectors (BS-D-DMOl -0-5) 8-23
IV

DM01 DATA MULTIPLEXER
CHAPTER 1
INTRODUCTION
This manual covers the maintenance of the data multiplexer, designated as Type DM01, now
in production at the Digital Equipment Corporation of Maynard, Massachusetts.
The DM01 is essentially aswitching device for use between the PDP-8®and amaximum of
seven peripheral or I/O devices, as shown in figure 1-1 .The peripheral devices include high-speed
magnetic tape systems, high-speed drum memories, and CRT display systems containing memory elements,
all of which use the PDP-8 data break facility.
MAXIMUM
OF
SEVEN
PERIPHERAL
DEVICES
PDP-8
DM01
DATA
MULTIPLEXER ^
Figure 1-1 DM01 General Block Diagram
0PDP is the registered trademark of the Programmed Data Processor manufactured by Digital Equipment
Corporation of Maynard, Massachusetts.
1-1

DM01 DATA MULTIPLEXER
CHAPTER 2
SCOPE
This manual provides complete maintenance data on the logic circuitry of the Data Multiplexer
Type DM01 .It details information on logical operation, interface characteristics and connections, and
installation and mounting.
Uses of the levels and pulses produced by the peripheral devices and the PDP-8 are not
covered in this manual. For further information on such signals, reference to the PDP-8 User's Handbook
F-85 and instruction manuals of the specific peripheral devices is advised.
2-1

DM01 DATA MULTIPLEXER
CHAPTER 3
OPERATION
3.1 GENERAL
The Data Multiplexer Type DM01, as noted, acts as aswitch between the PDP-8 and a
maximum of seven high-speed peripheral devices which use the data break facility.
Whenever adevice using the data break facility requests abreak, the device produces a
number of signals. As figure 3-1 shows, only the signals from the selected peripheral device pass through
the DM01 into the PDP-8.
3.2 LOGIC OPERATION
The following paragraphs describe the logic operation of the DM01 Data Multiplexer as it re-
lates to the PDP-8 and the peripheral devices connected to it. (Each major heading references directly
to an engineering drawing found in chapter 8 of this manual .)
3.2.1 Multiplexer Control (BS-D-DMOl-0-2)
Figure 8-13 illustrates the logic control circuitry of the DM01 Data Multiplexer. Upon receipt
of PDP-8 timing pulses and aBRK REQ (break request) level from the peripheral device requesting the
data break, this control logic produces MPX, BENABLE, and BRK REQ levels and ADD ACC (address
accepted) pulse
.
For ease in explanation, it is assumed the peripheral device producing the BRK REQ 1level
is requesting service. Similar operations occur when other peripheral devices request data breaks.
The timing diagram in figure 3-2 is used in conjunction with the multiplexer control descrip-
tion .
During the PDP-8 turn-^on period, or whenever the operator presses the START key, POWER
CLEAR pulses (-3v, 100-nsec pulses at a10-kHz rate) clear the BREAK IN PROGRESS (figure 8-4), and
the BENABLE, and MPX flip-flops (figure 8-8). These pulses are accepted, and their function imple-
mented, without the need for device selection through addressing.
All BRK REQ levels enter the DM01 through the R002 diode network (figure 8-3) at location
B22 and SI 11diode gate (figure 8-6) at B23. This circuitry is shown in the upper right corner of the
drawing
.
The ground BRK REQ 1level is applied to terminal Lof the above modules. The remaining
input terminals are at -3v
.
3-1

DM01 DATA MULTIPLEXER
PERIPHERAL
DEVICES
-DAO-0 THROUGH DA11-0
DAO- )THROUGH DA11-1
-DAO -2 THROUGH DA11-2
-DAO -3 THROUGH DA11-3
-DAO -4 THROUGH DA11-4
DAO -5 THROUGH DA11-5
-DAO -6 THROUGH DA11-6
BREAK REQUEST
THROUGH
BREAK REQUEST 6
ADD ACC-0
•THROUGH
ADD ACC-6
MULTIPLEXER
CONTROL
wcov-e>
THROUGH
WCOV -6
BENABLE
THROUGH 6
-DBO-O THROUGH DB11-0 -
-DBO- 1THROUGH DBI1-1 -
-DBO-2 THROUGH DB11-2 -
-DBO -3 THROUGH DB11-3 -
-DBO-4 THROUGH DB11-4 -
-DBO -5 THROUGH DB11-5 -
DBO -6 THROUGH DB11-6 -
DATA
LINE
SELECTOR
DA0 THROUGH DAIl
-BREAK REQUEST -
Tl
ADDRESS ACCEPTED
POWER CLEAR
WCOV
DATA -OUT -
—THROUGH -
DATA-OUT-
6
DA SEL DEV-O
-THROUGH
DA SEL DEV-6
+1—CA INH-O
THROUGH
+1-»CA INH-6
-+1— CA INH -
-DB0 THROUGH DB11
Figure 3-1 DM01 Data Break Signals
The -3v output of the SI 11diode gate is inverted by the SI 07 module (figure 8-5) at
location B32. The resulting BRK REQUEST ground level goes to the PDP-8 major state generator to
signal the computer that a data transfer is to take place.
BRK REQ 1is also applied to terminal Eof the W005 clamped load (figure 8-9) at location B9
and shown across the middle of the drawing. The level enables the DCD gate associated with the set
terminal of the MPX-1 flip-flop. The corresponding gate of the remaining MPX flip-flops is inhibited.
3-2

/DM01 DATA MULTIPLEXER
752
APDP-8 Tl timing pulse sets the MPX-1 flip-flop, enabling the DCD gate connected to the
set terminal of the BENABLE 1flip-flop. The ground level from the 1side of the MPX-1 is applied to
terminal Fof the SI 81 dc carry chain (figure 8-7) at B12 and shown across the lower portion on the
drawing. Through this operation, all MPX flip-flops that are less significant (to the right of) than
MPX-1 are held in the state. Because of this function, the peripheral device producing BRK REQ 1
is given priority over the less significant peripherals.
MEM
DONE
ADO
ACC.
fI: «^
MEMSTART
T2 Tl
Figure 3-2 PDP-8 -DM01 Timing Diagram
A-3v level is present at Kof the SI 11module at B30 and also shown across the lower part of
the drawing. When an ADDRESS ACCEPTED pulse arrives from the PDP-8, BENABLE 1is set and a-3v
ADD ACC-1 pulse is generated.
The levels and pulses produced by multiplexer control are used by other circuits of the DM01,
as covered in the following sections.
3.2.2 Level Production from Multiplexer Control (BS-D-DMOl-0-1 1)
The logic circuitry of figure 8-14 uses the output levels of the MPX and BENABLE flip-flops
to produce levels and pulses for use by both the DM01 and the peripheral devices.
The logic element on the left side of the drawing consists of seven, 2-input, diode gate-
inverter-clamped load networks. The Sill diode gates at locations B6, B8, and B23 have paired inputs
which form AND gates. One terminal of each gate is common, and is at -3v whenever abreak is in
progress.
Proceeding with the example, a-3v level from the set BENABLE 1flip-flop provides the
level necessary to give the desired -3v B•MPX 1level from the W005 clamped load at B9.
The gated driver, made up of the SI 11diode gates at A16, A17, and A18 and the W640
pulse converters (figure 8-1 1) at B29, A14, and A15 produce a-3v WCOV (word count overflow) pulse
when suitable inputs are present. Because a-3v BENABLE level is present, a-3v WCOV-1 pulse is
produced when a-3v WCOV pulse arrives. The B•MPX 1level and WCOV-1 pulse go to peripheral
device 1.
3-3

DM01 DATA MULTIPLEXER
The two paralleled inverters on the right side of the drawing produce levels that are used by
DM01 selector networks. A-3v DB SEL DEV 1level, which is used by the selector networks shown in
figure 8-16 and discussed in section 3.2.4, is generated by applying aground level from the BENABLE 1
flip-flop to terminal Hof the SI 07 diode gate or A12. The output is at terminal Fat B4.
DA SBL DEV 1is used by the logic circuitry of figures 8-15 and 8-16, and is explained in
section 3.2.3. The level is produced by inverting the MPX-1 ground level present at terminal Hof the
SI 07 inverter at B5 .The output is present at F, location A13.
3.2.3 Data Address Line Selector (BS-D-DM01-0-4)
The circuitry shown across the top of figure 8-15 serves to permit the 12-bit address from the
peripheral device requesting the break to enter the PDP-8 memory address register. This is accomplished
through alogical AND operation.
The terminals labeled E, H, K, M, P, S, and Uof the B141 Module (figure 8-2) at location
CI receive the levels designated DA SEL DEV through DA SEL DEV 6, respectively. The most signi-
ficant data address bit from the peripheral devices is applied to terminals F, J, L, N, R, T, and Vof
module Cl£ the least significant is applied to module C12.
Continuing with the example, a-3v DA SEL DEV 1level, applied to terminal H, provides
one level needed by the AND gate. The data address bits, designated DAO-1 through DAI 1-1, are
applied to the remaining terminal of the gate.
The output levels, DAO through DAI 1,which go to the PDP-8 memory address register, appear
at the SI 07 inverter output at locations B7 and B15.
The logic circuitry across the lower part of the drawing functions in asimilar manner.
DA SEL DEV 1enables the same terminal of each B141 Module.
A CYC SEL-1 level from peripheral device 1is logically ANDed with DA SEL DEV 1in the
diode gate at CI 3. The output CYC SEL level, available at terminal Rof the inverter at B15, goes to
the PDP-8 major state generator.
The B141 diode gates at locations CI 4, C15, and CI 6permit the extended memory address
bits from peripheral device 1to enter the PDP-8. The output levels, designated DAEX 1, DAEX 2, and
DAEX 3, are available at the S107 inverter terminals Fand Dat B25 and Tat B15, respectively.
3.2.4 Data Bits Line Selector (BS-D-DMOl-0-3)
Data bits from the selected peripheral device reach the PDP-8 memory buffer register through
the logic circuitry, made up of the Bl 41 diode gates at locations CI 7through C28, and illustrated
across the top of figure 8-16.
3-4

DM01 DATA MULTIPLEXER
This circuitry operates in the same manner as that used for data addressing; namely,
DB SEL DEV 1provides one level required by the gate string, and the data bits from peripheral device 1,
designated DBO-1 through DB11-1, provide the remaining levels.
The 12-bit output, comprised of the bits labeled DBO through DBU, are found at the SI 07
inverter outputs at locations B25 and B26.
An INCREMENT CA INHIBIT (+1 —CA INH) level, which is used during 3-cycle breaks,
is produced by ANDing the DB SEL DEV 1and +1 —CA INH levels.
Similarly, aDATA IN level, which specifies the data transfer direction, is produced by
ANDing DA SEL DEV 1with DATA OUT.
These two levels are terminated at pins Nand R, respectively, of the SI 07 diode gate at
location B32.
3-5

DM01 DATA MULTIPLEXER
CHAPTER 4
INTERFACE
All interface connections to the DM01 are made at assigned module receptacle connectors at
the back of the multiplexer. The interfacing between the PDP-8, DM01, and the peripheral devices
is shown in the following figures:
Figure 8-17 DM01 Interconnecting Cable Diagram (IC-DMOl-0-1 3)
Figure 8-1 8I/O Connectors (BS-D-DMOl -0-6)
Figure 8-19 Data Multiplexer Connectors (BS-D-DMOl -0-5)
4-1

DM01 DATA MULTIPLEXER
CHAPTERS
POWER SUPPLY
ADEC Type 728 Power Supply (table 8-1) generates the voltage levels (+10 and -15 vdc)
required for operation of the multiplexer.
Chapter 8contains the schematic of this power supply and chapter 6, the output check data.
The DEC System Modules Catalog (C-100) provides detailed information on the operational character-
istics of the supply.
5-1

DM01 DATA MULTIPLEXER
CHAPTER 6
MAINTENANCE
6.1 PREVENTIVE MAINTENANCE
The general preventive maintenance procedures provided in the PDP-8 Maintenance Manual
(F-87) apply to the multiplexer control logic.
6J.1 Power Supply Checks
Table 6-1 shows the output voltage checks needed for the Type 728 Power Supply used in
this equipment. Perform the power supply checks described in table 6-1 .Use amultimeter to make the
output voltage measurements with the normal load connected, and an oscilloscope to measure the peak-
to-peak ripple content on all dc outputs of the supply. The +10v and -15v supplies are not adjustable;
therefore, if any output voltage or ripple content is not within specifications, consider the power supply
defective and initiate troubleshooting procedures.
TABLE 6-1 TYPE 728 POWER SUPPLY OUTPUT CHECKS
(Drawing CS-B-728)
Measurement
Terminals at
Power Supply
Output
Nominal
Output
(vdc)
Acceptable
Output
Range (v)
Maximum
Output
Current (a)
Maximum
Peak-to- Peak
Output Ripple (v)
Red (+) to
Yellow {-)
Yellow (+) to
Blue (-)
+10
-15v
+9.5 to +11.0
-14.5 to -16.0
7
8
0.7
0.7
6.2 CORRECTIVE MAINTENANCE
The simplicity of the system and the logic description provided in this document permit the use
of standard troubleshooting techniques for isolating the trouble quickly and efficiently. For economical
maintenance under most conditions, replace the inoperative module with one from spares and return the
defective module to DEC for repair or replacement.
6-1