DM01 DATA MULTIPLEXER
CHAPTER 3
OPERATION
3.1 GENERAL
The Data Multiplexer Type DM01, as noted, acts as aswitch between the PDP-8 and a
maximum of seven high-speed peripheral devices which use the data break facility.
Whenever adevice using the data break facility requests abreak, the device produces a
number of signals. As figure 3-1 shows, only the signals from the selected peripheral device pass through
the DM01 into the PDP-8.
3.2 LOGIC OPERATION
The following paragraphs describe the logic operation of the DM01 Data Multiplexer as it re-
lates to the PDP-8 and the peripheral devices connected to it. (Each major heading references directly
to an engineering drawing found in chapter 8 of this manual .)
3.2.1 Multiplexer Control (BS-D-DMOl-0-2)
Figure 8-13 illustrates the logic control circuitry of the DM01 Data Multiplexer. Upon receipt
of PDP-8 timing pulses and aBRK REQ (break request) level from the peripheral device requesting the
data break, this control logic produces MPX, BENABLE, and BRK REQ levels and ADD ACC (address
accepted) pulse
.
For ease in explanation, it is assumed the peripheral device producing the BRK REQ 1level
is requesting service. Similar operations occur when other peripheral devices request data breaks.
The timing diagram in figure 3-2 is used in conjunction with the multiplexer control descrip-
tion .
During the PDP-8 turn-^on period, or whenever the operator presses the START key, POWER
CLEAR pulses (-3v, 100-nsec pulses at a10-kHz rate) clear the BREAK IN PROGRESS (figure 8-4), and
the BENABLE, and MPX flip-flops (figure 8-8). These pulses are accepted, and their function imple-
mented, without the need for device selection through addressing.
All BRK REQ levels enter the DM01 through the R002 diode network (figure 8-3) at location
B22 and SI 11diode gate (figure 8-6) at B23. This circuitry is shown in the upper right corner of the
drawing
.
The ground BRK REQ 1level is applied to terminal Lof the above modules. The remaining
input terminals are at -3v
.
3-1
