Digital Equipment DMO9AL User manual

INSTRUCTION MANUAL
DMOSA
ADAPTER/MUL TIPLEXER
DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS

DMDSA
ADAPTER/MUL TIPLEXER
INSTRUCTION MANUAL
DEC-09-19AA-D
DIGITAL EQUIPMENT CORPORATION. MAYNARD. MASSACHUSETTS

Copyright ©1968 by Digital Equipment Corporation
The following are registered trademarks of Digital
Equipment Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
ii
PDP
FOCAL
COMPUTER LAB
October 1968

CONTENTS
Page
1• Introducti on 1
1.1 Related
Documentation
1
1 .2 Engineering Drawing References 2
2.
Specifications
2
2.1 Environmental 2
2.2 Power Requirements 2
2.3 Physical 2
2.4
Controls and Indi cators 2
2.5 Performance 2
3.
Installation 3
4.
Principles of Operation 3
4.1 Basic 3
4.2
Detailed 4
4.2.1 Power
Turn-On
4
4.2.2
Internal Control Pulse Train 4
4.2.3
Single-Fast-Input Cycle
5
4.2.4
Single-Slow-Output Cycle
6
4.2.5
Double (Back to Back) - Fast-Output Cycles
7
5.
Acceptance Test Procedure
11
6.
Maintenance
11
6.1
General
11
6.2
Delay Adjustments
11
6.3 Module Complement
11
7.
Engineering Drawings
12
ILLUSTRATIONS
1-1
Basic DM09A System Block Diagram
3-1
Installation Diagram 3
4-1
Control Pulse Train Circuitry
5
4-2 Control Pulse Train Time Relationship 5
iii

1-1
4-1
4-2
4-3
6-1
7-1
CONTENTS (Cant)
TABLES
Reference Documents
Single-Fast-Input Cycle Signal Flow
Single-Slow-Output Cycle Signal Flow
Double {Back to Back)-Fast-Output Cycles Signal Flow
Module Complement
Engineering Drawings
iv
1
8
9
10
12
12

1• INTRODUCTION
The DM09A Adapter/Multiplexer an option to the PDP-9 manufactured by Digital Equipment
Corporation (DEC), provides an interface through which three I/O devices may'gain access to the
PDP-9 memory via the DMA channel. A basic system block diagram is given in Figure 1-1.
Figure 1-1 Basic DM09A System Block Diagram
This document
and the documents referenced herein provide the information necessary for
installation, operation and maintenance of the option. The level of discussion assumes that the user
is fami liar with the basic PDP-9.
1•1 Related Documentation
The
DEC documents listed in Table 1-1 contain material which supplements information in
this
document.
Title
PDP-9 User Handbook
PDP-9
Maintenance Manual
Volumes I and II
DIGITAL Logic Handbook
Table 1-1
Reference Documents
Document Number
F-95
F-97
C-105
Description
Operation and programming information
for
the PDP-9.
Operation and maintenance information
for
the PDP-9 including basic PDP-9
engineering drawings. Basic DM09A
theory of operation.
Specifications and descriptions of most
FLIP CHIP moduies used in the DM09A.

1 .2 Engineering Drawing References
Engineering drawings wi
II be referenced using an abbreviated code. As an example,
drawing D-BS-DM09-A-2, DMA Adapter Multiplexer Control, sheet 1 of 2, wi II be referenced as
[DM-2(2)] •
2. SPECIFICATIONS
2.1 Environmental
The DM09A consists
entire Iy of modu les of the type used in the PDP-9 centra I processor.
Therefore, PDP-9 environmentaI specifications apply to the DM09A.
2.2 Power Requirements
The option obtains a
II necessary operating power from the PDP-9 power supply system.
No additional power supplies, power control or fan assemblies are necessary.
2.3 PhysicaI
The DM09A consists entirely of modules which are housed by two DEC standard 1943 mount-
ing
panels, thus requiring 10-1/2 in. of mounting space. Placement of these panels is given in Sec-
tion 3, INSTALLATION.
2.4 Controls and Indicators
No controls or indicators are associated with the DM09A. The option is entirely under the
control of the PDP-9 and the I/O devices.
2.5 PeITormance
The multiplexer operates at two speeds. I/O devices with 10 mHz logic may request the
high speed and thus achieve a 1 iJS/transfer rate; I/O devices with low speed logic should request the
low speed of 3 iJS/transfer to permit sufficient data-line settling time. It should be remembered that
the speed range applies only to the DM09A. The PDP-9 DMA channel and the memory require only
1 iJS/transfer.
2

3. INSTALLATION
Implementation of the option involves insta II ing the option modules into their preassigned,
prewired locations in the basic PDP-9 cabinet. The location in which the option mounts is shown in
Figure 3-1 •
RESERVED
FOR
DM09A
RESERVED
FOR
ME09B
PAPER TAPE
READER AND
PUNCH
OPERATOR'S CONSOLE
TABLE
Figure 3-1 Insta Ilation Diagram
The following engineering drawings provide all necessary interface information.
Drawing Number
D-CD-DM09-A-9 (Rev. A)
CD-D-DM09-A-10
CD-D-DM09-A-11
Title
Memory Interface
Interface Cabling
DM09 Memory
Cabling DMA
Inter-Memory
4. PRINCIPLES OF OPERATION
4. 1 Basic
Description
Interface between the DM09A and the basic
PDP-9 memory.
Interface between the DM09A, ME09A memory
extension control and MM09A extended memory
bank.
Interface between the MC70B basic PDP-9 memory
and MM09A, Band C extended memory banks.
A basic description of DM09A logic operation can be obtained from Section 3.8.3, DMA
Channel Transfers, of the PDP-9 Maintenance Manual, Volume 1. A detailed DM09A block diagram
is also contain in that section.
This document describes in detail the operation of the DM09A DMA Adapter/Multiplexer.
3

4.2 Detai led
A variety of transfer type combinations are possible with the DM09A. To avoid excessive
repetition, only three types will be described herein; Single-Fast-Input cycle, Single-Slow-Output
cyc Ie and Doub Ie (Back to Back)-Fast-Output cyc les.
Certain DM09A operations are executed regardless of transfer type; namely, control circuitry
initialization via power turn-on and interna I DM09A control pulse train generation. Transfer type
descriptions assume I/O device 0 is being acted upon. All reference wi II be made to I/O device O.
Simi lar operations wi II result when any other device is acted upon.
All transfer types can be thought of as consisting of a number of "time states" each commen-
cing with a PDP-9 ClK pulse. Single transfers consist of time states in which either an I/O device is
made ready, in which a device is synchronized to the PDP-9, or in which a data transfer takes place.
With multiple transfers, synchronization is established during the previous data transfer.
When reading the logic descriptions, the user should refer to the engineering drawings
referenced on the signal flow tables. In addition, DM09A timing diagrams, drawings DM-8(1) and
DM-8(2) should be referenced for specific timing information.
4.2.1 Power Turn-On
When the system is first turned on, PK ClR (power and key clear) pulses arrive at the DM09A
control logic and produce PWR ClR POS (power clear positive) pulses to condition the control logic.
The operations performed are as follows:
4.2.2
Clear SYNC 0
Clear SET AO
Clear SET DO
Clear DEV 0 CaNT
Clear SLOW CYCLE A
InternaI ControI Pu Ise Train
Following PK ClR, ClK (clock) pulses arrive at the DM09A control logic and are used to
generate an internal DM09A control pulse train via the circuitry of Figure 4-1.
Ti me re lationships are illustrated in Figure 4-2. The pulse train is generated whenever the
system is operat i ng •
4

4.2.3
o
ClK ---+---JII
150fl
W005
A23
D
H
'VA
RIll
A21 F
U
A D
PHASE PHASE
W005
A23
W005
A23
u
Figure 4-1 Control Pulse Train Circuitry
WI)05
A23
ClK -----.U
U
I
A PHASE
~oons-n~------'n'---------
I
!-14-------650ns----n n
lOAD AMEMA ----:-1-----------' ..... ----------' ~---
.. ~----7oons----n n
D PHASE __ --'- ________ ----=.J L.. ________ --I L.. __ _
I
I
I
I
Figure 4-2 Control Pulse Train Time Relationship
Sing le-Fast-Input Cycle
The DM09A adapter/multiplexer is uti lized during the memory read/write cycle. During
this time the I/O device break request flag is set providing the DM09A with a CH 0 BK RQ level.
Referring to Table 4-1 and the referenced engineering drawings, internal control logic operations serve
to generate an AM RQ level. This level is applied to the PDP-9 memory control circuitry shown on
drawing D-BS-MC70-B-1 (sheet 2). A ClK pulse marking the beginning of the SYNCING time state
is then produced. During SYNCIN G, the centra I processor has access to core memory. CLK, delayed
100 ns, generates SYNC ClK to set the AM SYNC flip-flop in memory control via AM RQ{l). AM
5

SYNC(l) produces AM SYNC(l)B and AM SYNC BUS(l). AM SYNC(l)B is utilized by CM (control
memory) timing to prevent SM(l) from restarting the CM on the next ClK pulse which marks the begin-
ning of the DATA XFER time state.
The DATA XFER time state is entered via another PDP-9 ClK pulse. ClK, delayed 50 ns,
is POST ClK and resets the MODE flip-flop conditioned by AM SYNC(l). MODE(O) signifies AM
access to memory whi Ie MODE(1) signifies CP access to memory. PRE-WRITE OFF of the previous core
memory cycle (SYNCING) sets the MEM DONE flip-flop and produces AM GRANT. If an EAE or an
lOT instruction immediately precedes the DM09A request, AM GRANT is not produced. In this case
AM SYNC(l)B is delayed to generate AM GRANT SMlTD (simulated).
During the current time state, I/O device 0 address bits are present at the input gating
circuitry of the AM REGISTER (refer to drawing DM-3(2». Address bits uti lized by a PDP-9 with basic
memory are designated CH 0 ADDR BIT 05 through CH 0 ADDR BIT 17. The bits are applied to the
inverter modules shown. ADDR 0, the result of DEY 0 CONT(O) and SET DO(1), allows the address
bits
access to the jam input gates of the AM REGISTER as lAM 05 through lAM 17.
An AMI (adapter multiplexer input) pulse jam transfers the 13-bit address into the register.
AMI is the result of AM GRANT* or AM GRAND SMlTD. The flip-flops designated AMEMA 03 and
AMEMA 04 are used with PDP-9 systems containing extended memory banks. Inverter inputs are CH 0
ADDR BIT 03 and SET AO(l) for AMEMA 03 and CH 0 ADDR BIT 04 and SET AO(l) for AMEMA 04.
lOAD AMEMA jam transfers the extended memory addressing bits into their respective flip-flops. This
pulse is produced 650 ns after ClK by the control pulse train circuitry described in S.ection 4.2.2.
Following memory addressing, an 18-bit data word is jam transferred into the AM REGISTER.
I/O device 0 data word consists of CH 0 DATA BIT 00 through CH 0 DATA BIT 17. The data 'word is
also applied to a network of inverter modules. The enabling signal is DEY O. The data word is jam
transferred into the AM REGISTER by a second AMI pulse which is produced by AM STROBE.
4.2.4
Single-Slow-Output Cycle
Table 4-2 illustrates the signal flow associated with a Single-Slow-Output cycle. The
I/O device is programmed to indicate that an output transfer is to take place, the number of words to
be transferred and the address of the first word, DM09A control logic operations which result from this
type of data transfer are basically simi lar to those of the Single-Fast-Input cycle. The I/O device
requests multiplexer service via CH 0 BK RQ. The control logic proceeds to generate AM RQ and
AM RQ NEG. SYNC 0(1) and CH 0 FAST RQ condition the set DCD gate of the SLOW CYCLE A
*Both may
be present but the circuit is a logical OR.
6

flip-flop which is set by the positive going transition of AM RQ NEG. Following logic operations in
the multiplexer and in the PDP-9, an AM GRANT pulse is issued to produce AMI. With input transfers,
this pulse jam transfers
the device supplied address into the AM register. This is not necessary with the
current type of transfer.
Following further DM09A control logic operations, similar to those of Single-Fast-Input
cycle, PDP-9 AM STROBE arrives at the DM09A. This pulse is gated with CH 0 RQ IN and SET DO(l)
to produce SAl (sense amplifier input) thus allowing PDP-9 sense amplifier bits SA 00 through SA 17
access to the jam input gates of the AM register. A second AMI pulse is produced at this time to jam
transfer these bits into the AM register.
4.2.5
Doub Ie (Back to Back)-Fast-Output Cyc les
Signal flow for the current transfer type is given in Table 4-3. Initial signals sent to the
DM09A control logic are CH 0 BK RQ, CH 0 FAST RQ and CH 0 RQ IN. CH 0 BK RQsignals the
DM09A that service is requested. This signal and internal SLOW CYCLE A(O) produce SYNC 0 EN to
condition the set DCD gate of the SYNC 0 flip-flop. The D PHASE pulse preceding the SYNCING 1
time
state sets SYNC 0 to establish device priority. This conditions the CH 0 FAST CLR and sets the
DCD gate to produce AM RQ and AM RQ NEG. AM RQ signals the PDP-9 that a DMA cycle is de-
sired; the computer responds with AM SYNC(l) B.
The A PHASE
pulse of SYNCING 1 sets SET AO and generates CLR SYNC. This clears
SYNC O. SET AO(l) and AM SYNC(l)B generate SET DO EN which conditions the set DCD gate of the
SET DO fl ip-flop.
The following D PHASE pulse sets SET DO. SET AO(l) and SET DO(l) produce CLR SLW CYC
EN
which with A PHASE, maintains SLOW CYCLE A(O), a characteristic of fast transfers. SYNC 0 is
set again because SLOW CYCLE A(O) and CH 0 BK RQ are sti II present. Setting SYNC 0 generates
another AM RQ signa I. Because this signal is applied to the PDP-9 AM SYNC fl ip-flop prior to SYNC
CLK, the flip-flop remains set.
The PDP-9 produced AM GRANT arrives at the multiplexer control circuitry as the DATA
XFER 1 and SYNCING 2 time states are entered. The pulse jam-transfers address information into
the AM REGISTER. During these time states the data transfer associated with the preceding syncing
operations, and syncing operations for the next data transfer take pla.ce.
AM STROBE arrives from the PDP-9 and generates SAl and AMI, thus a Ilowi ng the sense
amplifier bits, SA 00 through SA '17, access through the AM register gating circuitry and into the
AM register•
DATA XFER 2 is entered. SET AO is cleared and operations simi lar to DATA XFER 1 take
place to jam transfer the data bits of the second word into the AM register. The D PHASE pulse at
the end of the current time state cI ears SET DO.
7

Time
Control
State Pulse
D
PHASE
SYNCING A PHASE
D PHASE
DATA XFER A PHASE
D PHASE
Table 4-1
Single-Fast-Input Cycle Signal Flow
Signal Conditions
SYNC 0 EN CH 0 BK RQ * SLOW CYCLE A(O)
SYNC 0(1) D
PHASE * SYNC 0 EN
AM RQ
SYNC 0(1)
AM SYNC(l)B
From PDP-9
SET AO(l) A
PHASE * SYNC 0(1)
CLR SYNC A PHASE * AM SYNC(l )B(B)
SET DO EN
AM SYNC(l)B * SET AO (1)
CH 0 FAST CLR
CLR SYNC * SYNC 0 (1)
SYNC 0(0) SYNC 0(1) *
CLR SYNC
SET DO(l)
D PHASE * SET DO EN
CLR SLW CYC EN SET AO(O) * SET DO(l)
AM GRANT From PDP-9
CH 0 ADDR ACC A PHASE * SET AO(l) * SET DO(l)
IN
DEV 0 CONT(l) CH 0 ADDR ACC IN * SET DO(l)
DEVICE 0
DEV 0 CONT(l) * SET DO(l) * CH 0 RQ IN
SET AO (0)
A PHASE * SYNC 0(0) * SET DO(l)
CH 0 ADDR ACC
CH 0 AD DR ACC IN
SLOW CYCLE A(O)
A PHASE * CLR SLW CYC EN
AM STROBE From PDP-9
CH 0 DATA RDY
D PHASE * SET DO(l) * SLOW CYCLE D(O)
IN
INH 0 DAP(O)
CH 0 DATA RDY IN
CH 0 DATA RDY CH 0 DATA RDY IN
CH 0 DATA ACC
DPHASE *CH ORQIN * INHODAP(O)*SETDO(l)
SET DO(O)
D PHASE * SET AO(O) * SLOW CYCLE D(O)
Drawing
Number
DM-2(2)
DM-2(1)
DM-2(2)
MC-1 (2)
DM-2(1)
DM-2(2)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
DM-2(1)
MC-1 (2)
DM-2(1)
DM-2(1)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
MC-2
DM-2(2)
DM-2(2)
DM-2(2)
DM-2(l)
DM-2(1)

Time Control
State Pulse
SYNC
D PHASE
SYNCING A
PHASE
D PHASE
DATA XFER
A PHASE
D PHASE
Table 4-2
Single-Slow-Output Cycle Signal Flow
Signal Conditions
SYNC 0 EN
CH 0 BK RQ * SLOW CYCLE A(O)
SYNC 0(1) D
PHASE * SYNC 0 EN
AM RQ
SYNC 0(1)
i
SLOW CYCLE A(l) SYNC 0(1) *
CH 0 FAST RQ * AM RQ NEG -+ 0
AM SYNC(l)B
From PDP-9
SET AO(l) A
PHASE * SYNC 0(1)
CLR SYNC A
PHASE * AM SYNC(l)B(B)
SET DO EN
AM SYNC(l)B * SET AO(l)
CH 0 FAST CLR CLR
SYNC * SYNC 0 (1)
SYNC 0(0)
CLR SYNC * SYNC 0(1)
SET 00 (1)
D PHASE * SET DO EN
AM GRANT
From PDP-9
CH 0 ADDR ACC
A PHASE * SET AO(l) * SET 00(1)
IN
DEV 0 CONT(l)
CH 0 ADDR ACC IN * SET DO(1)
SET AO(O)
A PHASE * SYNC 0(0) * SET 00(1)
CH 0 AD DR ACC
CH 0 ADDR ACC IN
CLR SLW CYC EN
SET AO(O) * SET D(l)
SLOW CYCLE A(O)
A PHASE * CLR SLW CYC EN
AM STROBE
From PDP-9
AMI
AM STROBE + AM GRANT
SAl
AM STROBE * CH 0 RQ IN * SET DO(l)
SET DO(O)
D PHASE * SET AO(O) * SLOW CYCLE D(O)
Drawing
Number
DM-2(2)
DM-2(1)
DM-2(2)
DM-2(1)
MC-1(2)
DM-2(1)
DM-2(2)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
MC-1 (2)
DM-2(1)
DM-2(1)
DM-2(l)
DM-2(1)
DM-2(1)
DM-2(l)
MC-2
DM-2(2)
DM-2(2)
DM-2(1)

Table 4-3
Double (Back to Back)-Fast-Output Cycles Signal Flow
Time Control Signal Conditions Drawing
State Pulse Number
SYNC 0 EN
CH 0 BK RQ * SLOW CYCLE A(O) DM-2(2)
D
PHASE SYNC 0(1) D
PHASE * SYNC 0 EN
DM-2(1)
AM RQ
SYNC 0(1) DM-2(2)
AM SYNC(l)B
From PDP-9 MC-1 (2)
SYNCING 1 A
PHASE
CLR SYNC A PHASE * AM SYNC(l)B(B) DM-2(2)
CH 0 FAST CLR
CLR SYNC * SYNC 0(1) DM-2(1)
SET AO(l) A
PHASE * SYNC 0(1) DM-2(1)
SET DO EN
SET AO(1) * AM SYNC(l)B DM-2(2)
SYNC 0(0)
CLR SYNC * SYNC 0(1) DM-2(1)
D
PHASE SET DO(l)
D PHASE * SET DO EN
DM-2(1)
SYNC 0(1) D PHASE * SYNC 0 EN
DM-2(1)
-
a
AM RQ SYNC 0(1) DM-2(2)
AM GRANT
From PDP-9 MC-2(1)
DATA XFER 1 A
PHASE
CH 0 ADDR ACC
A PHASE * SET AO(l) * SET 00(1)
SYNCING 2 IN
DM-2(1 )
CH 0 ADDR ACC
CH 0 ADDR ACC IN DM02(l)
DEV 0 CONT (l)
SET DO(1) * CH 0 ADDR ACC IN DM-2(1)
AM STROBE
From PDP-9 MC-2
SAl
CH 0 RQ IN * SET DO(l) * AM STROBE
DM-2(2)
SYNC 0(0)
CLR SYNC * SYNC 0(1) DM-2(l)
CH 0 FAST CLR
CLR SYNC * SYNC 0(1)
DM02(1)
D PHASE
CH 0 DATA RDY
D PHASE * SET DO(1) * SLOW CYCLE D(O)
DM-2(2)
IN
CH 0 DATA RDY
CH 0 DATA RDY IN DM-2(2)
AM GRANT
From PDP-9 MC-2(l)
CLR SLW CYC EN
SET AO(O) * SET DO(1)
DM-2(l)
DATA XFER 2 A
PHASE
SLOW CYCLE A(O)
A PHASE * CLR SLW CYC EN
MC-2(1)
CH 0 ADDR ACC
A PHASE * SET AO(l) * SET DO(l)
DM-2(1 )
IN
DM-2(1 )
CH 0 ADDR ACC
CH 0 ADDR ACC IN
AM STROBE
From PDP-9 MC-2
SAl
CH 0 RQ IN * SET DO(l) * AM STROBE
DM-2(2)
D
PHASE
SET DO(O)
D PHASE * SET AO(O) * SLOW CYCLE D(O)
DM-2(1)

5. ACCEPTANCE TEST PROCEDURE
Acceptance testing of the DM09A option consists of executing Test Procedure DM09A-O
with the DM09A Tester at both normal operating conditions and the voltage margins specified below.
Trial Test
Aggravation
Condition
1 DM09A-O
None
2 DM09A-O
Margin rack A
3 DM09A-O
Margin rack B
Minimum margin
specifications for rack A and rack B are listed below.
Margin
+10V -15V
+6V I -6V
+4V , -4V
6. MAINTENANCE
6.1 General
The general maintenance procedures described in the PDP-9 maintenance manual also
apply to the DM09A option.
6.2 Delay Adjustments
Adjust the R302 Delay at A27 according to the data given on engineering drawing DM-2(2).
6.3 Module Complement
Table 6-1 lists the module complement of the DM09A option.
11

Table 6-1
Module Complement
DEC Type
Module Type
Quantity
Recommended Spare Quantity
B169 Inverter
17 2*
B213 Jam
Flip-Flop
14
1*
R002 Diode Cluster
2 1*
R111 Diode Gate
12
1*
S107
Inverter
2 1*
S202 Dual
Flip-Flop
7 1*
S203 Triple
Flip-Flop
1 1*
S603 Pulse Amplifier 5
W005 Clamped Loads 3 1*
W300
Delay Line 1 1
W612 Pulse Amplifier S
R302
One-Shot De lay 1 1*
*Contained in the basic processor spare parts kit.
7. ENGINEERING DRAWINGS
Table 7-1 lists the DEC engineering drawings associated with the D"A09A option.
Drawing Number
DM-2(1)
DM-2(2)
DM-3(1 )
DM-3(2)
DM-4(1)
DM-4(2)
DM-5
DM-S(l )
DM-S(2)
Table 7-1
Engineering Drawings
Title
DMA Adapter Multiplexer Control BS-DM09-A-2
DMA Adapter Multiplexer Control BS-DM09-A-2
AM Register BS-DM09-A-3 Sheet 1 of 2
AM Register
BS-DM09-A-3 Sheet 2 of 2
Cab Ie Diagram BS- DM09-A-4 Sheet 1 of 2
Cable Diagram BS-DM09-A-4 Sheet 2 of 2
Module Uti
Iization MU-DM09-A-5
Sheet 1 of 2
Sheet 2 of 2
DM09A Timing Diagram TD-DM09-A-S Sheet 1 of 2
DM09A Timing Diagram TD-DM09-A-S Sheet 2 of 2
12
Revision
J
J
B
B
0
A
H
0
0

D
c
B
A
8 7
CH ¢ ADDR ~ee LN
H..J
ST
CH ¢ ADOI'< ACC
5T
SET AI(I) K
S=:T 0 1(1) L
HJ
6
PWR CL R POS----'---t:I--r==-:----=.-f--L--------O'-i'=-.!-='-i-...l-------C>J--i==-'--'::.....;:...l
D PHASE.
S=:T A ¢ (rf;)
SLOW c.YCl:E:Otf), =:
A PHAS.E
'.3ET D ¢(I)
PWR CLR
D PHASE
CLR SYNC .=:..(:{;?3:}---+------'.N,,-o!8j--+--------'D~C8:I
:E.N
'SYNC I (I)
'SYNC 2..(I~
8 7
\...
6
5 4 3 2
CH I ADDR Ace IN
CH 2 ADDR Ace IN
1'\
D
CH I ADDR Ace
CH 2. ADDR Ace
CH ¢ DATA Ace
CH I Rq IN
wl1Jr/is
CI9
58" A2 (I)
SET D2(1)
Ace
eN 2 RQIN_~~~
SLOW CYCLE 0 (I)
eLR
W~rj5
C.19
CH '2. F ..... ST C.LR
CH ¢ OAT A RDY HJ
CH I DATA RD'I IN
CH 2 D"TA RDY IN
SHA¢(;)
SET D <)(1)
CH if; ADDR. ACe. ~N
CH I "'-DDR ACC IN CH e ADOR Ace IN
5
DPHASE:
.s T ;:, T
SLOW· CYCLE 0(1) K
A PIfAS£' ---1>Ei;;;:"\--;;>f)<:]
CH 2. DATA Ace
c
PWR CLR POS --;;:O-=;=-''-=--=T-'
/I PHitS~
fl M. RQJi EG.
CH i
CH 2 B
t----------...-------+-----<O CLR SLW eye EN
3
A
2
BS-DM09-A-2 Sheet 1 of 2 DMA Adapter
Multiplexer Control
13

D
c
B
A
',7?5
r 2.(.'
8
CH
CH ¢ DATA RDY IN
H F
CH 0 RQTN --q~("V
IS/()7
824
8
7 6
• EN ~5ET D ~SET D Z EN
I-- __ --'-K~ .. I---~~N AM SYNC(i)e.CB')
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BS-DM09-A-2 Sheet 2 of 2 DMA Adapter
Multiplexer Control
15