Digital Equipment DV11 User manual

DV11 communications
multiplexer
user's manual

DV11 communications
multiplexer
user's manual
EK-OV11-0P-001
digital equipment corporation • maynard, massachusetts

Copyright © 1976 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject
to change without notice.
Digital Equipment Corporation assumes no respon-
sibility for any errors which may appear in this
manual.
Printed in U.s.A.
This document was set on DIGITAL's DECset-8000
computerized typesetting system.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-l0
DECSYSTEM-20
DECtape
DECUS
DIGITAL
MASSBUS
PDP
RSTS
lYPESET-8
lYPESET-ll
UNIBUS
1st Edition, December 1976

CHAPTER 1
1.1
1.2
1.2.1
1.2.1.i
1.2.1.2
1.2.2
1.3
1.3.1
CHAPTER 2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.4.1
2.1.4.2
2.1.4.3
2.1.5
2.2
2.3
2.3.1
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.5
CHAFfER 3
3.1
3.1.1
3.1.2
3.1.2.1
3.1.2.2
3.1.2.3
3.1.2.4
3.1.3
3.1.3.1
3.1.3.2
3.1.3.3
3.1.3.4
3.1.3.5
3.1.4
3.1.4.1
3.1.4.2
CONTENTS
INTRODUCTION AND GENERAL DESCRIPTION
PURPOSE AND SCOPE ........... .
DVII COMMUNICATIONS MULTIPLEXER .
DVll Overview Block Diagram
Establishing the Data Link
DVll Operation . .
Reference Documents
PHYSICAL DESCRIPTION
General Specifications
INSTALLA nON
SITE PREPARATION AND PLANNING
Minimum Through Maximum Configurations .
Compatibility Considerations and Precautions
Interface Specifications and Signals . . . . .
Interrupt Priorities and Address Assignments
Interrupt Priorities ........ .
Interrupt Vector Address Assignment
Address Assignments
Environment ............ .
UNPACKING AND INSPECTION .... .
INSTALLATION OF BASIC ASSEMBLIES
Unibus Cable Interconnections ....
MODULE INSTALLATION AND CUSTOMIZING
Unibus and Interrupt Vector Address Assignments
Synchronous Parameter Selection
Resistance Checks .....
Installation of Add-On DVll
SYSTEM CHECKOUT ..... .
PROGRAMMING
PROGRAMMABLE FACILITIES AND FUNCTIONS
Programmable Registers
Control Table . . . . . . .
Control Table Format
Receive Control Byte
Transmit Control Byte
Control Byte Symmetry
Operations With Directly-Addressable Registers
Modem Setup and Control
Accessing Secondary Registers
Data Transfer Enabling
Interrupt Enabling and Response
Extended Memory Addressing
Protocol Processing ....... .
BCC Polynomial Selections
Processing Block Terminations
iii
Page
1-1
1~1
1-1
1-2
1-2
1-3
1-3
1-3
2-1
2-1
2-1
2-2
2-2
2-2
2-2
2-2
.... ....
~-~
2-4
2-4
2-5
2-5
2-5
· 2-13
· 2-16
.. 2-16
· 2-17
3-1
3-1
3-4
3-4
3-4
3-5
3-5
3-5
3-5
3-6
3-6
3-6
3-6
3-6
3-6
3-6

3.1.4.3
3.1.4.4
3.1.4.5
3.1.4.6
3.1.4.7
3.1.5
3.1.5.1
3.1.5.2
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
3.3.10
3.3.11
3.3.12
3.3.13
3.3.14
3.3.15
3.3.16
3.4
3.5
3.5.1
3.5.2
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.4.1
3.6.4.2
3.6.5
3.6.5.1
3.6.5.2
CONTENTS (Cont)
Page
Control Byte Inhibit ... . . . . . . . . . . . . . . . . . . . 3-7
Sync Character Selection . . . . . . . . . . . . . . . . . . . 3-7
Sync/Mark State Select . . . .
.. ............ 3-7
Stripping Received Syncs ...................... 3-7
Line Activity Snapshot . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Data Transfer Operations
.................... 3-7
Provision for Alternate Data Transmission Tables ............ 3-7
Table Size and Location . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
DIRECTLY-ADDRESSABLE REGISTERS
.................. 3-8
System Control Register (SCR) . . . . . . . . . . . . . . 3-8
Line Control Register (LCR)
.......... 3-8
Receiver Interrupt Character Register (RIC)
.... 3-15
NPR Status Register (NSR)
.. . . . . . . . . . . . . . . . . 3-15
Reserved Register
..... . . . . . . . . . . . . . . . . . . 3-20
Special Functions Register
(SFR) . . . . . . . . . . . . . . . 3-20
Secondary Register Selection Register (SRS) .... . . . . . . . 3-20
Secondary Register Access Register (SAR) ..... . . . . . . . 3-24
Modem Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
INDIRECTLY ADDRESSABLE (SECONDARy) REGISTERS ............... 3-29
Transmitter Principal Current Address
(0000) . . . . . . . . . . . 3-29
Transmitter Principal Byte Count (000
I) .. . . . . . . . . . . . . . . 3-29
Transmitter Alternate Current Address
(0010) .. . .......... 3-32
Transmitter Alternate Byte Count
(00 II) . . . . . . . 3-32
Receiver Current Address (0100)
......... . ........ 3-32
Receiver Byte Count
(0101) ............ . .......... 3-32
Transmitter Accumulated Block Check Character (0110)
............... 3-32
Receiver Accumulated Block Check Character (0111)
.... , .... 3-32
Transmitter Control Table Base Address
(I (00) . . . . . ... . 3-33
Receiver Control Table
Base Address (100 1) . . . . . . .. . . 3-33
Line Protocol Parameters
(1010) ....... . . . . . . .. 3-33
Line State
(lOll) ... . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-33
Transmitter Mode Bits (1100) . . . . . . . . . .
.. 3-33
Receiver Mode Bits (1101)
.... . . . . . . . . . . .. 3-33
Line Progress (1110)
.......... . .............. 3-33
Receiver Control Byte Holding
(1111) . . . . . . . . . . . . . 3-33
CONTROL BYTE FORMAT. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
DVl1 INITIALIZATION . . . . . . . . . . . . . .............. 3-41
Line Modem Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
DVl1 Data Transfer Setup. . . . . . . . . . . . . . . . . .. . ..... 3-41
DATA TRANSFER IMPLEMENTATION
....................... 3-41
Originating and Answering Calls . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
Resynchronization During Reception . . . . . . . .
.. ........... . 3-42
Termination
of Transmission and Reception ........... . . 3-42
BISYNC Implementation ... . . . . . . . . . . . . . . 3-43
Transmission Control
.................... . . 3-43
Reception Control . . . . . . . . . . . . . . . . . . . . . . . . 3-43
DDCMP Implementation
...... . . . . . . . . . . . . . . . . . . . . . . 3-47
Transmission Control . . . . . . . . . . . . . .
..... 3-47
Reception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
iv

CONTENTS (Cont)
APPENDIX A PDP-II MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS
APPENDIX B PROTOCOLS
FOR BINARY SYNCHRONOUS COMMUNICATIONS
APPENDIX C GLOSSARY OF TERMS AND ABBREvlA nONS
Figure No.
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Table No.
1-1
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
ILLUSTRATIONS
DVll Overview Block Diagram
DV
11 Communications Multiplexer
DVll Interconnection Diagram
Module Utilization Diagram
Title
DVll M7836 Module -Device Address Selection Switches
DVll M7837 Module - Interrupt Vector Address Selection
Switches for DVll Data Handling Section ........ .
DVll M7807 Module -Device Address Selection Jumpers
and
Interrupt Vector Address Selection Jumpers for DVll
Modem Control Unit .. . . . . . . . . . . . . . . . . . .
Location
of Sync Switches on M7839 Module ...... .
Distribution Panel and Test Connector
Jumper Configuration
Control Byte Address
Control Byte Formats
DV
11 Primary Registers
DVl1 Secondary Registers
BISYNC Transmission Flow Diagram
BISYNC Reception Flow Diagram .
DDCMP Transmission Flow Diagram
DDCMP Reception Flow Diagram
TABLES
Title
Reference Documents
EIA Electrical Specifications
Device Address Switches
..
Vector Address Switches for Data Handling Section
Vector Address Jumpers for Modem Control Unit
Synchronous Parameter Selection Switches
Functions of DVII Programmable Registers
System Control Register Bit Assignments
Line Control Register Bit ASSignments
(For Synchronous Line Cards) .....
v
Page
Page
1-2
1-5
2-4
2-6
2-7
2-8
· 2-9
· 2-14
· 2-18
3-4
· 3-5
· 3-9
· 3-30
... 344
· 3-46
.. 3-48
.. 3-49
Page
1-4
2-3
· 2-10
· 2-11
· 2-12
· 2-15
3-2
3-12
· 3-14

Table No.
34
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
TABLIS (Cont)
TItle
Line Control Register Bit ASSignments
(For Asynchronous Line Cards)
Receive Function Interrupt Conditions
(For Synchronous Line Cards) ....
Receive Function Interrupt Conditions
(For Asynchronous Line Cards)
Transmit Function Interrupt Conditions .....
Control Status Register Bit Assignments
Line Status Register Bit Assignments
line Protocol Parameters Secondary Register Bit Assignments
Line State Secondary Register Bit ASSignments
Line Progress Secondary Register Bit Assignments
Control Byte Bit Assignments ...... .
Transparent Data Transmission Control
Non-Transparent Data Transmission Control
vi
Page
· 3-16
· 3-21
· 3-22
· 3-24
· 3-25
· 3-28
· 3-34
· 3-35
· 3-37
· 340
· 345
· 3-45

CHAPTER 1
INTRODUCTION AND GENERAL DESCRIPTION
1.1 PURPOSE AND SCOPE
This manual is intended to provide operational pro-
gramming information for the DVll Commu-
nications Multiplexer.
The manual consists of three
chapters plus appendices:
Chapter I provides an introduction and overall
functional and physical descriptions
of the
DVII;
Chapter 2contains site preparation, interfacing,
and installation information;
Chapter 3 includes all information necessary for
operation of the DV II via the PD P-II
program;
Appendices contain reference data, commu-
nications introductory data,
and an extensive
glossary
of terms and abbreviations.
The reader unfamiliar with communication line pro-
tocols should read Appendix B before attempting
Chapters I and 3.
Terms unique to the DVII are generally defined at
their first appearance. However, should the reader
encounter a word
that is not fully understood, refer
to the glossary provided in Appendix C before
proceeding.
1.2 DVII COMMUNICATIONS
MULTIPLEXER
The DV II is a communications multiplexer for the
PDP-II family of computers. By means of the DVII,
I-I
8 or 16 serial data lines can be multiplexed directly to
PDP-II core memory for bidirectional data transfer.
The
DVII is intended for use with a PDP-II-program
that provides the rules
or protocol which govern the
data transfers
and the generation and interpretation
of data link control and character codes.
Protocols require processing to (1) monitor trans-
mitted and received characters in order to identify
and respond to control characters, (2) maintain a
record
of control and data transmission and recep-
tion sequences, and (3) compute the error checking
~ode (block check calculation) on each character
transmitted
or received. The DVII performs these
functions, thus relieving
the processor of this over-
head. A Core Memory Control Table, set up by the
PDP-II program, is used by the DVII to direct the
processing
of received and transmitted characters.
The control table
is comprised of control bytes,
which form a one-to-one correspondence with each
cha~acter transmitted or received.
1.2.1 D
VII Ol'eniew Block Diagram
Figure I-I
is a DV II overview block diagram, show-
ing the principal functional units,
and data and con-
trol lines for the DV II. The DVII consists of two
primary functional subsystems, as indicated on the
block diagram: a Modem Control Unit,
and a Data
Handling Section. The Modem Control Unit mon-
itors and controls operations of the line modems as
directed
by the PD P-II program. The Data Handling
Section sequences
and synchronizes transfer of data
between the modems and the PDP-II Unibus (effec-
tively, core memory).

MODEM CONTROL
INTERRUPT
SET-UP
MODEM
CONTROL
UNIT MODEMS
I
DATA LINES
TO
---------------~-----
REMOTE
MODEMS
VI
::l
CD
DATA HANDLING
Z ...------4
::l
SYNC 6FLAGS
Q.
MICRO- RECEIVED
o ...------f
~------ .. CHARACTER
Q. PROCESSOR SILO
...... ----t 8 ~-------"1
RECEIVER
INTERRUPT
CHARACTER
REGISTER
~--------~8~---------------------------------'
~--------~ 8 t---------------------------------------------
11- Z896
Figure I-I DVII Overview Block Diagram
1.2.1.1 Establishing the Data Link -
Data transfer is
enabled whenever
l.
An operator manually initiates a call to a
remote modem,
or the PDP-ll program
dials the remote number via the
DNll
Automatic Calling Unit; when the data
link
is established by the remote modem
answering the call, the
DVII Modem
Control Unit signals the
PDP-II program
via
an interrupt.
2. In response to a RING signal from a
remote modem, the
DVII Modem Con-
trol Unit interrupts the PDP-II program,
to initiate an exchange of signals that
establishes the data link.
1.2.1.2
DVII Operation -With the data link estab-
lished, the PDP-II program sets up the DVII Data
1-2
Handling Section to enable the data transfer between
the selected local modem
and core memory.
The serial/parallel interface is accomplished in the
receivers and transmitters. The receivers assemble
characters received from the serial data lines
and set a
flag each time a character
is assembled. The trans-
mitters disassemble parallel characters for transmis-
sion on the serial data lines and set a flag each time
another character can
be accepted for transmission.
The Master Scanner cyclically enables the receivers
and transmitters to route their flags to the
Microprocessor.
The Microprocessor is controlled by a Read-Only
Memory (ROM), which handles character transfers
and steps the Master Scanner. Once started by the
PDP-II program, the Microprocessor runs
continuously.