Dimtel iGp-5120F User manual

iGp-5120F Signal Processor
Technical User Manual
Author:
Dmitry Teytelman
Revision:
1.6
September 19, 2008

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CONTENTS
Contents
1 Regulatory Compliance Information 3
2 Introduction 4
2.1 Delivery Checklist . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 SystemOverview ......................... 4
2.3 Front Panel Features . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Rear Panel Features . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 GettingStarted.......................... 9
3 IOC Setup 10
4 Utilities and Selftest 12
4.1 Utilities .............................. 12
4.2 Selftest............................... 13
5 User Interface 16
5.1 Installation ............................ 16
5.2 StartingtheEDM......................... 17
5.3 DisplayPanels........................... 17
5.3.1 MainPanel ........................ 17
5.3.2 Control Panel . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.3 Coefficients Panel . . . . . . . . . . . . . . . . . . . . . 21
5.3.4 Coefficient Generator Panel . . . . . . . . . . . . . . . 22
5.3.5 TimingPanel ....................... 23
5.3.6 DrivePanel ........................ 25
5.3.7 Waveforms Panel . . . . . . . . . . . . . . . . . . . . . 27
5.3.8 Environmental Monitoring Panel . . . . . . . . . . . . 28
5.3.9 Device Controls Panel . . . . . . . . . . . . . . . . . . 29
5.3.10 8-channel ADC Panel . . . . . . . . . . . . . . . . . . . 31
5.3.11 GPIOPanels ....................... 31
5.4 Power Amplifier Panel . . . . . . . . . . . . . . . . . . . . . . 34
6 External Software Interface 34
7 Specifications 36
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CONTENTS
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8 Warranty and Support 40
8.1 Warranty ............................. 40
8.2 Support .............................. 40
9 Appendix A: Address Map 41
9.1 Registers.............................. 41
9.1.1 Overall Layout . . . . . . . . . . . . . . . . . . . . . . 41
9.1.2 Gateware Config Register . . . . . . . . . . . . . . . . 42
9.2 Drive pattern memory . . . . . . . . . . . . . . . . . . . . . . 44
9.3 Environmental monitor . . . . . . . . . . . . . . . . . . . . . . 45
9.4 MAX1202 8-channel ADC . . . . . . . . . . . . . . . . . . . . 46
9.5 AD8842 8-channel DAC . . . . . . . . . . . . . . . . . . . . . 47
9.6 ECLdelaylines.......................... 48
9.7 General-purpose digital I/O . . . . . . . . . . . . . . . . . . . 48
9.8 Memory .............................. 49
10 Appendix B: Connector Pinouts 50
11 Glossary 55
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Regulatory Compliance Information
1 Regulatory Compliance Information
This equipment requires a ground connection provided by the power source.
The exposed metal parts of the unit are connected to the power ground to
protect against electrical shock. Always use an outlet with properly con-
nected protective ground.
iGp-5120F was designed and tested to operate safely under the following
environmental conditions:
indoor use;
altitude to 2000 meters;
temperatures from 5 to 40 ◦C;
maximum relative humidity 80% for temperature 31 ◦C, decreasing
linearly to 50% @ 40 ◦C;
pollution category II;
overvoltage category II;
mains supply variations of ±10% of nominal.
iGp-5120F contains no user serviceable parts inside. Do not operate with
the cover removed. Refer to qualified personnel for service.
NOTE: This equipment has been tested and found to comply with the limits
for a Class A digital device, pursuant to Part 15 of the FCC Rules. These
limits are designed to provide reasonable protection against harmful inter-
ference when the equipment is operated in a commercial environment. This
equipment generates, uses, and can radiate radio frequency energy and, if
not installed and used in accordance with the instruction manual, may cause
harmful interference to radio communications. Operation of this equipment
in a residential area is likely to cause harmful interference in which case the
user will be required to correct the interference at his own expense.
NOTE: This Class A digital apparatus complies with Canadian ICES-003.
Cet appareil num´erique de la classe A est conforme `a la norme NMB-003 du
Canada.
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Introduction
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2 Introduction
2.1 Delivery Checklist
1. iGp-5120F chassis;
2. AC power cord;
3. 16-pin ribbon cable;
4. 6 dB SMA attenuator;
5. 0.91 m SMA-to-SMA cable;
6. Compact disk with software and documentation;
7. User manual;
8. CE declaration of conformity.
2.2 System Overview
ADC
Acquisition
memory
supply monitoring
Temperature and
Input
interface
USB
Output
RF clock
DACFPGA
Fiducial
Triggers
and digital I/O
Slow analog
USB driver EPICS IOC
Linux IOC
computer Ethernet
Figure 1: iGp-5120F block diagram
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2.2 System Overview
iGp-5120F signal processor is designed for the bunch-by-bunch feedback
and diagnostics in lepton storage rings. Functionally iGp-5120F implements
a baseband bunch-by-bunch processing channel configured for 5120 bunches.
Each bunch is processed in a 8-tap finite impulse response (FIR) filter before
being sent to the one-turn delay and, from there, to the high-speed digital-
to-analog converter (DAC).
A block diagram of the iGp-5120F system is shown in Figure 1. The main
signal processing chain consists of a high-speed analog-to-digital converter
(ADC), a field programmable gate array (FPGA), and a high-speed DAC
and is driven by the radio frequency (RF) clock. In addition to performing
real-time control computations, the FPGA interfaces to a number of on-
board devices, such as high-speed data acquisition memory (static random
access memory (SRAM)), low-speed analog and digital input/output (I/O),
as well as temperature and supply voltage monitors. In turn, the FPGA
uses an internal universal serial bus (USB) connection to communicate to
an embedded input-output controller (IOC) computer housed in the same
chassis. The IOC runs the Linux operating system and is connected to the
overall control system via the Ethernet.
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2.3 Front Panel Features
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2.3 Front Panel Features
1 32 4 5 6 7 8 109
Figure 2: Front panel features
1) Power switch This momentary-on lighted switch turns iGp-5120F on
and off. From the off condition, the unit will take 25–30 seconds to fully
boot. Shutdown time after power switch actuation is 5–10 seconds.
2) Low-speed DAC This 16-pin connector provides 7 general-purpose ana-
log outputs. DAC settings are adjustable via experimental physics and
industrial control system (EPICS).
3) Low-speed ADC This 16-pin input connector is provided for measuring
up to 8 external analog channels with 12-bit resolution.
4) Fast ADC Two SMA connectors accept the differential inputs for the
high-speed ADC. When a single input is used the full-scale (FS) swing
is 195 mV peak-to-peak. Differential mode swing is 97.5 mV peak-to-
peak.
5) RF Clock This input accepts the high stability bunch crossing clock sig-
nal (RF clock). Nominal input level is -3 dBm. The signal is internally
AC coupled.
6) Fiducial This input receives the revolution fiducial. Input is expected
to be NIM-level. Active edge is the 0 to −0.8 V transition. The signal
must be stable within one RF period for reliable operation.
7) Trigger 1 This input is currently unused.
8) Trigger 2 This NIM-level input is used as an external trigger for data
acquisition.
9) LEDs Eight front-panel LEDs provide indications of system activity and
operating status.
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2.3 Front Panel Features
STATUS FPGA Local bus activity is indicated in green.
SATURATION FIR filter operation status. Green indicates normal
operation, red — output saturation.
CLOCK MISSING Red indication when the input RF clock is not
detected.
DCM LOCK Lock status of the signal processing digital clock man-
ager (DCM). Green — locked, red — unlocked.
FIDUCIAL ERROR Red indication if the fiducial is missing, at the
wrong frequency, or jittering.
DCM2 LOCK (USER1) Lock status of the data acquisition DCM.
USER2 Data acquisition activity indicated in green.
USER3 Additional status of the signal processing DCM.
10) Fast DAC These two differential outputs are generated by the high-
speed DAC. For proper operation both outputs must be terminated
into 50 Ω.
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2.4 Rear Panel Features
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2.4 Rear Panel Features
1 32 4 5 6
Figure 3: Rear panel features
1) Voltage selection switch Slide switch for selecting appropriate mains
voltage: 115 or 230 V.
2) Power entry socket IEC-320 power input socket. Always use an outlet
with properly connected protective ground.
3) GPIO This 68-pin connector provides 32 low-voltage transistor-transistor
logic (LVTTL) signals for future expansion.
4) PS/2 keyboard Connect PS/2 keyboard for the initial setup of the iGp-
5120F.
5) Monitor output Connect a monitor for the initial setup of the iGp-
5120F.
6) Network This RJ-45 connector is used to connect the iGp-5120F to the
control network. All control and data acquisition communications with
the unit are performed via this network connection.
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2.5 Getting Started
2.5 Getting Started
In this section we will present a quick step-by-step guide to get your new
feedback processor running in a minimal configuration.
WARNING: Before connecting power to the unit make sure the
voltage selection switch (Fig. 3, item 1) is in the correct position
(115 or 230 V).
1. Configure voltage selection switch (Fig. 3, item 1). Mains supply re-
quirements for the iGp-5120F are listed in Table 8;
2. Connect RF clock at −3 dBm nominal level (Fig. 2, item 5);
3. Connect single-ended high-speed ADC input signal to Ain+ (Fig. 2,
item 4). The FS swing of this signal should be 190 mV peak-to-peak;
4. Connect a 50 Ω terminator to Ain- (Fig. 2, item 4);
5. Connect high-speed DAC output(s) (Fig. 2, item 10) to the appropriate
back-end unit;
6. If single-ended output configuration is used, connect a 50 Ω terminator
to the unused high-speed DAC output;
7. Connect a PS/2 keyboard (Fig. 3, item 4);
8. Connect a video monitor (Fig. 3, item 5);
9. Push the power button (Fig 2, item 1) to turn on the system;
10. Perform the IOC setup (see Chapter 3);
11. Push the power button (Fig 2, item 1) to turn the system off;
12. Disconnect the keyboard and the video monitor;
13. Connect the Ethernet (10/100BASE-T);
At this point your system is ready for internal testing and use in beam
diagnostics and feedback. To extend the configuration beyond the minimum
described above one can also connect the external fiducial and trigger signals
(NIM-level).
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IOC Setup
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3 IOC Setup
Setup program is included in the IOC for configuring the important features
of the iGp-5120F. The program can be executed locally or remotely. For
local execution one must first connect a keyboard (Fig. 3, item 4) and a
video monitor (Fig. 3, item 5) to the system. For remote setup, use ssh
after system bootup to establish connection. In both setup methods the
user must login as root (initial password is supplied with the system). If the
newly received iGp-5120F must be configured remotely (when, for example, a
keyboard or a monitor is not available), such configuration can be performed
using a dedicated network. Set up a network consisting of the iGp-5120F, a
network hub or a switch, and a remote computer. The iGp-5120F is delivered
with the following network configuration:
IP address 192.168.1.41
Netmask 255.255.255.0
Gateway 192.168.1.254
Configure the remote computer as follows:
IP address 192.168.1.254
Netmask 255.255.255.0
Gateway 192.168.1.41
Once the dedicated network is configured, remote connection to the iGp-
ging in locally or remotely, start the setup program as follows:
[root@IOC ~]# setup
Setup program presents a series of text-mode window dialogs to collect the
necessary information for configuring the iGp-5120F. The following settings
are configured in this process: timezone, date, time, network, root password,
and EPICS device name.
Setup dialogs are illustrated in Figure 4. Here we provide a step-by-step
guide through the setup process.
a) Welcome panel This panel provides a summary of settings handled by
the setup program.
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IOC Setup
(a) Welcome screen (b) Timezone (c) Date
(d) Time (e) Network (f) Password
(g) Device name
Figure 4: Setup screens
b) Timezone In this panel, select the appropriate timezone.
c) Date Set the correct date using the calendar.
d) Time Set the correct time. The initial setting is taken from the current
IOC time. If you know the current IOC time to be correct press OK
quickly to retain the setting as closely as possible.
e) Network Configure the IOC IP address, network mask and the default
gateway as provided by your network administrator. The DNS and
NTP server addresses are optional.
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Utilities and Selftest
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NOTE: Only set the DNS address if the server connection is fast and
reliable. Delays in DNS server access can negatively impact the opera-
tion of the IOC.
f) Root password Type in the new root password. The password must 5
to 8 characters in length. Please use the standard rules for selecting a
strong password (Not based on a dictionary word, a mix of upper and
lower-case characters and numbers).
g) Device name This device name is the second part of the EPICS process
variable (PV). All PV names start with IGPF:X:, where Xis the device
name. As delivered the iGp-5120F defaults to device name TEST pro-
ducing PVs of the form IGPF:TEST:DELAY. If multiple iGp-5120F units
are to be deployed they must be assigned differing device names. For
example, one could use device names X,Y,Zfor horizontal, vertical,
and longitudinal feedback channels.
NOTE: If the setup program is executed remotely and the network address is
changed, the ssh connection will hang at the end of the process. To connect
to the IOC, close the existing ssh session and start the new connection at
the newly assigned IOC IP address.
4 Utilities and Selftest
4.1 Utilities
The IOC includes several utilities designed to communicate to the iGp-5120F
directly, without using the EPICS softIOC software. These utilites allow the
user to access individual FPGA registers and memory locations. For register
descriptions and address map see Sec. 9. All of the utilities below will accept
addresses and data in decimal, hex, if preceded by 0x, and octal, if the value
starts from 0. For example, value 12 can be specified as 12,0xc,014. In
order for these utilities to gain access to the FPGA interface the IOC process
must be terminated. To terminate the IOC execute:
[root@IOC ~]# pkill st.cmd
Here is a short description of the available commands:
usbr <addr> Read a single register or memory location.
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4.2 Selftest
usbw <addr> <val> Write a single location.
usbrblk <addr> <len> Read a block of memory. The data is send to
stdout and can be redirected into a file.
usbwblk <addr> <len> Write a block of memory. This utility expects the
data from stdin.
usbtest <addr> <len> <cnt> Test the register or memory block specified
by the addr,len combination. The utility generates a block of random
numbers and writes it to the FPGA. Then the data is read back and
compared to the original values. Argument cnt specifies the number
of test cycles to perform.
4.2 Selftest
Another important utility included in the IOC is selftest. This program
performs testing of the main signal path, memories, and peripherals. In order
to perform the testing system hardware must be configured as follows:
Connect the 16-pin ribbon cable between the 7-channel DAC (Fig. 2,
item 2) and the 8-channel ADC (Fig. 2, item 3);
Connect 509 MHz clock to the RF clock input (Fig. 2, item 5);
Terminate Ain- fast ADC input (Fig. 2, item 4);
Terminate Aout- fast DAC output (Fig. 2, item 10);
Connect 6 dB attenuator to Aout+ fast DAC output;
Connect the output of the attenuator to Ain+ fast ADC input using
the supplied SMA-SMA cable;
Make sure no cable is connected to the general-purpose digital I/O port
(Fig. 3, item 3);
Make sure fiducial input is not driven (Fig. 2, item 6);
Once the hardware is configured the test procedure can be initiated by
typing selftest at the IOC command prompt (establish local or remote
connection to the IOC as described in Sec. 3). Example output of the test is
shown below:
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4.2 Selftest
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1 Terminating the IOC
2
3 System information :
4 Function : fe e dba c k
5 Harmonic number : 64
6 D emul t ipl e xin g : 4
7 R e v i s i o n : 1 . 0 1
8 S e r i a l number : iGp 0003
9
10 STARTING THE AUTOMATED TEST SEQUENCE
11
12 T est ing i n t e r n a l blockRAM : [OK]
13 T es ti ng e x t e r n a l SRAM: [OK]
14 T esti ng g en er al −purpose d i g i t a l i n p u t s / out pu ts : [OK]
15 V e r i f y i n g RF c l o c k p r e se n c e and DCM l o c k : [OK]
16
17 Te s ting low−speed DAC/ADC system
18 Ch(ADC) ADC(mV) DAC(mV) Off (mV) DAC(mV) ADC(mV)
19 1 −2040 −2062 5 2039 2025
20 2 −2024 −2039 −4 2039 2028
21 3 −2035 −2039 −3 2039 2033
22 4 −2029 −2039 2 2039 2035
23 5 −2025 −2039 8 2039 2030
24 6 −2033 −2039 −3 2039 2034
25 7 −2031 −2039 −3 2039 2035
26
27 Te s ting high−spe ed DAC o f f s e t channel
28 O f f s e t DAC( cn t ) Fast ADC( cn t )
29 −128 −17.3
30 66 1 . 0
31 127 6 . 9
32
33 Te s ting high−spe ed DAC output
34 HS DAC( cnt ) HS ADC( cnt )
35 −1574 −120.0
36 0 −0.0
37 1576 120.0
38
39 Environmental measurements
40 Bulk su pp ly v o l t a g e (1 2V ) : 1 2 . 0
41 Vcc s up pl y v o l t a g e ( 3 . 3V ) : 3 . 3
42 FPGA c o re s up pl y v o l t a g e ( 1 . 5V ) : 1 . 5
43 iGp bo ard t e mp e ra tu r e ( deg C ) : 2 5 . 7
44 ADC t em pe rature r i s e ( deg C) : 50 . 4
45 FPGA temp er at ure r i s e ( deg C ) : −0.3
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4.2 Selftest
46 FID c lo ck d e lay t emperature r i s e ( deg C) : 5 . 8
47 DAC cl o c k dela y temper at ur e r i s e ( deg C) : 6 .1
Line 1 The utility terminates the IOC process to gain access to the FPGA
interface.
Lines 3–8 Contents of the FPGA config register are parsed and printed out.
Line 12 Test of the data acquisition blockRAM.
Line 13 External SRAM test.
Line 14 General-purpose digital I/O is tested.
Line 15 Presence of the RF clock is verified as well as the lock status of the
DCMs.
Lines 17–25 A test of the low-speed DAC and ADC system. This test
uses 7 channels of the DAC to drive different voltages and measures
the voltages using the ADC. The test measures several parameters for
each channel. Test code finds the minimum DAC setting that does not
saturate the ADC. ADC reading (column 2) and the dead-reckoned
DAC output (column 3) are printed out in millivolts. Next the DAC is
set to 0 and the ADC reading (offset, column 4) is taken. Finally, the
code finds the maximum DAC setting that does not saturate the ADC.
Lines 27–31 This portion of the test uses channel 7 of the slow DAC to
adjust the output offset of the high-speed DAC ˙
The code extracts the
reading from the high-speed ADC at the positive and negative extremes
of the offset DAC. Next the code finds the offset DAC setting that
minimizes the high-speed ADC measurement. This setting should be
very close to the factory determined value used in EPICS to null the
high-speed DAC output.
Lines 33–37 This fragment verifies the response via the high-speed DAC.
To do so it finds the DAC settings to obtain readings of ±120 and 0
counts from the ADC.
Lines 39–47 Environmental monitor readings are taken and displayed.
The output of selftest utility can be redirected to a file and compared
to the factory measurement provided in /root/factory.selftest.
After testing restart the IOC process by typing:
[root@IOC ~]# iGp_start
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User Interface
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5 User Interface
User interface functionality for the iGp-5120F is implemented using extensi-
ble display manager (EDM). Software installation CD is designed for seamless
installation on a client computer, configured with Fedora 8 version of Linux
operating system.
5.1 Installation
Log into the client computer.
Insert the installation CD into the CD-ROM drive.
Mount the CD by accepting the ”Open in New Window” option or by
right clicking on the CD icon and selecting ”Mount”.
Open a terminal window.
Issue the following installation command:
sudo sh <CD mount point>/install.sh. Typically CD mount point
will be /media/iGp.Note: to install the software one must have supe-
ruser privileges, obtained either via sudo or su.
When prompted, enter the user name to install under. If the specified
user does not exist it will be created. Default user name is iGp.
When prompted, enter the installation directory. Default directory is
iGp.
If the specified user did not exist, the program will prompt for password.
Wait for the installation process to complete.
The resultant installation can support multiple IOCs with distinct device
names. Refer to Section 3 for a definition of the device name. Each IOC
must be added to the configuration. To to so, log in under the username,
specified during software installation (EPICS user). Open a terminal and
type:
[iGp@host ~]$ IOC_add <IP address> <device name>
WARNING: IOC and the client computer must be able to com-
municate at this point, otherwise IOC add will fail.
After adding one or more new IOCs to the configuration the user must
log out and log back in for the changes to take effect.
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5.2 Starting the EDM
5.2 Starting the EDM
Once the software has been installed and the IOCs added via IOC add you
are ready to start the EDM. iGp-5120F display panels are opened by the
following command:
[iGp@host ~]$ iGp_display [device name]
Note that the device name is optional. If the argument is omitted the com-
mand defaults to device name TEST.
5.3 Display Panels
5.3.1 Main Panel
Figure 5: Main (top-level) panel
Running iGp display brings up the top-level panel shown in Figure 5.
All of the display panels include two buttons on the top: HELP and EXIT.
EXIT button will always close the current window. In addition, EXIT button
on the top-level panel will close the EDM session.
Top-level panel consists of three elements: FEEDBACK ON/OFF con-
trol, SETUP button and the status border around this button. The FEED-
BACK ON/OFF control enables or disables the FIR filter output to the DAC.
The status border indicates system operational status summary. Green in-
dicates no errors, yellow - warning (saturation), red - error. The SETUP
button opens the control panel shown in Fig. 6.
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5.3 Display Panels
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5.3.2 Control Panel
Figure 6: Control panel
This window integrates most important controls for the iGp-5120F.
COEFFICIENT SET Feedback coefficient set selector.
SHIFT GAIN Output gain adjustment, each step doubles the feedback
gain.
DOWNSAMPLING Processing channel downsampling factor.
SAT. THRESHOLD iGp-5120F is equipped with an integrating satura-
tion counter. The counter is compared with a threshold duty cycle,
expressed here in percent. A setting of 50% indicates that the output
was saturated half the time. On every poll cycle (once a second) the
threshold comparison result is read out and the counter is reset to 0.
Value of 0 produces single saturation event detector within a polling
period,
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