DSP 1030 Assembly instructions

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DSP1030
4CHANNEL PROGRAMMABLE AMPLIFIER
USER REFERENCE MANUAL

dsp, TRAQ, and IRAQ-H are trademarks of DSP Technology Inc.
(C) 1988 All rights reserved.
DSP Technology, Inc. 48500 Kato Road, Fremont, CA., USA
[phone]

SECTION 1
INTRODUCTION
The DSP model 1030 is a 4 channel wideband amplifier packaged in a single width CAMAC
module. Input voltage ranges are selectable from +/-25mv to +/-25V in 1-2-5 steps. The input
impedance of each channel can be selected to be either 50 ohms or 1 megohm. Coupling for each
channel can be either AC or DC. Each channel's output can be offset +/-250mv in 2mv steps.
These parameters can be selected for each channel independently via the CAMAC dataway. All
setup parameters for each amplifier are stored in battery backed up memory.
DSP 1030 User's Manual August,1989 1

SECTION 2
SPECIFICATIONS
ANALOG INPUTS
Connector:
Impedance:
Full scale:
Gains:
Maximum input
voltage:
Bandwidth:
ANALOG OUTPUTS
Connector:
Impedance:
Output range:
Offset range:
Lemo coaxial
1megohm or 50 ohms, programmable via CAMAC dataway
50 my p-p to 50 V p-p 1-2-5 steps
.01, .025, .05, .1, .25, .5, 1, 2.5, 5, 10
a) With 1 megohm input impedance selected: +50 V
at input sensitivities of +25mv to +500mv. +250 V (DC + peak AC)
for other range settings.
b) With 50 ohm input impedance selected: 7 VDC (50mv to 10 V range)
-3db at > 100 MHz minimum for all gain settings.
Lemo coaxial
50 ohms, +2%
+/-250mv max; includes +/-250mv signal + offset (output terminated into 50
ohms)
+/-250mv, settable in approx. 2mv steps via the CAMAC dataway
DSP 1030 User's Manual August,1989 2

CAMAC COMMANDS
F(0) .A(0) .N: Read channe
F(0) .A(1) .N: Read channe
F(0) .A(2) .N: Read channe
F(0) .A(3) .N: Read channe
F(0) .A(4) .N: Read channe
F(0) .A(5) .N: Read channe
F(0) .A(6) .N: Read channe
F(0) .A(7) .N: Read channe
F(3) .A(0) .N: Read module
F(16) .A(0) .N: Write channe
F(16) .A(1) .N: Write channe
F(16) .A(2) .N: Write channe
F(16) .A(3) .N: Write channe
F(16) .A(4) .N: Write channe
F(16) .A(5) .N: Write channe
F(16) .A(6) .N: Write channe
F(16) .A(7) .N: Write channe
one control register (R1-R8)
two control register (R1-R8)
three control register (R1-R8)
four control register (R1-R8)
one offset register (R1-R8)
two offset register (R1-R8)
three offset register (R1-R8)
four offset register (R1-R8)
identifier (R1-R16)
one control register (R1-R8)
two control register (R1-R8)
three control register (R1-R8)
four control register (R1-R8)
one offset register (R1-R8)
two offset register (R1-R8)
three offset register (R1-R8)
four offset register (R1-R8)
DSP 1030 User's Manual August,1989 3

CONTROLS AND INDICATORS
LED INDICATORS
N
SELECTED CHANNEL
Indicates that the module is being addressed by the computer.
Four LED lamps one for each channel, indicating which
channel's status is being displayed on the front panel status
lights.
GAIN Four LED lamps that indicate the gain of the amplifier in the
selected channel, according to the encoding shown below:
GND
AC
HIZ
CONTROLS
SELECT
CONNECTORS
INPUT
OUTPUT
LED 3 LED 2 LED 1 LED 0 GAIN VFS
OFF OFF OFF OFF 10 50mv
OFF OFF OFF ON 5 100mv
OFF OFF ON OFF 2.5 200mv
OFF OFF ON ON 1 500mv
OFF ON OFF OFF .5 1v
OFF ON OFF ON .25 2v
OFF ON ON OFF .1 5v
OFF ON ON ON .05 10v
ON OFF OFF OFF .025 20v
ON OFF OFF ON .01 50v
When this lamp is on, the selected amplifier's input is
disconnected from its input connector and connected to ground
through a 50 ohm resistor.
When this lamp is on, the selected amplifier's input is AC
coupled.
When this lamp is on, the selected amplifier's input impedance
is 1 megohm; when it is off, the impedance is 50 ohms.
This pushbutton increments the selected channel by one each
time it is pushed. When the selected channel is channel 4,
the next push of the SELECT button selects channel 1.
Each of the four channels has a LEMO coaxial input
connector.
Each of the four channels has a LEMO coaxial output
connector.
DSP 1030 User's Manual August,1989 4

INSTALLATION OPERATION
R4 R3 R2 R1 GAIN VFS
0 0 0 0 10 50mv
00 0 1 5 100mv
0 0 1 0 2.5 200mv
0 0 1 1 1500mv
0100.5 lv
0 1 0 1.25 2v
0 1 10.1 5v
0111.05 10v
10 0 0 .025 20v
1 0 0 1 .01 50v
CAMAC CONTROL
F(0) A(0) N Read channel 1 controls. This command reports amplifier status regarding
gain setting, coupling, input impedance and enabled/ground state. Data on
the R lines reports the status according to the table below:
R5 = 0: Channe
R5 = 1: Channe
R6 = 0: Channe
R6 = 1: Channe
R7 = 0: Channe
R7 = 1: Channe
input impedance is 1 megohm
input impedance is 50 ohms
is DC coupled
is AC coupled
is enabled
is disabled and grounded
F(0) A(1) N Read channel 2 controls. This command reports amplifier status regarding
gain setting, coupling, input impedance and enabled/grounded state. Data
on the R lines reports the status according to the table shown for F(0) A(0)
N.
F(0) A(2) N Read channel 3 controls. This command reports amplifier status regarding
gain setting, coupling, input impedance and enabled/grounded state. Data
on the R lines reports the status according to the table shown for F(0) A(0)
N.
F(0) A(3) N Read channel 4 controls. This command reports amplifier status regarding
gain setting, coupling, input impedance and enabled/grounded state. Data
on the R lines reports the status according to the table shown for F(0) A(0)
N.
F(0) A(4) N Read channel 1 offset setting (R1-R8). R1-R8 represent a binary code, with
R1 being the LSB. A code of 0 indicates that the output of this channel
(terminated in 50 ohms), with no signal, will be offset -.25 volts. A code of
255 indicates that the offset is +.25 volts.
F(0) A(5) N Read channel 2 offset setting (R1-R8). R1-R8 represent a binary code, with
R1 being the LSB. A code of 0 indicates that the output of this channel
(terminated in 50 ohms), with no signal, will be offset -.25 volts. A code of
255 indicates that offset is +.25 volts.
DSP 1030 User's Manual August,1989 5

F(0) A(6) N
W4 W3 W2 W1 GAIN VFS
000 0 10 50mv
00 0 1 5 100mv
00102.5 200mv
001 1 1500mv
01 0 0.5 1v
01 0 1 .25 2v
0110.1 5v
011 1 .05 10v
1 0 0 0 .025 20v
100 1 .01 50v
F(0) A(7) N
Read channel 3 offset setting (R1-R8). R1-R8 represent a binary code, with
R1 being the LSB. A code of 0 indicates that the output of this channel
(terminated in 50 ohms), with no signal, will be offset -.25 volts. A code of
255 indicates that the offset is +.25 volts.
Read channel 4 offset setting (R1-R8). R1-R8 represent a binary code, with
R1 being the LSB. A code of 0 indicates that the output of this channel
(terminated in 50 ohms), with no signal, will be offset -.25 volts. A code of
255 indicates that the offset is +.25 volts.
F(3) A(0) N Read module identifier (R1-R16).
F(16) A(0) N Write channel 1 controls. This command sets amplifier gain, coupling, input
impedance and enabled/grounded state. W1-W7 control the status according
to the table below:
F(16) A(1) N
F(16) A(2) N
F(16) A(3) N
F(16) A(4) N
W5 = 0: Channe
W5 = 1: Channe
W6 = 0: Channe
W6 = 1: Channe
W7 = 0: Channe
W7 = 1: Channe
input impedance is 1 megohm
input impedance is 50 ohms
is DC coupled
is AC coupled
is enabled
is disabled and grounded
Write channel 2 contro s. This command sets amplifier gain, coupling, input
impedance and enabled/grounded state. W1-W7 control the status according
to the table for F(16) A(0) N.
Write channel 3 controls. This command sets amplifier gain, coupling, input
impedance and enabled grounded state. W1-W7 control the status according
to the table for F(16 A(0) N.
Write channel 4 controls. This command sets amplifier gain, coupling, input
impedance and enabled/grounded state. W1-W7 control the status according
to the table for F(16) A(0) N.
Write channel 1 offset DAC. This command writes data on W1-W8 to the
offset DAC. W1 is the LSB. A code of 0 offsets the output to -.25v. A code
of 255 offsets the output to +.25v. The output can be offset in 2mv steps
using the following expression.
Voffset = (0.500/256) * (code-128)
DSP 1030 User's Manual August,1989 6

F(16) A(5) N Write channel 2 offset DAC. This command writes data on Wl-W8 to the
offset DAC. W1 is the LSB. A code of 0 offsets the output to -.25v. A code
of 255 offsets the output to +.25v The output can be offset in 2mv steps
using the following expression.
✓offset = (0.500/256) * (code-128)
F(16) A(6) N Write channel 3 offset DAC. This command writes data on W1-W8 to the
offsets DAC. W1 is the LSB. A code of 0 offsets the output to -.25v. A code
of 255 offsets the output to +.25v. The output can be offset in 2mv steps
using the following expression.
✓offset = (0.500/256) * (code-128)
F(16) A(7) N Write channel 4 offset DAC. This command writes data on W1-W8 to the
offset DAC. W1 is the LSB. A code of 0 offsets the output to -.25v. The
output can be offset in 2mv steps using the following expression.
✓offset = (0.500/256) * (code-128)
DSP 1030 User's Manual August,1989 7

FUNCTIONAL DESCRIPTION
GENERAL
Refer to Fig.1, 1030 Block Diagram. The 1030 module contains four independent wideband
amplifiers, each with seperate controls for coupling, termination, gain, offset, and enable/disable.
These controls are accessible only from the CAMAC dataway. However, the status of each amplifier
(except for offset) can be viewed on front panel indicator lights. These lights indicate the status of
one channel, which is selected by operating the SELECT pushbutton. The channel currently being
displayed is also shown on the front panel LEDs.
In addition to the four amplifier channels, the module contains a block of logic to decode and
implement CAMAC commands, another block of logic to retain the setup information when the
power is shut down (battery backup), and a power supply and reference voltage section.
To isolate the amplifier channels from crosstalk and power supply noise, each amplifier has its own
ground plane as well as the liberal use of ferrite beads to reduce RF signals on power planes.
AMPLIFIER
GENERAL
Each amplifier has two stages. The first stage sets the coupling, enable/disable, and termination
parameters, and also does coarse signal attenuation and impedance transformation for the second
stage. Input protection is provided here also. The second stage provides gain, fine signal
attenuation and signal offsetting.
INPUT STAGE
Refer to Fig 2, 1030 Input Stage Diagram. Signals entering the amplifier go to terminals on two
relays. The first connects the input to a 50 ohm termination resistor, if desired; The second either
connects the amplifier proper to the signal input or to a 50 ohm termination, providing the
enable/disable function. Assuming that the amplifier is enabled, the signal next encounters the AC
coupling capacitor, with its shorting relay (for DC coupling). Next the signal encounters two parallel
2megohm attenuators, with a voltage attenuation factor of 1/10 or 1/100. A one-of three analog
multiplexer selects either the X 1, X 0.1, or X 0.01 attenuation to the following circuitry. The signal
thus selected is applied to the input of a FET voltage follower, which supplies a low impedance
drive to the output stage. The X 1 multiplexer relay, switchs in a capacitor to replace the input
capacitance of the FET follower in order to maintain a constant capacitance in the attenuator input
node.
DSP 1030 User's Manual August,1989 8

INPUT STAGE DETAILS
Refer to Sheet 2 of the Schematic Diagram. Only channel 1 will be described; All other channels
are identical. Signals enter via J1 on the front panel. K8 selects the 50 ohm termination, formed
by the parallel combination of R47 and R48. Relay K9 selects either the input signal or terminating
resistor R46. C54 is the AC coupling capacitor, in parallel with shorting relay K7. R44 provides a
current limit to the overload protection circuitry at the amplifier input when the X 1 attenuation is
selected by K6. C49 maintains compensation for the following RC attenuator networks. The 1/10
attenuator is formed by R37-R40, C47, C50 and C51. The variable capacitor C51 adjusts the low
frequency peaking of the attenuator section. The 1/100 attenuator is formed by R35, R36, R42,
R43, C42, C43 and C46. The variable capacitor C45 adjusts the low frequency peaking of the
attenuator section.
The X 1 switch on the 1-of-3 multiplexer is relay K6. Both contact sets are used to provide extra
"off' state isolation. C49 connects to the input terminal whenever the amplifier is switched
elsewhere, to assure that the amplifier input capacitance remains constant at all gain settings. The
X0.1 switch is K5. K4 selects the X 0.01 setting on the multiplexer.
Dual low-leakage diode D5 prevents the amplifier input from swinging more than about +/-6 volts
when overdriven, to protect the amplifier input and following circuitry. 1F is a FET-input unity-gain
buffer, which provides a very high load impedance for the input attenuator and very low driving
impedance to the following amplifier stage. R31 and R32 provides offset adjustment for the input
stage.
Note that the relay coils and the amplifier power terminals are decoupled by RC on RC networks.
These networks protect the input circuitry from system noise and also prevent crosstalk between
the compoments.
DSP 1030 User's Manual August,1989 9

OUTPUT STAGE
Refer to Fig. 3, 1030 Output Stage Block Diagram. Signals from the input stage drive two parallel
attenuators. One attenuates by 0.5, and the second by 0.2. The multiplexer selects the 1-2-5
portion of the inverting input of the amplifier connects to gain switching and offset bias circuitry.
OUTPUT STAGE DETAILS
Refer to Sheet 3 of the 1030 Schematic Diagram. Only channel 1 will be described in detail; all
the other channels are identical. Signal from the input stage connects to two parallel attenuators.
The X 1 signal flow is from the buffer output thru RX2 and K2 to the amplifier's positive input. The
X.5 attenuator is made up of RX3 and R29. The X.2 attenuator uses the X.5 attenuator plus K3
and R27. R30 and C31 are high frequency compensation for the X.5 attenuator. The variable
capacitor C31 adjusts the peaking of the X.5 attenuator. The output of the 1-2-5 attenuator is
applied to the positive input of the amplifier. The programmable offset voltage is applied to the
inverting side of the amplifier. Also there is a gain switch for the X 10 range on the inverting input.
The amplifier has an internal 1K feedback resistor, which is connected by a trace between pins 4
and 11. Gain of the amplifier is set by this resistor and the parallel combination of the resistors
connected to the inverting input pin of the amplifier. R18, R19, R20 and R23 are the primary gain-
setting resistors. Relay K1 increases the amplifier gain for the X 10 gain setting only, and R19
provides overall adjustment for this gain setting. R18 adjusts overall amplifier gain for all other
settings. R24 sets the scale factor for the voltage from the offset D/A convertor. Since the offset
convertor is unipolar in nature, an offset current must be provided to make it bipolar; R25 and the
1V reference provide that offset current. R17 sets the output impedance of the amplifier channel.
Afine offset adjustment to compensate for the amplifier bias current error is formed by R81 and
R82. The error is unipolar and therefore so is the compensation.
DSP 1030 User's Manual August,1989 10

CAMAC DECODING LOGIC
Refer to Sheet 10 of the 1030 Schematic Diagram. There is an internal 8-bit read/write bus to
reduce wiring complexity. 7A provides a write path from the CAMAC dataway W lines to this bus,
and 8A serves a similar purpose for the CAMAC R lines. These ICs are controlled by 6A, which
also generates some CAMAC-originated signals that do not require strobing with S1. 8B generates
all signals that require the S1 strobe, as well as some other unstrobed CAMAC signals (such as
Xand Q). 1A stretches the S1 pulse to blink the N light, and 6B adds some extra channel
decoding. 9A and 6A generate the unit ID that is read by F(3) A(0). They drive the R lines
independently, because the ID is a 16-bit word. 6D-2 and 6D-4 provide open collector drive to the
CAMAC dataway for X and Q.
BATTERY BACKUP LOGIC AND CHANNEL CONTROL DECODING
Refer to Sheet 11 of the 1030 Schematic Diagram. Amplifier status except for offset control is
stored in a CMOS register for each channel. These registers are 2A-5A, for channels 1, 2, 3 and
4respectively. These ICs have a readback feature; i.e. when pin 1 is brought low, data in the
registers is presented on the D inputs without disturbing the register Q outputs. 7B prevents
operation of the clock inputs to the registers when the power is down. 7D prevents data strobing
of the offset D/A convertor (see sheet 13).
2B-5B are small PROMs that further decode the channel setup data contained in the battery
backup registers. 6D provides drive power for some of the control relay coils.
FRONT PANEL DISPLAY LOGIC
Refer to Sheet 12 of the 1030 Schematic Diagram. The front panel SELECT button is debounced
by 1B. Each time the button is pressed, the 2-bit counter formed by 1C increments one count. The
counter outputs go to the selection PAL 8B and also are decoded by 1D, which drives the LEDs
that indicate the selected channel. The channel status LEDs are driven directly from the 8-bit
read/write bus.
DSP 1030 User's Manual August,1989 11

POWER SUPPLY
Refer to Sheet 1 of the 1030 Schematic Diagram. D3 drops the 6 volts from the CAMAC connector
to near 5 volts, as does D4 for the -6 volts to near -5 volts. Lithium battery BT1 provides
powerdown voltage for the backup registers through D2, while D1 supplies the same registers when
power is on, saving battery power. 11A serves as a power fail detector and power on reset
generator. VR1 and VR2 provide +15 volts and -15 volts, respectively, to the input stage buffers
on the amplifiers.
REFERENCE VOLTAGES
Refer to Sheet 13 of the 1030 Schematic Diagram. Precision reference 11B is the master voltage
standard for the 1030. 11C derives from it a 1 volt reference, which is used both as a reference
for the D/A convertor and as unipolar/bipolar conversion offset for the amplifiers. The D/A convertor
8D is a quad CMOS device with internal latches that can be read back through its input data bus.
Its power terminal is connected to the backup battery voltage, thus preserving its settings when
power is off. 10B is a quad operational amplifier that that buffers the output of each D/A convertor
section, providing drive current for the amplifier offset inputs.
DSP 1030 User's Manual August,1989 12

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