Dynamic Engineering PCIe3IP User manual

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DYNAMIC ENGINEERING
150 DuBois, Suite C Santa Cruz, CA 95060
[phone] Fax [phone]
www.dyneng.com
[email protected]
Est. 1988
User Manual
PCIeIP Carrier Series
PCI Express x1 to
IP (Industry Pack) Bridge
Models in Group :
PCIe3IP [Released]
PCIe5IP [Released]
VPX2IP [Released]
VPX4IP [Coming soon]
Revision A1.3
December 2016
©2013-2016 by Dynamic Engineering.
Other trademarks and registered trademarks are owned by their respective manufacturers.

E m b e d d e d S o l u t i o n s P a g e 2 o f 71
PCIe3IP: PCI Express carrier with 3 IP positions.
Fab Number: 10-2014-0202/3 FLASH Rev 0x10
PCIe5IP: PCI Express carrier with 5 IP positions.
Fab Number: 10-2015-1601 FLASH Rev 0x10

E m b e d d e d S o l u t i o n s P a g e 3 o f 71
VPX2IP: PCI Express carrier with 2 IP positions.
Fab Number: 10-2016-1901 FLASH Rev 0x10

E m b e d d e d S o l u t i o n s P a g e 4 o f 71
PCIeIP Carrier Series
PCI Express x1 to
IP (Industry Pack) Bridge
Dynamic Engineering
150 DuBois St. Suite C, Santa Cruz CA 95060
831-457-8891 831-457-4793 FAX
This document contains information of proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the recipient, by accepting this material, agrees
that the subject matter will not be copied or reproduced, in whole or in part, nor its
contents revealed in any manner or to any person except to meet the purpose for which
it was delivered.
Dynamic Engineering has made every effort to ensure that this manual is accurate and
complete. Still, the company reserves the right to make improvements or changes in the
product described in this document at any time and without notice. Furthermore,
Dynamic Engineering assumes no liability arising out of the application or use of the
device described herein.
The electronic equipment described herein generates, uses, and can radiate radio
frequency energy. Operation of this equipment in a residential area is likely to cause
radio interference, in which case the user, at his own expense, will be required to take
whatever measures may be required to correct the interference.
Dynamic Engineering’s products are not authorized for use as critical components in life
support devices or systems without the express written approval of the president of
Dynamic Engineering.
This product has been designed to operate with IndustryPack Modules and compatible
user-provided equipment. Connection of incompatible hardware is likely to cause
serious damage.

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PRODUCT DESCRIPTION 9
THEORY OF OPERATION 16
PROGRAMMING 18
VPX2IP ADDRESS MAP 18
PCIE3IP ADDRESS MAP 19
PCIE5IP ADDRESS MAP 20
PCIEIP RESETS, CLOCKS, & BUS ERROR 22
IP CHANNEL TRANSFER ACTIVITY MONITOR AND LOGIC 26
PCIEIP INTERRUPTS 28
PCIEIP REGISTERS 37
LED DECODE TABLE 49
PCIEIP BOARD FEATURES 52
PCIeIP Carrier IP Logic Connector Pin Assignment 52
PCIeIP IP Carrier IO Connector to 50 Pin Header Assignment 53
VPX2IP IP Carrier Condo Header Connector Assignment –Option 1 53
VPX2IP IP Carrier Rear IO Connector Assignment –Option 2 54
PCIE3IP BOARD FEATURES 55
PCIe3IP DIP Switches 55
Table of Contents

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PCIe3IP LED’s 56
PCIe3IP IP1/IP2 connectivity option 57
PCIe3IP Board Revision 58
PCIE5IP BOARD FEATURES 59
PCIe5IP DIP Switches 59
PCIe5IP LED’s 60
PCIe5IP Board Revision 61
VPX2IP BOARD FEATURES 62
VPX2IP DIP Switches 62
VPX2IP LED’s 63
VPX2IP IP0/IP1 connectivity options 64
VPX2IP Board Revision 65
MECHANICAL 66
APPLICATIONS GUIDE 66
ELECTRICAL 66
AC/DC TIMING 66
INTERFACING 66
CONSTRUCTION AND RELIABILITY 67
THERMAL CONSIDERATIONS 67
WARRANTY AND REPAIR 68
Service Policy 68
Out of Warranty Repairs 68

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For Service Contact: 68
SPECIFICATIONS 69
ORDER INFORMATION 71

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Figure 1 PCIe3IP Block Diagram 14
Figure 2 PCIe3IP FPGA Block diagram 15
Figure 3 VPX2IP Base Address Map 18
Figure 4 PCIe3IP Base Address Map 19
Figure 5 PCIe5IP Base Address Map 20
Figure 6 PCIeIP Register Address Map 38
Figure 7 PCIeIP IP Logic Interface 52
Figure 8 PCIeIP IP I/O to 50 pin Header Connections 53
Figure 9 VPX2IP IP Carrier Rear IO Connector Assignment 54
Figure 10 PCIe3IP IP[2:0] I/O to 50 pin J[2:0] Header Diagram 57
Figure 11 VPX2IP IP[1:0] I/O to Condo Header or Rear IO (VPX) connector Diagram 64
List of Figures

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Product Description
The PCIeIP Carrier Series is part of Dynamic Engineering’s IP Compatible family of
modular I/O components. The PCIeIP Carrier Series uses a single PCI Express (PCIe)
slot or lane (VPX). Products in the PCIeIP Carrier Series covered by this manual
include:
1) PCIe3IP - A half-length card providing three IndustryPack Compatible sites.
2) PCIe5IP - A full-length card providing five IndustryPack Compatible sites.
3) VPX2IP - A 3U 4HP with bezel or rear IO card providing two IndustryPack
Compatible sites.
IndustryPack ID, IO, INT, and MEM access types are supported for read and write
cycles. The full 8 Mbytes of address space is allocated to each of the MEM spaces.
Low impedance Quick Switch devices provide a signaling bridge between the 3.3V
FPGA signaling and 5V IP signaling environments. A user switch setting can select the
IP bus to operate at 3.3V. Users can take advantage of the 3.3V signaling by removing
their level shifting devices. Module positions are independent for reference voltage
selection.
The PCI Express link is a by one (x1) link that is fully compliant to PCI Express 1.1
revision of the PCI-SIG specification and as such can operate in any compliant PCIe
Gen1, Gen2, Gen3, or Gen4 slot. Each IP position supports 8 & 16 bit IP devices and is
fully compliant to the Vita 4-1995 specification.
Each IndustryPack module position has a completely separate IP control bus
connection to the FPGA. Within the FPGA each of the IP control buses are separately
controlled. Packets received from the PCIe link are routed through steering logic to the
proper control bus interface. Within each control interface FIFOs are used to store
multiple packets. With this architecture multiple IndustryPack data transfers can be
queued for execution as the IP is ready. One advantage of this architecture is that a
slower IP does not hold up a faster IP from being serviced. Also a loop to load a FIFO
or fill RAM etc. can potentially be completely adsorbed by PCIeIP allowing the CPU to
move onto other tasks much faster.
Since some situations require deterministic execution and coordination between
installed IndustryPack modules, design features are provided to control the execution of
commands in a specific sequence between multiple IP modules. Since all instructions
are executed in order, this mode is not needed for single IP deterministic operation.

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Per the PCIe specification every access is at least a one long word. Byte, word, and
3byte accesses are supported utilizing PCIe byte enables. Any combination of byte
enables and starting address as defined by the PCIe specification is supported. The
PCIeIP supports PCIe transfer sizes of 1 and 2 long words (2Lwords = 1 quad word).
PCIe accesses are automatically converted into IP accesses and may range from a
single IP access up to 4 back-to-back IP accesses with the IP address incrementing
between cycles unless the address increment disable function is selected. For a read,
the IP read data is assembled, and a PCIe read completion packet is returned. The
Automatic generation of IP accesses greatly enhances the overall throughput when
transfers are > 2 bytes. Additionally, based on the PCIe byte enables the PCIeIP
determines when only a single 16 bit IP access needs to be performed for word or byte
transfers. In all cases the appropriate IP byte lane enables are applied as necessary.
Each IP clock is independently programmable for 8 or 32 MHz operation via a bit in its
control register. By default each IP CLK is 8MHz after power up and/or reset. The clock
frequency maybe changed at any time without consequence. Regardless of the
frequency of each clock, the IP clock outputs are designed to be “phase stepped” in
relation with one another to reduce simultaneous switching noise. For the PCIe3IP and
PCIe5IP the rising edge of IP1 clock is 8ns and IP2 clock is 16ns after the rising edge of
IP0’s clock. The PCIe5IP IP3/4’s clock is in phase with IP0/1’s clock. For the VPX2IP
the rising edge of IP1 clock is 8ns after the rising edge of IP0’s clock.
In normal operation IP access latency and performance is substantially better and the IP
logic runs 4 times faster when the IP CLK is 32MHz versus 8MHz.
PCIeIP has a programmable watchdog timer function, which completes the IP access if
the IP does not respond within the required amount of clock cycles. The watchdog timer
has a status bit and an optional Bus Error interrupt output.
PCIeIP supports interrupts from each IP slot with separate mask bits. Two interrupts
from each IP slot are supported. An interrupt force bit is available to aid in software
development in addition to the IP required 5V Power Good interrupt. All the interrupts
are maskable. The masked interrupt output signals are tied together and if asserted will
generate either MSI or INTA#.
PCIeIP has several programmable interrupt features to control when an interrupt is
generated. Programmable bits select behavior such as edge or level, or aggregation
timer values to pace the rate at which interrupts are generated (see Interrupt section for
details).

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VPX2IP/PCIe3IP/PCIe5IP has a total of 15/16/18 LED’s to indicate various status. 2/3/5
LED’s are used and light to indicate ACK* activity on each of the 2/3/5 IP channels. 5
LED’s are used with 5 independent voltage monitoring circuits to accurately detect if any
of the board’s voltages are out of range. One LED for each power monitoring circuit,
when the LED is on the voltage is in range, if the LED is off the voltage is out of range.
Eight (8) user controllable LED's are supplied. Each LED is programmable with one of
sixteen possible sources to provide a variety of status. The 4bit LED select field in the
Switch and LED control register is used to determine each LED’s meaning.One of the
selections allows the user to directly control the LED’s. The default selection uses 4
LED’s to reflect PCIe link status, when all four of the lower four LED’s are on they
indicate a working link.
Two 8 bit "dip switches" are provided on the PCIeIP. One 8 bit dip switch is for user
configuration and is readable via the Switch and LED control register. The other 8 bit dip
switch is for board configuration and test purposes (see Board Features section for
details).
Power-on PCIe PERST# reset is used to reset the entire PCIeIP. Each IP Reset* is
asserted as long as PERST# is asserted. Once PERST# is de-asserted each IP’s clock
starts toggling, and each IP Reset* will remain asserted until a 256ms timer expires.
Once the timer expires IP Reset* de-asserts synchronously with that IP’s CLK. Two
separate control register reset bits are provided for each IP. One only asserts IP Reset*,
and one asserts IP Reset* and resets that PCIeIP’s IP channel/FIFO.
To meet the PCI Express specification requirement for PCIe core initialization within
100mS from PERST# de-assertion; PCIeIP implements a 16 bit wide 90ns Flash in
conjunction with a CPLD to configure the FPGA via its parallel configuration port. With
this architecture, PCIeIP beats this aggressive specification by a comfortable margin.
For the PCIe3IP/PCIe5IP the IO’s for each IP are brought out to their own 50 pin
headers. For the VPX2IP, stuffing options route the IO to either the Condo header or the
VPX rear connector. All IO signals for each PCIeIP board are routed carefully with
matched length and impedance control. Differential routing techniques are used to
support operation with LVDS, RS485 and other differential electrical standards as well
as single ended systems –analog, TTL IO etc. Please see the pin-out tables later in
this manual for the mapping of IP IO to header.
For the PCIe3IP/PCIe5IP the 50 pin header in the first position is mounted [right angle
header] to be accessible through the bezel. The second, third, (PCIe3IP) fourth and
fifth positions (PCIe5IP) have traditional vertical headers.

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The bezel for the PCIe3IP is a special design with accommodation for the right angle
header and cable routing for the other two. All of the IO can come through the bezel
without wasting another IO position. The bezel incorporates an arm with hinge to allow
the side of the bezel to be rotated out of the way to aide in threading the rear IO through
the bezel. Install the IO into the rear headers, lift the bezel arm, place the cabling onto
the bezel, rotate the arm back into position, and mount into the system.
PCIeIP conforms to the VITA standard for IndustryPack Carriers. This guarantees
compatibility with multiple IndustryPack compatible modules.
Dynamic Engineering provides Windows, Linux and VxWorks drivers for the PCIeIP.
The drivers detect the carrier card and communicate with the OS to get the memory,
interrupts etc. assigned to the installed carrier. The driver interrogates the IP positions
on the carrier and when an IP is located determines if a corresponding driver is
installed. If not the IP-Generic driver is installed to allow any third party IP module to
be used with the carrier. When a recognized module is detected the driver for that
module is installed automatically.

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Feature List Summary
• 2/3/5 IP compatible slots VPX2IP/PCIe3IP/PCIe5IP
• 8 or 32 MHz operation in each slot independently programmable
• IP CLK phase stepper –reduces simultaneous switching noise
• PCI Express Gen1, Gen2, Gen3, or Gen4 slot operable and compliant
• Non-blocking IP FIFO architecture - prevents IP versus IP packet congestion
• MSI and INTA# Interrupt support
• Programmable Interrupt pacing/aggregation with edge or level detection
• IP Channel Activity Monitors - ACK* Counters & Logic enable sequenced IP transfers
• byte, word, long word, and quad word transfer capable
• Incrementing or static address access of each IP slot
• Programmable IP Word and/or Byte Swapping
• Programmable Bus error abort response times
• 5 independent voltage monitoring circuits –to detect if a board voltage is out of range
• 1:1 50 pin headers with matched 5 mill trace & spacing widths between IO and header
• IP1/IP2 I/O SMT to 50 pin headers trace configuration/stuffing options - PCIe3IP only
• Configurable IO routing to Condo header or VPX Rear IO connector –VPX2IP only
• Individual IP resets with options for IP only or IP and local control
• Two 8 position "DIP Switches” – one for users, one for configuration and test
• Configurable IP Bus Termination –select 5.0V or 3.3V termination via CFG switches
•8 User LED's, 5 Power good indicator LED's, an ACK* activity LED for each IP
• Fused Filtered Power with resettable fuses for each position
• Windows, Linux & VxWorks drivers
As Dynamic Engineering adds features to the hardware we will update the PCIeIP page
on the Dynamic Engineering website. If you want some of the new features, and have
already purchased hardware, you can download the Flash update and use the tools
provided to update the Flash via the JTAG port. Or you may send the board back and
Dynamic Engineering will update the Flash. A nominal fee is required for this service.
The basic PCIe identifying information will not change with the updates, including the
PCIe Revision ID field which is set to 0x01. To allow configuration control a Version ID
register is provided at offset 0x01C to indicate the current code revision of both the
FPGA and CPLD. Each devices revision ID has a major and minor field. The major
field is updated with new client releases. The minor is used internally for development
purposes and in some cases with specialized client releases. Our drivers make the
revision information available as part of the board info.
If your project can benefit from a "non-standard" implementation, or features that we
have not thought of, or implemented yet please let us know. For example, if your project
has IP's that can operate at 64 MHz instead of 32 MHz Dynamic Engineering could
modify the design the meet 64MHz timing.

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The PCIeIP Architecture is the foundation for all the devices in the PCIeIP Carrier
Series. The PCIe3IP Block Diagram (Figure 1) and PCIe3IP FPGA Block Diagram
(Figure 2) illustrate a 3IP channel design using the PCIeIP Architecture. To create the
PCIe5IP two additional IP channels (IP3 & IP4 –not shown) are implemented. To create
the VPX2IP the IP2 channel is removed.
PCIe3IP Block Diagram
Power Circuits
Monitors & Power in range LEDs
P12V
CPLD Parallel
FPGA Loader
PERp/n0
16 bit –90ns
FLASH
JTAG
Header
32MHz
OSC
PETp/n0
Lattice ECP3 FPGA
CFG & TEST
P5VGOOD
Parallel CFG & Data
USER DIP Switch Inputs
TDO
PCIe REFCLK +/-
M12V P5V
3.3V 1.2V
CFG & TEST
DIP Switch
USER
DIP Switch
USER LED [7:0]
x1
PCI
Express
Edge
Fingers
Connector
TDI
TDI
TDO
Lattice ECP3 FPGA
PCI
Express
Core
PERST#
IP0
Interface
IP0
IP0 ACK* Activity LED
``
Carrier
IP0 Logic
Connector
SMT
3.3V –5V
Level
Shifter
``
HDR_50
IP0
RT Angle
Header
With
Ejectors
IP0
Carrier
IO
Connector
SMT
IP1
Interface
IP1
IP1 ACK* Activity LED
``
Carrier
IP1 Logic
Connector
SMT
3.3V –5V
Level
Shifter
``
HDR_50
IP1
Vertical
Header
IP1
Carrier
IO
Connector
SMT
IP2
Interface
IP2
IP2 ACK* Activity LED
``
Carrier
IP2 Logic
Connector
SMT
3.3V –5V
Level
Shifter
``
HDR_50
IP2
Vertical
Header
IP2
Carrier
IO
Connector
SMT
Figure 1 PCIe3IP Block Diagram

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PCIe3IP FPGA Block Diagram
PERp/n0
PETp/n0
REFCLK +/-
Credits
Available
Unsupported
Request
Packet Generator
Credits
Processed
Receive
FIFO
&
Packet
Router
PCI Express
Core
PERST#
TX Arbiter
& Packet
Transmitter
Credit
processor
IP1 Rx Packet
IP2 Rx P acket
Un-support Request
Un-support Request
Rx Packet
Interface
IP1 Channel
IP2 Channel
Read/Write
Packet
Processor
Receive
Packet
FIFO
READ
Completion
Packet
Generator
Transmit
Packet
FIFO
IP0 Channel
IP
Data Path
State
Machines
&
Logic
Register Rx Packet
IP0 Rx P acket
Tx Packet
Interface
Tx RDY
Read/Write
Packet
Processor
Receive
Packet
FIFO
READ
Completion
Packet
Generator
Transmit
Packet
FIFO
Register Channel
PICe3IP
Registers
IP1 Rx P acket
IP0 Rx P acket
IP2 Rx P acket
IP1 Tx Packet
IP2 Tx Packet
IP0 Tx Packet
Register Tx Packet
Register Tx Packet
Un-support Request Tx Packet
Register Credit
IP0/IP1/IP2 Credits
UR Credit
UR Credit
IP2
IP1
IP0
IP Interfaces
Figure 2 PCIe3IP FPGA Block diagram

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Theory of Operation
PCIeIP functions as a bridge between PCI Express and IP bus devices that adhere to
their respective specifications. Since there are no additional PCIe virtual buses or PCIe
ports downstream from the PCIeIP’s PCI Express port, the PCIeIP is defined to be a
PCIe Endpoint. As an Endpoint the PCIeIP is downstream from the Host/Root Complex
which detects it and configures it during the enumeration process using PCIe
configuration read and write packets. The VPX2IP/PCIe3IP requests a total of 32MB
and the PCIe5IP requests 64MB from the Host who provides the requested memory
space via BAR0. Each IP's ID, IO, INT, and MEM spaces are mapped inside the
32/64MB space. When the PCIe Host transmits either a memory read or write packet
which contains an address within the PCIeIP’s BAR0 it is routed to either the PCIeIP
register block, or one of the IP’s to be further decoded to generate an ID, IO, INT, or
MEM space IP access.
The VPX2IP/PCIe3IP/PCIe5IP handles all accesses within its 32/64 MB of space.
Writes to reserved registers or memory are dropped. For reserved register reads,
0x0000_0000 is returned. For reads of undefined memory spaces, 0xFFFF_FFFF is
returned. In all cases credits are updated.
If a packet is received with an address outside the PCIeIP’s BAR0 space it is discarded,
credits are updated, and an unsupported request PCIe packet is returned to complete
the transaction.
PCIeIP uses a Lattice semiconductor ECP3 Family FPGA and utilizes Lattice’s PCI
Express Endpoint Core IP which is compliant to PCI-SIG PCI Express 1.1 Base
Specifications. The core handles the PCIe Physical and Data Link Layer requirements
and provides an extensive interface which the PCIeIP interacts with to receive or
transmit Transaction Layer Packets (TLPs) and communicate and/or update available
flow control credits.
All Transaction Layer Packets coming from the PCIe Core that are within BAR0 space
are written into a receive packet FIFO. Upon detecting a packet is in the receive FIFO it
is immediately read out, routed and written into the target IP’s or registers receive FIFO.
The FIFO’s are sized and PCIeIP advertises credits such that no access packet has to
wait behind a different IP channels access packet, as such this creates a Non-blocking
IP FIFO architecture. However, since the IP interfaces run much slower than the rate at
which incoming receive FIFO Packets can be received, packets can back up inside a
particular IP’s receive FIFO, but will never backup into the main receive FIFO.

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For example if 100 reads are in one IP’s receive FIFO and a new read is received for a
different IP, it will be routed into that IP’s receive FIFO.
The header credits are set to the maximum allowed by the PCIe core, which is 127, so
up to 127 combined IP read and write requests may be pending at any one time inside
the PCIeIP.
Once a register or IP access has completed processing a write or read, the appropriate
credit updates will be accumulated and sent to the core which will create Flow Control
DLL packet(s) to inform/update the Host that more space/credit is available inside the
PCIeIP. For the VPX2IP/PCIe3IP/PCIe5IP there are three/four/six possible read targets
and/or sources for read completion packets, they are: IP[1:0]/IP[2:0]/IP[4:0], and a
register access. When the read target has assembled the read completion packet it
stores it in its transmit FIFO as it must arbitrate for and then write the completion into
the transmit packet port of the PCIe core. The transmit packet arbiter is a round robin
arbiter. The transmit packet port won’t grant access until the core informs it is ready to
receive a packet.

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Programming
PCIeIP is tested in a Windows environment. We use the Dynamic Engineering Driver to
do the low level accesses to the hardware. We use MS Visual C++ in conjunction with
the driver to write our test software. Please consider purchasing the engineering kit for
the VPX2IP, PCIe3IP or PCIe5IP; the software kit includes our test suite. In addition
Linux and VxWorks drivers and reference suites are available.
The drivers take care of discovery and the UserAp allows the client to select which
installed board is selected for use.
If you are writing your own driver it is suggested to get the engineering kit and the Linux
version of the SW. Usually the code defines and perhaps some of the code can be
reused in your effort.
VPX2IP Address Map
Function
Offset
Size
Registers –IP[2:0]
0x000 –0x3FF
1K Bytes
ID Space –IP0
0x400 to 0x47F
128 Bytes
ID Space –IP1
0x480 to 0x4FF
128 Bytes
Reserved
0x500 to 0x7FF
768 Bytes
IO Space –IP0
0x800 to 0x87F
128 Bytes
IO Space –IP1
0x880 to 0x8FF
128 Bytes
Reserved
0x900 to 0xBFF
768 Bytes
INT Space –IP0
0xC00 to 0xC7F
128 Bytes
INT Space –IP1
0xC80 to 0xCFF
128 Bytes
Reserved
0xD00 to 0xFFF
768 Bytes
Reserved
0x1000 to 0x7F_FFFF
8 MB-4KB
MEM Space –IP0
0x080_0000 to 0x0FF_FFFF
8 MB
MEM Space –IP1
0x100_0000 to 0x17F_FFFF
8 MB
Reserved
0x180_0000 to 0x1FF_FFFF
8 MB
Figure 3 VPX2IP Base Address Map

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PCIe3IP Address Map
Function
Offset
Size
Registers –IP[2:0]
0x000 –0x3FF
1K Bytes
ID Space –IP0
0x400 to 0x47F
128 Bytes
ID Space –IP1
0x480 to 0x4FF
128 Bytes
ID Space –IP2
0x500 to 0x57F
128 Bytes
Reserved
0x580 to 0x7FF
640 Bytes
IO Space –IP0
0x800 to 0x87F
128 Bytes
IO Space –IP1
0x880 to 0x8FF
128 Bytes
IO Space –IP2
0x900 to 0x97F
128 Bytes
Reserved
0x980 to 0xBFF
640 Bytes
INT Space –IP0
0xC00 to 0xC7F
128 Bytes
INT Space –IP1
0xC80 to 0xCFF
128 Bytes
INT Space –IP2
0xD00 to 0xD7F
128 Bytes
Reserved
0xD80 to 0xFFF
640 Bytes
Reserved
0x1000 to 0x7F_FFFF
8 MB-4KB
MEM Space –IP0
0x080_0000 to 0x0FF_FFFF
8 MB
MEM Space –IP1
0x100_0000 to 0x17F_FFFF
8 MB
MEM Space –IP2
0x180_0000 to 0x1FF_FFFF
8 MB
Figure 4 PCIe3IP Base Address Map

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PCIe5IP Address Map
Function
Offset
Size
Registers –IP[2:0]
0x000 –0x3FF
1K Bytes
ID Space –IP0
0x400 to 0x47F
128 Bytes
ID Space –IP1
0x480 to 0x4FF
128 Bytes
ID Space –IP2
0x500 to 0x57F
128 Bytes
ID Space –IP3
0x580 to 0x5FF
128 Bytes
ID Space –IP4
0x600 to 0x67F
128 Bytes
Reserved
0x680 to 0x7FF
384 Bytes
IO Space –IP0
0x800 to 0x87F
128 Bytes
IO Space –IP1
0x880 to 0x8FF
128 Bytes
IO Space –IP2
0x900 to 0x97F
128 Bytes
IO Space –IP3
0x980 to 0x9FF
128 Bytes
IO Space –IP4
0xA00 to 0xA7F
128 Bytes
Reserved
0xA80 to 0xBFF
384 Bytes
INT Space –IP0
0xC00 to 0xC7F
128 Bytes
INT Space –IP1
0xC80 to 0xCFF
128 Bytes
INT Space –IP2
0xD00 to 0xD7F
128 Bytes
INT Space –IP3
0xD80 to 0xDFF
128 Bytes
INT Space –IP4
0xE00 to 0xE7F
128 Bytes
Reserved
0xE80 to 0xFFF
384 Bytes
Reserved
0x1000 to 0x7F_FFFF
8 MB-4KB
MEM Space –IP0
0x080_0000 to 0x0FF_FFFF
8 MB
MEM Space –IP1
0x100_0000 to 0x17F_FFFF
8 MB
MEM Space –IP2
0x180_0000 to 0x1FF_FFFF
8 MB
MEM Space –IP3
0x200_0000 to 0x27F_FFFF
8 MB
MEM Space –IP4
0x280_0000 to 0x2FF_FFFF
8 MB
Reserved
0x300_0000 to 0x3FF_FFFF
16 MB
Figure 5 PCIe5IP Base Address Map