Dynatem CPU-111-10 User manual

USER MANUAL
CPU-111-10 (VPQ)
Intel Xeon Quad-Core 6U VPX
Single Board Computer
CPU-111-10_User_Manual_d0.1.doc Updated 25mar2013

CPU-111-10 User’s Manual Rev. Draft 0.1
March 25, 2013
Dynatem
23263 Madero, Suite C
Mission Viejo, CA 92691
Phone: [phone]
Fax: [phone]
www.dynatem.com

Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual i
Table of Contents
1. FEATURES ......................................................................................................................................................... 1
2. RELATED DOCUMENTS ..................................................................................................................................... 3
2.1 Standards.............................................................................................................................................. 3
2.2 Product Specifications, Component Data Sheets, and Design Guides ..................................................... 3
3. HARDWARE DESCRIPTION................................................................................................................................ 4
3.1 OVERVIEW AND SPECIFICATIONS ....................................................................................................................... 4
3.2 PROCESSING ARCHITECTURE ............................................................................................................................. 6
3.2.1 Processor........................................................................................................................................... 6
3.2.2 Memory Controller Hub and DDR2 SDRAM ........................................................................................ 6
3.2.3 I/O Controller Hub ............................................................................................................................. 6
3.3 PCI EXPRESS ARCHITECTURE ............................................................................................................................ 8
3.3.1 Dual XMC Sites .................................................................................................................................. 8
3.3.2 PLX PEX8624 PCIe Switch ................................................................................................................... 8
3.3.2 IDT Tsi384 PCIe to PCI-X Bridges for PMC Support.............................................................................. 9
3.3.3 Intel 82599 Dual 10Gb Ethernet Controller ........................................................................................ 9
3.3.4 Intel 82571 Dual 1Gb Ethernet Controller .......................................................................................... 9
3.3.5 Silicon Motion SM750 Graphics Controller ......................................................................................... 9
3.4 10 GIGABIT ETHERNET ARCHITECTURE ............................................................................................................. 10
3.4.1 Fulcrum FM3224 Switch .................................................................................................................. 10
3.4.2 Intel 82599 Dual 10GB Ethernet....................................................................................................... 11
3.4.3 SFP+ Interface (AEL2009)................................................................................................................. 12
3.4.4 VPX 10Gb Ethernet I/O .................................................................................................................... 12
3.4.5 XMC 10GbE I/O................................................................................................................................ 13
3.5 VPX GENERAL PURPOSE I/O.......................................................................................................................... 13
3.6 CLOCKING .................................................................................................................................................. 13
3.7 RESET STRUCTURE ....................................................................................................................................... 14
3.8 SMBUS ARCHITECTURE................................................................................................................................. 15
3.9 BOARD POWER ........................................................................................................................................... 16
3.10 REAR TRANSITION MODULE ....................................................................................................................... 17
4. INSTALLATION................................................................................................................................................ 18
4.1 SELECTABLE OPTIONS ................................................................................................................................... 18
4.2 PCI MEZZANINE CARD (PMC) INSTALLATION .................................................................................................... 20
4.3 FRONT PANEL CONNECTORS AND RESET SWITCH ................................................................................................ 20
A. CONNECTOR PIN-OUTS .................................................................................................................................. 21
A.1 VPX BACKPLANE CONNECTORS....................................................................................................................... 21
A.2 PCI-X MEZZANINE CARD CONNECTORS ............................................................................................................ 24
A.3 XMC CONNECTORS ...................................................................................................................................... 25
A.4 SFP+ PIN-OUT ............................................................................................................................................ 25
A.5 FRONT PANEL USB PIN-OUT .......................................................................................................................... 26
B. BIOS & SETUP *** NEED INPUT FROM HUNG ***.................................................................................... 27
B.1 REDIRECTING TO A SERIAL PORT ...................................................................................................................... 27
B.2 SETUP MENUS ............................................................................................................................................ 28
B.3 NAVIGATING SETUP MENUS AND FIELDS ........................................................................................................... 28

Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual ii
B.4 MAIN SETUP MENU ..................................................................................................................................... 29
B.5 EXIT SETUP MENU ....................................................................................................................................... 30
B.6 BOOT SETUP MENU ..................................................................................................................................... 31
B.7 POST SETUP MENU..................................................................................................................................... 33
B.8 PNPSETUP MENU....................................................................................................................................... 36
B.9 SUPER I/O (SIO) SETUP MENU ...................................................................................................................... 37
B.10 FEATURES SETUP MENU............................................................................................................................ 38
B.11 FIRMBASE SETUP MENU............................................................................................................................ 39
B.12 MISCELLANEOUS SETUP MENU ................................................................................................................... 41
C. POWER AND ENVIRONMENTAL REQUIREMENTS........................................................................................... 43
D. RTM REAR PLUG-IN I/O EXPANSION MODULE FOR THE CPU-111-10 ............................................................. 44
D.1 RTM VPX PIN-OUTS.................................................................................................................................... 44
D.2 CPU-111-10 REAR TRANSITION MODULE PIN-OUTS .......................................................................................... 46
D.3 REAR PANEL CONNECTOR PIN-OUTS ................................................................................................................ 46

Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual iii
List of Figures
FIGURE 1: CPU-111-10 BLOCK DIAGRAM 4
FIGURE 2: PCI EXPRESS STRUCTURE 8
FIGURE 3: 10GB ETHERNET ARCHITECTURE 10
FIGURE 4: 10GB SWITCH BLOCK DIAGRAM 11
FIGURE 5: 82599 BLOCK DIAGRAM 11
FIGURE 6: VPX 10GBE I/O 12
FIGURE 7: CLOCKS 13
FIGURE 8: RESET STRUCTURE 14
FIGURE 9: SMBUS ARCHITECTURE 15
FIGURE 10: POWER GENERATION & DISTRIBUTION 16
FIGURE 11: REAR TRANSITION MODULE 17
FIGURE 12: CPU-111-10 CONNECTORS AND HEADERS 19
FIGURE 13: FRONT PANEL CONNECTORS AND INDICATORS 20
List of Tables
TABLE 1: VPX P0 CONNECTOR PIN-OUTS 21
TABLE 2: VPX P1 CONNECTOR PIN-OUTS 21
TABLE 3: VPX P2 CONNECTOR PIN-OUTS 22
TABLE 4: VPX P3 CONNECTOR PIN-OUTS 22
TABLE 5: VPX P4 CONNECTOR PIN-OUTS 23
TABLE 6: VPX P5 CONNECTOR PIN-OUTS 23
TABLE 7: VPX P6 CONNECTOR PIN-OUTS 24
TABLE 8: PCI-X MEZZANINE CARD CONNECTOR PIN-OUTS 24
TABLE 9: XMC CONNECTOR PIN-OUTS 25
TABLE 10: SFP+ CONNECTOR PIN-OUTS 25
TABLE 11: USB CONNECTOR PIN-OUT 26
TABLE 12: ENVIRONMENTAL REQUIREMENTS 43
TABLE 13: POWER REQUIREMENTS 43
TABLE 14: RTM VPX RP0 PIN-OUTS 44
TABLE 15: RTM VPX RP4 PIN-OUTS 44
TABLE 16: RTM VPX RP3 PIN-OUTS 45
TABLE 17: RTM VPX RP6 PIN-OUTS 45
TABLE 18: PMC I/O HEADER PIN-OUTS 46
TABLE 19: RTM REAR PANEL CONNECTOR PIN-OUTS 46

Chapter 1 –Features
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 1
1. Features
The CPU-111-10 is a rugged, high-performance 6U VPX (VITA 46) Single Board Computer (SBC) featuring a
quad-core Intel L5408 Xeon processor and integrated 10 Gigabit Ethernet switch to support full-mesh backplane data
layer interconnectivity for up to eight SBCs integrated into a single chassis. Available in air cooled or conduction
cooled formats, the CPU-111-10 conforms to the OpenVPX (VITA 65) payload module profile MOD6-PAY-4F2T-
12.2.2.4 with four fat pipes (10 GBase-BX4) and two thin pipes (1000Base-T).
Providing unparalleled data processing capabilities in a single-slot 6U VPX form factor card with built-in 10 Gigabit
Ethernet fabric switching, the CPU-111-10 serves as an ideal open-architecture building-block for next-generation
Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR)
applications onboard (un)manned air / ground vehicles and shipboard platforms. Standard onboard I/O resources
includes up to 8x 10 Gigabit Ethernet, 2x 1 Gigabit Ethernet, 4x SATA, 2x USB 2.0, 1x RS-232/485, and 1x VGA
video ports. Dual XMC / PMC expansion module sites enable additional I/O expansion, including 10G XAUI lanes
from each XMC card to the 10G switched fabric.
Features of the CPU-111-10 include:
OPENVPX COMPATIBLE:
Rugged Single-Slot 6U Single Board Computer compatible with VITA 65 OpenVPX Payload Module Profile
MOD6-PAY-4F2T-12.2.2.4 (4x 10GBase-BX4 Fat Pipes and 2x 1000Base-T Thin Pipes)
HIGH PERFORMANCE x86 CPU:
4-Core Intel Xeon L5408 Processor @ 2.13 GHz with 4GB of DDR2 RAM
Linux, VxWorks, Windows, LynxOS, QNX, x86 RTOS Compatible
16 GB Bootable Solid State Flash Disk
10 GIGABIT SWITCH:
Integrated 10 Gigabit Ethernet Packet Processor Provides Full-Mesh Data Layer Switch Fabric for Up to 8 SBCs
without Use of Additional Switch Board (7 XAUI Ports to VPX Backplane, 1 SPF+ Port)
10 Gigabit XAUI Fabric Interfaces to Dual XMC Expansion Modules
Front Panel SFP+ 10 Gigabit Port Supporting CX4 Copper and Fiber Applications for Chassis-to-Chassis and
Rack-to-Rack Communications
I/O & EXPANSION:
Network: Up to 8x 10 Gigabit Ethernet, 2x 1 Gigabit Ethernet
Peripherals: 4x SATA, 2x USB 2.0, 1x RS-232/485, and 1x VGA Video
Dual XMC / PMC Mezzanine Expansion Sites
RUGGED DESIGN:
Designed to Meet MIL-STD-810 Environmental Conditions (Thermal, Shock, Vibration, Humidity, Altitude) and
Stresses of VPX Chassis Injection/Ejection
Air and Conduction Cooled Variants; Conductively Cooled Version Integrate Board Stiffeners and Wedge Locks
for High Shock and Vibration Immunity/Efficient Thermal Transfer.

Chapter 2 –Related Documents
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 3
2. Related Documents
Listed below are documents that describe applicable standards, the processor and chipset, and the peripheral
components used on the CPU-111-10. Either download from the Internet or contact your local distributor for copies
of these documents. Many of the documents are confidential and may require execution of a non-disclosure
agreement between the supplier and CPU-110-10 user.
2.1 Standards
VITA 20-2001 - Conduction Cooled PMC, R1.1, February 2005
VITA 32-2003 - Processor PMC, R1.0, July 2003
VITA 42.0-2005 - XMC Switched Mezzanine Card Baseline Standard, D0.29, September 2005
VITA 42.3-2006 - XMC PCI Express Protocol Layer Standard, R1.0, June 2006
VITA 42.6-200x - XMC 10 Gigabit Ethernet 4-Lane Protocol Layer Standard, R0.911, January 2009
VITA 46.0-2007 - VPX Baseline Standard, R1.2, April 2008
VITA 46.4-2008 - PCI Express on VPX Fabric Connector, R6.00, March 2008
VITA 46.7-2008 - Ethernet on VPX Fabric Connector, R0.05, October 2008
VITA 46.9-2005 - PMC/XMC Pinout Mapping, R0.1, May 2005
VITA 46.21-2009 - Distributed Switching on VPX, R0.01, February 2009
IEEE P1386 - Common Mezzanine Card Family (CMC), D2.4a, March 2001
IEEE P1386.1 - CMC Physical and Environmental Layers, D2.4, January 2001
JEDEC 4.20.10 - PC2-6400/5300/4200/3200 Registered DIMM Design Specification, R3.98, January 2009
2.2 Product Specifications, Component Data Sheets, and Design Guides
CPU-111-10 Data Sheet, October 3, 2011
CPU-111-10 Schematic Diagram, R0.1, June 2009
CPU-111-10 Bill of Materials, R0.1, June 2009
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet, Doc. No. 318589-005, August 2008
Quad-Core Intel® Xeon® Processor L5408 Series in Embedded Applications Thermal/Mechanical Design Guidelines, Doc.
No. 319133-001, April 2008
Intel® 5100 Memory Controller Hub Chipset Datasheet, Doc. No. 318378-003U, July 2008
Intel® 5100 Memory Controller Hub Chipset for Communications, Embedded, and Storage Applications
Thermal/Mechanical Design Guide, Doc. No. 318676-003US, July 2008
Intel® Xeon® Processor 5000 Sequence with Intel® 5100 Memory Controller Hub Chipset for Communications,
Embedded, and Storage Applications Platform Design Guide, Doc. No. 352108-2.3, April 2009
Intel® I/O Controller Hub 9 (ICH9) Family Datasheet, Doc. No. 316972-004, August 2008
Debug Port Design Guide for UP/DP Systems, Doc. No. 313373-001, June 2006
Intel® 82599 10 Gigabit Ethernet Controller Datasheet, R0.6, October 2008
Intel® 82571 & 82572 Gigabit Ethernet Controller Datasheet, R2.0, December 2006
82571EB/82572EI Gigabit Ethernet Controller Design Guide, Doc. No. 315337-002, February 2008
Micron MT47H256M8 DDR2 SDRAM Data Sheet, Doc. No. 09005aef824f87b6, Rev. B, September 2008
PLX Technology ExpressLane PEX 8624-AA 24-Lane/6-Port PCI Express Gen 2 Switch Data Book, Version 0.80,
November 2007
Tundra Tsi384 PCIe-to-PCI/X Bridge User Manual, Doc. No. 80E1000_MA001_08, July 2008
Tundra Tsi384 Board Design Guidelines, Doc. No. 80E1000_AN004_04, July 2008
Fulcrum Microsystems FocalPoint FM4000 24-Port 10G Ethernet Switch Datasheet, R2.1, May 2009
Fulcrum Microsystems FocalPoint FM4212/FM3212 12-Port 10G Ethernet Switch Datasheet Addendum, R1.1, March 2008
Netlogic Puma AEL2005 10Gbps SFP+ Transceiver Data Sheet, R1.2, December 2007
Silicon Motion SM750 LynxExpress Mobile Multimedia Companion Chip Data Sheet, R0.1, June 12, 2009
Silicon Motion SM2240 Serial ATA to IDE Bridge Data Sheet, R0.3, November 26, 2008
Silego SLG505YC264B Clock Synthesizer Data Sheet, Doc. No. 000-0084505B-10, R1.0, April 2008
IDT ICS9DB403D Quad Differential Clock Buffer Data Sheet, Rev. J, February 2009
Intersil ISL6313B Two-Phase Buck PWM DCDC Controller Data Sheet, Doc. No. FN6809.0, November 2008
Linear Technology LTM4616 Dual 8A Low-Vin DC/DC Module Data Sheet, Doc. No. LT 1108, Rev. A, 2008
Lattice Semiconductor ispPAC-POWR1220AT8 Power Supply Monitor/Sequencer/Controller Data Sheet, Doc. No.
DS1015, June 2008

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 4
3. Hardware Description
3.1 Overview and Specifications
The block diagram of the CPU-111-10 is shown below. The sections that follow describe the major functional blocks
of the CPU-111-10.
SATA x1
Intel
L5408
Quad-Core
Xeon
Processor
Intel
5100
MCH
2GB
DDR2
SDRAM
2GB
DDR2
SDRAM
DDR2 - 1066 DDR2 - 1066
1066/1333MHz
FSB
Intel
ICH9R
ESI
PCIe x8
SATA x4
USB 2.0 x2
16Mbit
FWH
RS232/RS485 Console
IDP-XDP
ispPOWR
1220A
Power Monitor
and
Sequencer
CK505
Clock
Generator
PCIe x8 PCIe x8
16Mbit
SPI SPI Bus
Link Port “A” Link Port “B”
Link Port “C”
XMC
J15
XMC
J25
PLX
PEX8624
Gen2
6-Port
PCIe
Switch
Tsi384
PCIe-PCIX
Bridge
PCIe x4 PCIe x4 Tsi384
PCIe-PCIX
Bridge
PMC
J11-J13
PCI-X PCI-X PMC
J21-J23
Link Port “D”
Link Port “E”
64-Bit/133MHz 64-Bit/133MHz
Fulcrum Micro
FM3224
24-Port
10GigE
Switch
PMC
J14
PMC
J24 Single Ended x64
Single Ended x64
Differential Signaling x12
Link Port “F”
VPX
P4
VPX
P3
VPX
P6
VPX
P1
FABRIC
VITA46.21
(Legacy PCI/PCI-X)
VPX I/O
2GB/Sec
2GB/Sec
4GB/Sec
4GB/Sec
8GB/Sec
(Legacy PCI/PCI-X)
Link Port “G” MDI x2
4GB/Sec
300MB/Sec x4
1.06GB/Sec 1.06GB/Sec
8.5GB/Sec
5.3GB/Sec 5.3GB/Sec
2GB/Sec
2.5MB/Sec
60MB/Sec x4
XAUI[6]
Intel 82599EB
Dual 10GigE
(Niantic)
XAUI[9]
XAUI[10]
10GigE x2 XAUI[0]
XAUI[8] 10GigE x1
1GigE x2
Dual PMC/XMC Sites
2GB/Sec
SFP+
FRONT PANEL
COPPER/FIBER
INTERFACE
1.25GB/Sec x2
125MB/Sec x2
1.25GB/Sec x1
10GigE x1
1.25GB/Sec x1
XAUI[11]SFI
Gen2 PCIe x8
P[0:5] P[0:4]
STN[0] P[0]
STN[1] P[5] STN[2] P[9] STN[2] P[8]
PE6 PE7 PE4 PE5
PE2 PE3 PE0
P[0]P[1]
P[19] P[13]
P[7]
P[20] P[14] XAUI[1]
XAUI[2] XAUI[3] 10GigE x4 1.25GB/Sec x4
P[12]
P[8] P[4]
P[23]
RX[0:3]/TX[0:3]
125MB/Sec x2
1GigE x2
SMBus
MDIO
XMC
J16
XMC
J26
XAUI[4]
P[11]
10GigE x4 1.25GB/Sec x4
Intel
82571EB
Dual 1GigE 1000BASE-KX x2
Serial
EEP
Netlogic
AEL2005
XAUI to SFI
PHY
LPC BUS
CP2103 USB
To UART Cntlr
60MB/Sec
P[5] USB 2.0 x1
SM2240
SATA to Flash
Controller FLASH BUS
20MB/Sec
300MB/Sec x1
Differential Signaling x12
3.125Gbit/Sec x12 Pairs
RX[0:3]/TX[0:3] RX[0:3]/TX[0:3] RX[0:3]/TX[0:3] RX[0:3]/TX[0:3] RX[0:3]/TX[0:3] RX[0:3]/TX[0:3]
RX[0:3]/TX[0:3]
RX[0:3]/TX[0:3]
MDIO
I2C BUS
Serial
EEP VPX
P2
XAUI[5] RX[0:3]/TX[0:3]
VPX
P5
XAUI[7] RX[0:3]/TX[0:3]
P[24]
3.125Gbit/Sec x12 Pairs
P[3]
IDP-XDP
SM750 VGA
Controller VGAPCIe x1
500MB/Sec
Link Port “F”
PCIe x4
16GByte
NAND
Flash
Dual GigE Magnetics 1000BASE-T x2
1GigE x2
125MB/Sec x2
OpenVPX
MOD6-PAY-4F2T-12.2.2-4
10GBASE-BX4 10GBASE-BX4 10GBASE-BX4 10GBASE-BX4 10GBASE-BX4 10GBASE-BX4 10GBASE-BX4
Figure 1: CPU-111-10 Block Diagram

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 5
Specifications

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 6
3.2 Processing Architecture
3.2.1 Processor
The CPU-111-10 supports a 2.13GHz 4-Core Xeon L5408 Processor with 32KB data and 32KB of instruction
cache per core and 12MB of L2 shared cache. Processor features include:
One Intel quad-core L5408 Xeon Processor running at 2.13 GHz
32KB L1 Instruction and 32KB L1 Data Cache per core
12MB L2 Cache (shared)
1066/1333 MHz Front Side Bus supporting 8.5 GByte/Sec
transfer rates
3.2.2 Memory Controller Hub and DDR2 SDRAM
The Intel® 5100 Memory Controller Hub (MCH) provides dual memory controllers and 24 lanes of PCI Express
expansion (all of which are implemented on the CPU-111-10) for high-speed connectivity to dual XMC sites (8 lanes
each) and a PLX PEX8624PCIe Switch (8 lanes) for further PCI Express distribution. The MCH supports up to 4
GBytes of DDR2 SDRAM running at up to 1066 MHz double data rate speeds. MCH features include:
Intel 5100 MCH with 1066/1333 MHz Front Side Bus
4GB DDR2 ECC SDRAM at 533/667 MHz (1066 MHz DDR)
Two x8 PCI Express Ports to XMC Sites
One x8 PCI Express Port to PEX8624 Gen 2 PCIe Switch
ESI Bus to ICH9R I/O Controller Hub
3.2.3 I/O Controller Hub
The Intel® ICH9R I/O Controller Hub (ICH) chipset provides basic I/O, and standard PC system resources including
graphics, the real time clock, NV-RAM, timers, thermal management, and interrupt management. Features include:
Four Serial ATA Ports to VPX P4 Connector
Four USB Ports to VPX P4 Connector
LPC Bus to 16Mbit Firmware Hub
16Mbit SPI Flash
RS232/RS485 Serial Communications to VPX P4 Connector
x1 PCIe Interface supports SM750 VGA Controller
Real-time clock with 256 bytes of battery-backed RAM

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 7

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 8
3.3 PCI Express Architecture
The PCI Express (PCIe) structure is shown below. All PCIe links operate at Gen1 speeds. The CPU-111-10 does
not support XMC based root complexes, only end-points.
Intel 5100
MCH
Intel ICH9R
IOH
PLX
PEX8624
PCIe
Switch
XMC
J15
XMC
J25
IDT
Tsi384
IDT
Tsi384
Intel
82599
Intel
82571
Silicon Motion
SM750 VGA
PE0 - x8 PCIe
PE1 - x8 PCIe
PE2 - x8 PCIe PE3 –x4 PCIe
PE4 –x4 PCIe
PE5 - x8 PCIe
PE6 –x4 PCIe
PE7 –x1 PCIe
ESI
Bus
Figure 2: PCI Express Structure
The MCH provides 24 lanes of Gen1 PCIe and acts as the root complex. This is divided into three x8 ports. Two x8
ports connect to the XMC sites. The third x8 port connects to a PLX PEX8624 24-port Switch. This switch "fans
out" the MCH PCIe further as two x4 PCIe links to two IDT Tsi384 PCIe to PCI-X Bridges, providing a PCI-X
interface for each PMC site. The switch also supports a x8 link to an Intel 82599 Dual 10Gb Ethernet Controller,
providing a high-speed connection in the on-board 10GB Ethernet switch fabric.
The ICH9R has two PCIe ports. One x4 port is connected to an Intel 82571 Dual 1Gb Ethernet Controller to
support 1000BASE-T backplane control plane I/O. The remaining x1 PCIe port connects to a Silicon Motion
SM750 Graphics Controller.
3.3.1 Dual XMC Sites
Each XMC Site can support a x8 Gen1 PCIe endpoint per VITA42.3 using connectors J15 and J25. XMC based
root complexes are not supported on the CPU-111-10.
3.3.2 PLX PEX8624 PCIe Switch
The PEX8624 is a 6-port, 24-lane PCI Express switch configured as four ports. It has integrated low power SerDes
on all lanes and supports a fully non-blocking switch architecture. Its cut-thru packet latency is less than 160nSec
between symmetric ports (x8 and x8). The maximum data payload size is 2048 bytes.

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 9
3.3.2 IDT Tsi384 PCIe to PCI-X Bridges for PMC Support
The IDT Tsi384 is a high-performance bus bridge that efficiently connects the x4 PCIe link from the PEX8624 to a
64-bit 133MHz PCI-X bus. One Tsi384 is used per PMC site to maximize PCI-X transfer rates. The Tsi384's only
support 3.3V PCI-X I/O signaling.
3.3.3 Intel 82599 Dual 10Gb Ethernet Controller
The Intel 82599 10 Gigabit Ethernet Controller is a single component with two fully integrated 10Gbit Ethernet MAC
and XAUI ports. Each port can support KX4/KX (802.3ap*) interfaces and contains a SerDes for backward
compatibility with gigabit backplanes. The architecture is designed for low-latency data handling and provides
superior DMA transfer-rate performance. The 82599 also supports the IEEE 1588 precision time protocol (PTP) by
time stamping in-coming and out-going data packets.
3.3.4 Intel 82571 Dual 1Gb Ethernet Controller
The Intel 82571 Gigabit Ethernet Controller is a single component containing two fully integrated Gigabit Ethernet
Media Access Controllers and physical layer ports. Both ports contain a SerDes to support Gigabit backplane
applications. The 82571 provides high performance and low memory latency using a x4 PCI Express link to the
ICH9R I/O Hub.
Complies with 1Gb/Sec Ethernet/802.3ap
x4 PCI Express interface to ICH9R
MDII or SERDES interface to backplane
4-Wire SPI EEPROM Interface
3.3.5 Silicon Motion SM750 Graphics Controller
The SM750 is a PCI Express 2D multimedia mobile display controller device, packaged in a 265-pin BGA. Designed
to complement needs for the embedded industry, it provides video and 2D capability. It supports a wide variety of
I/O, including an analog RGB, two Zoom Video interfaces, and Pulse Width Modulation (PWM).
The 2D engine includes a front-end color space conversion with 4:1 and 1:8 scaling support. The video engine
supports two different video outputs (Dual Monitor), at 8-bit, 16-bit, or 32-bit per pixel and a 3-color hardware
cursor per video output.
Connects to ICH9R via x1 PCI Express Interface
16MByte Internal DDR SDRAM Video Memory
2D Graphics Accelerator
DMA Controller

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 10
3.4 10 Gigabit Ethernet Architecture
The CPU-111-10 utilizes 10Gb Ethernet (10GbE) to provide high-speed interconnection paths between the CPU,
both XMC sites, the backplane, and a front panel SFP+ module. The 10GbE architecture is shown below.
FULCRUM
FM3224
10GigE
24-Port
Switch
XMC
J16
XMC
J26
82599
NETLOGIC
AEL2005
VPX
P1
VPX
P2
VPX
P5
VPX
P4
SFP+
Port 1
Port 2
Port 3
Port 4
Port 7
Port 8
Port 11
Port 12
Port 13
Port 14
Port 20
Port 23
Port 24
Port 19
XA0
XA1
XA2
XA3
XA4
XA5
XA6
XA7
XA8
XA9
XA10
XA11
XA12
XA13 CROSSOVER
Figure 3: 10Gb Ethernet Architecture
3.4.1 Fulcrum FM3224 Switch
The FM3224 10GbE Switch is the heart of the CPU-111-10 SBC. Using 10Gb Ethernet, it connects the backplane to
the CPU, XMC Modules, and front panel SFP+ Fiber Optic I/O modules (not included with the CPU-111-10).
The FM3224 is a fully integrated single-chip wire-speed 10G Ethernet switch. In addition to enhanced layer-2
functionality, the FM3224 layer-3 capabilities include advanced classification, extensive congestion management, and
improved switch management flexibility.
Features of the FM3224 include:
300nS Latency
Advanced Policy Engine
Switch Virtualization and Scaling
Port and MAC Based Security
In-band Switch Management
Provides Full-Mesh connectivity between up to eight VPQ Node Boards
Support for Front Panel SFP+ Connector for Copper or Fiber Optic cables (Configuration
dependent)

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 11
Figure 4: 10Gb Switch Block Diagram
3.4.2 Intel 82599 Dual 10GB Ethernet
The 82599 provides a high-speed CPU path into the switch fabric for both data and switch management . The
interface to the switch consists of dual-channel XAUI (IEEE 802.3ae). The 82599 connects via x8 Gen2 PCIe to the
PEX8624 PCIe switch and from there to the CPU. As previously mentioned, the 82599 also supports IEEE 1588
precision time protocol (PTP) by time stamping in-coming and out-going data packets.
Figure 5: 82599 Block Diagram

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 12
3.4.3 SFP+ Interface (AEL2009)
The AEL2005 is a bidirectional single-channel 10 Gigabit Ethernet transceiver containing integrated EDC (Electronic
Dispersion Compensation) circuits targeted for 10GBASE-LRM optical modules and 10Gbps SFP+ applications.
The SFP+ connector is located on the CPU-111-10 front panel.
3.4.4 VPX 10Gb Ethernet I/O
Seven ports from the FM3224 10GbE switch are connected to the VPX backplane. The CPU-111-10 complies with
the VITA 46 OpenVPX standard for profile MOD6-PAY-4F2T-12.2.2-5. This profile covers the four 10GbE
channels on VPX connector P1. The remaining three 10GbE channels connect to P2, P4, and P5.
10GbE Port 23
KEY
KEY
SE
P0/J0
S
E
Data Plane
4 Fat Pipes
(4) 10GBASE-KX4
P2
OpenVPX Profile
MOD6-PAY-4F2T-12.2.2-5
Control Plane
Two Thin Pipes
(2) 1000BASE-T
10GbE Port 12
10GbE Port 8
S
E
KEY
S
EP3
S
EP4
S
EP5
S
EP6
User Defined
User Defined
User Defined
User Defined
User Defined
Color
Code
10GbE Port 14
10GbE Port 20
P1
Control Plane
Utility Plane
OpenVPX
Data Plane
User Defined
User Defined
Data Plane
PMC/XMC I/O
10GbE Port 4
10GbE Port 24
Figure 6: VPX 10GbE I/O

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 13
3.4.5 XMC 10GbE I/O
Each XMC site supports one 10GbE channel to provide a high-speed data path into the 10GbE switch fabric.
3.5 VPX General Purpose I/O
The CPU-111-10 provides general purpose I/O via VPX connector P4. This I/O can be connected to a rear transition
module or can be terminated on the backplane. The I/O consists of (4) SATA ports, (4) USB ports, (1) LPC bus, (1)
RS232/RS485 Serial Communications Port, (2) 1GbE SERDES channels, and (2) 1000BASE-T 1GbE ports.
3.6 Clocking
An IDT ICS9LPR501 CK505 Clock Synthesizer generates the majority of clocks used on the CPU-111-10. It
generates 100MHz differential clocks used by the CPU and PCIe peripherals. It also generates 48MHz, 33MHz, and
14MHz clocks used throughout the CPU-111-10. Clocks for DDR SDRAM are generated by the MCH. Separate
312.5MHz and 125MHz oscillators provide clocks to the FM3224 10GbE Switch.
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
CK505
CLOCK
GENERATOR
CPU_ITP
MCH_ITP
DB400
PEX8624
Tsi384 #1
Tsi384 #2
82599
XMC #1
XMC #2
SM750
ICH9R
LPC HDR
FWH
FM3224
XPD0
CPU0
MCH
CLK
BFR
DDR REG
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
CLK
BFR
DDR REG
312.5
MHZ
OSC
125
MHZ
OSC
CLK
BFR
CLK
BFR
FM3224
SRC8
CPU_0
CPU_1
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
48MHz
33MHz
14MHz
33MHz
33MHz
33MHz
33MHz
33MHz
100MHz
100MHz
125MHz
312.5MHz
SRC0
SRC1
SRC3
SRC4
SRC6
SRC7
SRC5
SRC9
SRC11
SRC2
82571
100MHz
SRC10
USB
PCI0
REF0
PCI1
PCI2
PCI3
PCI4
PCI5
Figure 7: Clocks

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 14
3.7 Reset Structure
A block diagram of the CPU-111-10 reset structure is shown below. The ispPOWR1220A provides reset glue logic
for the board. The backplane system reset (BP_SYSRST#) is an input when the CPU-111-10 is installed in a
peripheral slot and an output when installed in the system controller slot.
PEX8624
Tsi384 #1
Tsi384 #2
82599
XMC #1
XMC #2
SM750
CPU
LPC HDR
FWH
FM3224
AEL2005
82571
SSD
DDR REG
MCH_ITP
CPU_ITP
DDR REG
MCH
PMC #1
PMC #2
ICH9R
ispPOWR
1220A
CPU CORE
SUPPLY
VPX P1
VPX P0DUAL
DBNCR
FET
SWITCH
SYSCON#
BP_SYSRST#
RESET
SWITCH
VRM_PWRGD
BP_SYSRST#
PB_SYSRST#
ICH_CPU_PWRGD
PLTRST#
PLTRST1#
PLTRST2#
RSMRST#
SYS_PWRGD
SYS_PWRGD_3V3
CPU_PWRGD
ICH_PWRBTN#
PLTRST#
CPURST#
PCI_RST1#
PCI_RST2#
Figure 8: Reset Structure
When all non-core supplies are up and stable, the ICH9R release the platform reset, or PLTRST#. The 1220A
buffers this reset and distributes it throughout the board as PLTRST1# and PLTRST2#. When PLTRST# is released
and the CPU core supply is stable, the CPU reset is released and the board boots up.

Chapter 3 –Hardware Description
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC –User’s Manual 15
3.8 SMBus Architecture
The CPU-111-10 utilizes an SMBus to support inter-chip communications. This can range from management
functionality, e.g. reading temperature sensors, to setting up application specific operational conditions in the various
peripheral components. The SMBus runs at a maximum speed of 100KHz.
The ICH9R SMBus connects to the MCH and an I2C Bus Multiplexer, where the bus is then distributed around the
board. A separate SMBus connects the ICH9R to the FM3224 10GbE Switch to support initialization and out-of-
band switch management.
SMB_A is connected to the CK505 Clock Generator, the DB400 Clock Buffer, the ispPOWR1220A power
monitor/sequencer, various Temperature monitoring devices, and an I2C bus expander.
PEX8624
PECI MON
DUAL T.S.
82599
XMC #1
XMC #2
ispPOWR1220A
I2C BUS
MULTIPLEXER
VPX RTM
CK505 CLK
x4 MAX7500 T.S.
DB400
82571
SFP+
I2C BUS EXP
XDP
DEBUG
ICH9R
FM3224
MCH DDR2 SPD
DDR2 SPD
ICH_SMB SMB_B
SMB_A
DDR2_SMB
FM_SMB
Figure 9: SMBus Architecture
The I2C bus expander provides GPIO for reading the board geographic address, system controller status, and the
VPX backplane non-volatile memory read-only (NVMRO) status.
SMB_B is connected to the PEX8624 PCIe switch, the 82599 Dual 10GbE controller, 82571 dual 1GbE controller,
both XMC sites, the front panel SFP+ connector, and to a rear transition module via the VPX backplane.
The MCH provides one SMBus port which connects to two serial presence detect (SPD) EEPROM's containing
memory initialization parameters.