Silicon Laboratories EFR32 User manual

AN930: EFR32 2.4 GHz Matching Guide
The EFR32 devices include chip variants that provide 2.4 GHz-
only operation, sub-GHz-only operation, or dual-band (2.4 GHz
and sub-GHz) operation. In addition, the EFR32 chips are availa-
ble in a 7x7 mm 48-pin package and a 5x5 mm 32-pin package.
This application note describes the matching techniques applied
to the EFR32 Wireless Gecko Portfolio in the 2.4 GHz band.
For information on PCB layout requirements for proper 2.4 GHz operation, refer to
AN928: EFR32 Layout Design Guide. Refer to AN933: EFR32 2.4 GHz Minimal BOM
for information on minimizing the bill of materials. For information on the matching pro-
cedure for the sub-GHz path, refer to AN923: EFR32 sub-GHz Matching Guide.
KEY POINTS
• Description of the applied 2.4 GHz
matching networks and techniques for the
EFR32 device
•Detailed discussion of the design steps
and design examples
• Three different EFR32 versions: 7x7 mm
48-pin dual band version, 7x7 mm 48-pin
2.4 GHz version, and 5x5 mm 32-pin 2.4G
Hz version.
• Measured TX spectrum and RX sensitivity
results
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1. Introduction
This application note is intended to help users achieve the best 2.4 GHz RF match for targeted applications. It describes the details of
matching network design procedures and presents additional test results.
Thorough derivations of four different matching topologies are presented:
• A ladder 2-element LC match for up to 10 dBm power levels
• A ladder 4-element LCLC match for up to 20 dBm power levels
• A hybrid type match applying both discrete elements and a transmission line (LC-Tline-C) for up to 20 dBm power levels
• A parallel LC 2-element match for up to 13 dBm power levels
Readers simply seeking recommended values, topologies, and RF performance data should skip to Appendix 2. 2.4 GHz RF Network
Schematics and Technical Data.
The presented matches are tested with three EFR32 variants:
• 7x7 mm, 48-pin 2.4 GHz
• 5x5 mm, 32-pin 2.4 GHz
• 7x7 mm, 48-pin dual band
For example, the 7x7 mm, 48-pin 2.4 GHz-only version's package pinout is shown in the figure below. The 2.4 GHz RF pins are high-
lighted with a red box.
Figure 1.1. EFR32 2.4 GHz RF Pins
1.1 Related Literature
Related documentation includes:
•AN923: EFR32 sub-GHz Matching Guide
•AN928: EFR32 Layout Design Guide
•AN933: EFR32 2.4 GHz Minimal BOM
•AN0002.1: EFM32 and EFR32 Wireless Gecko Series 1 Hardware Design Considerations
AN930: EFR32 2.4 GHz Matching Guide
Introduction
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2. EFR RF Architecture Overview
The EFR32 chip family has separate sub-GHz and 2.4 GHz RF front ends. The sub-GHz part is not detailed here. The 2.4 GHz RF front
end architecture of the EFR32 chip is shown in the figure below.
The 2.4 GHz front end has a unified, single-ended TX and RX pin (2G4RF_IOP), so the TX and RX paths are tied together internally.
The 2G4RF_ION TX pin has to be grounded at the pin. It should consist of a good RF ground with multiple parallel GND vias.
Radio Transciever
2G4RF_IOP
2G4RF_ION
RF Frontend
PA
I
Q
LNA
BALUN
RFSENSE
Frequency
Synthesizer
DEMOD
AGC
IFADC
CRC
BUFC
MOD
FRC
RAC
PGA
Figure 2.1. 2.4 GHz Front End Configuration
The on-chip part of the front end comprises a variable (from 0 dBm to 20 dBm) power class AB differential PA, a variable PA tuning
cap, a differential LNA, an LNA/low-power PA match and protection circuit, and an integrated balun. The high-power PA is biased
through the PAVDD pin. Externally, a single-ended matching network and harmonic filtering are required.
AN930: EFR32 2.4 GHz Matching Guide
EFR RF Architecture Overview
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3. 2.4 GHz RF Matching Design Steps
2.4 GHz RF matching design for EFR32 chips consists of the following steps:
1. Determine the optimum termination impedance for the PA.
2. Choose the RF matching topology.
3. Create the initial design with ideal, loss-free elements. This ideal design can be used as a starting point for a design with parasitics.
4. Design with parasitics and losses. At 2.4 GHz, the parasitics of the SMD elements and the pcb have a major effect, so tuning/
optimization of the design is required. Here an optional EM simulation can be done, but simulations with well-estimated pcb parasit-
ics and SMD equivalent models usually give adequate results.
5. Conduct bench testing and tuning.
3.1 Determining the Optimum Termination Impedance for the PA
The first step of the matching design procedure is to determine the optimum termination impedance at the PA. The realized matching
network should present this impedance for the PA at the 2G4RF_IOP pin if 50 Ω termination is applied at the antenna port.
The 2G4RF_IOP RF port termination determines the major RF parameters, such as the delivered PA power and harmonic content in
TX mode or the sensitivity in RX mode. As part of the design process, the goal is to deliver maximum power to a 50 Ω output termina-
tion (e.g., to a 50 Ω antenna) in TX mode. In addition, proper harmonic suppression and good RX sensitivity in reception mode are
required.
The optimum termination impedance for delivering maximum power in TX mode is determined by load-pull testing. A good termination
impedance compromise for all EFR variants and for all power levels is Zload_opt = ~23+j11.5 Ω. Refer to Appendix 1. PA Optimum
Impedance Determination for more details. This termination impedance has to be shown by the matching network at the PA side if its
antenna output is terminated with a 50 Ω load.
The proper impedance at the single-ended output pin (2G4RF_IOP) also depends on the grounding of the other (2G4RF_ION) TX pin.
To keep its effect negligible, this pin should be massively connected ("back-routed") to the next ground layer beneath it by multiple vias,
as shown by the blue dashed ellipse in the figure below. More detailed information about proper layout design can be found in AN928:
EFR32 Layout Design Guide.
Figure 3.1. Element Match PCB Layout with Good 2G4RF_ION Grounding
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In real radio links, the TX power and the receiver sensitivity together (i.e., the link budget) determine the range. So, with the applied TX
termination impedance, the impedance match in RX mode should also be acceptable. Fortunately, the RX sensitivity is quite immune to
impedance variations. The sensitivty variation is less than 0.2 to 0.3 dB if the termination changes from 50 Ω to the PA optimum
impedance (Zload_opt) given above.
3.2 Choosing the RF Matching Topology
The second step of the matching design procedure is to choose the appropriate RF matching topology.
In addition to creating an optimum termination impedance on the IC side, the matching solution must exhibit sufficiently robust harmonic
filtering characteristics to comply with emissions standards. There are many different types of RF matching topologies. Separate match-
ing and harmonic filtering sections can be utilized, or they can be combined in one circuit. To minimize the number of elements, all
matches presented here are of the combined type, with low-pass circuits employed for their inherent harmonic suppression characteris-
tics.
Four 2.4 GHz matching topologies are presented here:
• A ladder 2-element LC match for up to 10 dBm power levels.
• A ladder 4-element LCLC match for up to 20 dBm power levels.
• A hybrid type applying both discrete elements and a transmission line (LC-Tline-C) for up to 20 dBm power levels.
• A parallel LC 2-element minimal BOM match for up to 13 dBm power levels. This match is derived from the hybrid LC-Tline-C match
by eliminating the Tline and second capacitor.
For final match schematics and RF performance data, refer to Appendix 2. 2.4 GHz RF Network Schematics and Technical Data.
The selection of the proper match from the above four topologies depends on special application requirements.
• The Ladder 2-Element Match has moderate second harmonic suppression, and, therefore, can only operate up to 10 dBm with
FCC compliance. It applies a series film type SMD (LQP15TN series from Murata) inductor and so has a higher cost than the paral-
lel LC match. Moreover, it has slightly higher insertion loss. The advantage of the Ladder 2-Element Match lies in its superior sup-
pression of third and higher harmonics. The Ladder 2-Element Match will be detailed in subsequent sections.
• At high power levels, the Ladder 4-Element LCLC Match gives very strong second and higher harmonic suppression but has slight-
ly lower TX power and worse sensitivity due to higher insertion loss. However, it is a very stable match, being less sensitive to ele-
ment spreading. For more information about the Ladder 4-Element Match design, refer to Appendix 3. 2.4 GHz Ladder 4-element RF
Matching Design Steps.
• The Hybrid Type LC-Tline-C Match uses the inexpensive LQG15HS multilayer inductor series from Murata. Its harmonic suppres-
sion is nearly as good as that of the Ladder 4-Element type but with lower cost and better insertion loss, i.e., slightly higher power
and better sensitivity. The drawback is a slightly larger footprint due to the 3.5 mm long transmission line. For more information
about the LC-Tline-C Match design, refer to Appendix 4. Transmission Line (Tline) Match for Minimal BOM Solutions (U.S. Patent
US9780757B1).
• The Parallel LC Match is a very low-cost, simplified version of the Hybrid Type LC-Tline-C match since the transmission line and
second parallel capacitor are eliminated. It features an inexpensive LQG15HS series inductor and minimal PCB area. It has very low
insertion loss and thus good power and sensitivity. The drawback is its reduced third or higher harmonic suppression, so it is only
FCC compliant up to ~13 dBm. It may be compliant at higher power levels if used with an antenna possessing higher harmonic sup-
pression characteristics. For more information about the parallel LC, refer to Appendix 4. Transmission Line (Tline) Match for Mini-
mal BOM Solutions (U.S. Patent US9780757B1).
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3.3 Initial Design with Ideal, Loss-Free Elements
After choosing the best topology for the application, the third step of the matching design procedure is to generate a lumped element
schematic of the match with ideal loss-free elements and without PCB parasitics. The matching circuit should show an input impedance
of Zload_opt = ~23 + j11.5 Ω terminated with a 50 Ω load at its output.
The matching design process starts with a simplified case in which all losses and parasitics are eliminated. Here, parasitic-free ideal
capacitors and inductors are used, and there are no PCB losses or parasitics. The real-world case can be derived later from this ideal
design by means of incremental tuning and optimization.
In the following sections, the design steps of the Ladder 2-Element Match are demonstrated. The design steps for the other three match
types can be found in Appendix 3. 2.4 GHz Ladder 4-element RF Matching Design Steps and Appendix 4. Transmission Line (Tline)
Match for Minimal BOM Solutions (U.S. Patent US9780757B1).
The matching circuit should show the Zload_opt = ~23 + j11.5 Ω impedance at the input while it is terminated by 50 Ω at its output. The
general, lumped, two-reactive-element matching technique can be applied to create a schematic of the simplest two-element match
(see Item 1 in 6. References). In theory, two possible solutions exist: low-pass and high-pass. These procedures, along with their corre-
sponding schematics and Smitch chart solutions, are shown in the figure below. The antenna side is denoted by the 50 Ω ZL load impe-
dance in the schematics and indicated by the DP1 points in the Smith chart centers. The PA side impedance is denoted by Zin in the
schematics and given by the TP3 endpoints in the Smith charts. In both the low-pass and high-pass cases, the TP3 endpoint is the
optimum impedance (Zload_opt = 23+j11.5 Ω). Since the circuit should also filter the harmonics, only the low-pass solution, which con-
sists of a series 2.3 nH inductor and a 1.4 pF parallel capacitor (as shown in the first column of the figure) can be used in real designs.
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Figure 3.2. Basic Two-Element Matching Techniques with Ideal Lumped Elements
3.4 Design with Parasitics and Losses
The fourth step should be to take into account the parasitics of the discrete components. For Silicon Labs reference designs 0402 or
0201-sized, surface mount device (SMD) elements are used. With 0201 elements, one can expect lower parasitics, but their handling is
more difficult.
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3.4.1 Effects of SMD Discrete Parasitics and Losses
Inductors are the most critical elements in matching networks due to their higher cost and lower Q compared to SMD capacitors. There
are three basic SMD inductor types: wirewound, metal-film-based, and multilayer. A good description of SMD inductors can be found in
Item 2 of 6. References. The wirewound inductor has the best Q, while the multilayer type has the worst. The better Q (i.e., lower loss)
helps achieve low insertion loss in low-pass ladder structures where the inductor is the series element. Unfortunately, the price of the
wirewound inductor is the highest, typically several cents, while the multilayer is the least expensive, typically much less than a cent
when purchased in high volume. Film type inductors are between these in cost, so they are a good compromise at 2.4 GHz in terms of
price and Q.
SMD parasitics are investigated in the ladder two-element match employing 0402 SMD elements and a film type inductor. Simplified
equivalent circuits of the Murata SMD capacitance (1.4 pF) and film inductance (2.3 nH) are shown in the figure below. These simplified
equivalent circuits are only accurate at the fundamental frequency. For higher harmonic simulations, the measured S-parameters given
by the SMD manufacturer are used. Using these SMD models, the impedance differs slightly from the optimum Zload_opt = 23 + j11.5
Ω at the generator side of the match (see Figure 3.4 2-Element Match Mistuning with Real SMD Elements on page 9). To shift it
back to the optimum, a slight decrease of the parallel capacitance to 1.2 pF is required.
Figure 3.3. Equivalent Circuits of Real SMDs at the Fundamental Frequency
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Figure 3.4. 2-Element Match Mistuning with Real SMD Elements
3.4.2 Rough Estimation of PCB Parasitics
In addition to the discrete parasitics, the following PCB trace parasitics also have significant effects:
•Series inductances (denoted by Ls)
• Parallel capacitances (denoted by Cp)
• Losses
These trace parasitics usually enforce the further decrease in values of the discrete low-pass prototype matching elements (series in-
ductance and parallel capacitance). There are three approaches to simulating PCB parasitics: lumped element, distributed element,
and EM-based. Since the trace lengths in the match are usually shorter than 1 mm (much lower than the wavelength at 2.4 GHz), even
the simple lumped element method gives good accuracy. The most accurate is the EM-based method, but that usually requires exper-
tise and expensive CAD tools.
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The figure below shows the reference plane positions used in the simulations for the EFR32 IC 2G4RF_IOP pin and for the discrete
SMD pins. Since the IC pin covers the whole pad area, the reference plane falls to the geometric center of the PCB pad. With the dis-
crete SMD elements, the reference plane is put at the ends of the SMD soldering pin.
Figure 3.5. Reference Planes with Real SMD Elements
Figure 3.6 Estimation of PCB Layout Parasitics on page 10 shows the Rf part of the top layer of the 5x5 mm packaged EFR single
band design with estimated pcb series parasitic inductor and parallel capacitor values. The series pcb parasitic inductors are calculated
here using the reference plane definitions of Figure 3.5 Reference Planes with Real SMD Elements on page 10. The parallel parasitic
cap values are calculated to the whole printed area including the soldering pads. Here, estimation both for the area cap (calculated from
the dielectric thickness down to the grounding layer beneath and from the pad dimensions) and the fringing field caps (to the side
ground metal on the same layer) are required. The gap to the side ground metal are given by the G parameters in the figure. The easi-
est way to make that estimation is to use a grounded coplanar calculator, which computes the unit parallel capacitance and series in-
ductance parasitics as well. Numerous calculators can be found on the internet. An example of this type of calculator is given in Item 3
of 6. References at the end of this document.
The ladder 2-element matching circuit with PCB parasitics is shown in Figure 3.7 2-Element Lumped Element Match with Discrete Mod-
els of PCB Layout Parasitics on page 11. The applied PCB layout is proper for incorporating a ladder four-element match; so, if only
the ladder two-element match is applied, the additional LC section (a series inductor denoted by L1 and a parallel capacitor denoted by
C1 ) is not populated. In this case, a 0 Ω resistor has to be used in the place of the series L1. The parasitic series inductance of this 0 Ω
resistor is ~0.1 nH, which is also included in the figure. The losses of the PCB traces are not taken into account because they are much
smaller compared to the losses of the applied SMD discretes.
Figure 3.6. Estimation of PCB Layout Parasitics
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Figure 3.7. 2-Element Lumped Element Match with Discrete Models of PCB Layout Parasitics
These PCB parasitics detune the matching network in the same way as the SMD parasitics described previously. Here, the further de-
crease of the applied series inductor (L0) to 1.8 nH and parallel capacitor (C0) to 1.1 pF compensates for the PCB parasitic effects.
Unfortunately, the harmonic suppression of the ladder two-element match is insufficient at the 20 dBm power level, so it is only used up
to 10 dBm. At power levels above 10 dBm, the ladder four-element match is required to comply with the harmonic restrictions of the
ETSI and FCC standards. However, below 10 dBm power levels, the ladder two-element match is advantageous because it has lower
cost and lower insertion loss compared to the ladder four-element match. Furthermore, if a dedicated match is designed for the low-
power regime, then it is useful to tune it to the optimum load-pull impedance of the 10 dBm power level, which is ~20 + j10 Ω as docu-
mented in Appendix 1. PA Optimum Impedance Determination and . The figure below shows the modified match (with L0 = 1.7 nH, C0
= 1.2 pF) to this new impedance.
Figure 3.8. 2-Element Match with SMD and PCB Layout Parasitics Tuned for the 10 dBm Power Level Optimum (20 + j10 Ω)
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3.4.3 EM Simulations
As mentioned previously, the best accuracy can be achieved by EM simulations. However, this step can be skipped if the proper CAD
tool is not available. The EM simulated results shown here were created by an Axiem 3D planar simulator of AWR Corporation.
The figure below shows a simulated layout. This layout is used for both the ladder two-element and four-element matches. Here, the
2G4RF_IOP pin of the EFR32 chip is connected to Port 2. The L0 inductor is connected between Ports 3 and 4, the C0 capacitor be-
tween Ports 5 and 6, the L1 inductor between Ports 7 and 8, and the C1 capacitor between Ports 9 and 10. For the ladder two-element
match, a 0 Ω is connected to the place of L1 and the C1 and is not fitted.
Figure 3.9. EM Simulated Layout for the Discrete Lumped Element Matches
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Figure 3.10.a shows the EM simulated impedance of the ladder two-element match at the EFR32 TX pin (Port 2) together with the tar-
geted 10 dBm power impedance (~20 + j10 Ω). They are quite close. Here an L0 series inductance of 1.9 nH and a C0 parallel capaci-
tance of 1.5 pF is used as shown in the following table.
Table 3.1. Final SMD Values for the Ladder Two-Element Match
Two-element Matching Network
Schematic
Reference Designator
Component Value Tolerance Part Number Manufacturer
LH0 1.9 nH ±0.05 nH LQP15MN1N9W02 Murata
CH0 1.5 pF ±0.1 pF GRM1555C1H1R5BA01D Murata
Figure 3.10.b shows the simulated transfer characteristic from the TX pin to the 50 Ω output port. As expected, the second harmonic
suppression is sufficient only up to ~10 dBm fundamental power.
Figure 3.10. EM Simulation Results of the Ladder Two-Element SMD Match
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3.5 Bench Tuning and Measured Results
The final (fifth) step of the matching design is bench tuning with real measurements. The figure below shows the impedance and trans-
fer characteristic measurement setup. Port 1 of the VNA is connected to the soldering pad of the 2G4RF_IOP pin through a pigtail (the
EFR32 chip is removed here as only the matching network is measured). The reference plane of the S-parameter measurements is
shifted to the TX pin. Port 2 is connected to the matching 50 Ω side output through a UFL connector.
Figure 3.11. Match Impedance and Transfer Characteristic Measurement
The figure below shows the measured impedance and transfer characteristic of the ladder two-element match with the final SMD ele-
ments. As shown, the real part is very close to the targeted 20 Ω, but the reactance is slightly higher (14 Ω instead of the targeted 10
Ω). This slight deviation causes a negligible (> 0.1 dB) power drop, so the match is not tuned further.
Second harmonic suppression is only 13.7 dB, so the ladder two-element match is, as expected, only proper for the lower (< +10 dBm)
power regimes.
Figure 3.12. Measured S11 and S21 (Transfer) Characteristic of the Ladder 2-element SMD Match
The measured ladder two- and four-element spectrum plots in the middle of the band (2.45 GHz) with the 7x7 mm dual band EFR32
version is shown in in the first column of Figure 3.13 Measured Spectrum Plots of the Dual Band 7x7 mm EFR32 with (a) a Ladder
Two-Element Match in 10 dBm Power State and (b) a Ladder Four-Element Match in 20 dBm Power State on page 15. In the second
column, the four-element match spectrum is also given. The ladder two-element match is tested with a 10 dBm power setting, while the
four-element match is tested with a 20 dBm power setting.
In the 20 dBm power setting, the achieved fundamental power is ~19 dBm at 2.45 GHz. Large volume measurements show approxi-
mately ±1 dB variation of the output power. The average is typically ~19.5 dBm with 134 mA total IC current. Note that the loss of the
applied UFL connector is approximately 0.3–0.5dB. With direct connection, the delivered power is around 20 dBm.
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With the ladder two-element match, the IC consumes ~40 mA current at ~10 dBm power level. At low power levels, due to the lower
current consumption and the required lower PA supply voltage, the built in dc-dc converter can supply the PA through the PA_VDD pin.
The generated supply voltage by the dc-dc converter is 1.8V, which is correct for PA operation up to 13 dBm power levels. Since the
dc-dc converter converts the higher external supply voltages to the optimum 1.8 V with good efficiency, the PA efficiency improves sig-
nificantly. Without the dc-dc converter, the PA unnecessarily burns significant dc power and, thus, has lower efficiency at higher supply
voltages. A second advantage is that, with the dc-dc converter, the PA power is stable independently of external VDD variations. For
these reasons, Silicon Labs suggests supplying the PA_VDD rail from the internal dc-dc converter up to power levels of 13 dBm. The
allowed harmonic level by the US FCC is –41.2 dBm EIRP (or 500 µV/m electric field strength at a distance of three meters), while it is
-30 dBm EIRP by EU ETSI regulation. As shown in the figures, the second harmonic with the ladder two-element match has approxi-
mately 3 dB margin to the more strict FCC limit at a 10 dBm power level. With the ladder four-element match, the margin is much larg-
er, even at the highest (20 dBm) power level.
It should be noted that, in the spectrum measurements, the Spectrum Analyzer is used as a wideband 50 Ω termination. With a real
antenna, the termination at the harmonics can differ significantly from 50 Ω with variations in power delivered to the antenna. Moreover,
the harmonic termination impedance at the matching output depends on the transmission line properties between the matching network
and the antenna. In addition, the radiation gain of the antenna can differ at harmonic frequencies. Due to these facts, the radiated har-
monic power levels can be very different from the conducted measurement results and must be checked with the final antenna.
The different package versions have no significant effect on the output spectrum using both the ladder two-element and four-element
matches. Band edge (2.4 GHz and 2.48 GHz) spectrum variations across the bands are typically less than 0.5 dB, and the harmonics
are also much lower than the allowed limits, independent of package versions. More information about power variation across the band
and the package effect can be found in Appendix 2. 2.4 GHz RF Network Schematics and Technical Data.
Figure 3.13. Measured Spectrum Plots of the Dual Band 7x7 mm EFR32 with (a) a Ladder Two-Element Match in 10 dBm Pow-
er State and (b) a Ladder Four-Element Match in 20 dBm Power State
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4. Sensitivity Measurements
The sensitivity of the ladder two-element and four-element matches with the 7x7 mm dual band EFR32MG1 series is compared in the
table below. Here, 20 byte long standard ZigBee® packages are used and 1 % PER sensitivity is shown. The measurements were
made at room temperature. More sensitivity data can be found in Table 4.1 on page 16.
The applied setup includes the WSTK motherboard and the BRD41XX type development boards with different match types. The
BRD41XX type boards apply a UFL RF connector and a UFL-SMA transition. These two elements cause approximately 0.5 dB addi-
tional attenuation. The RX sensitivity results shown are already compensated for by this error. The frequency is 2.405 GHz, i.e., the first
Zigbee channel.
These RX test results are done on a very limited number of samples and are typical. Large test sample sensitivity results are only avail-
able for the 7x7 mm dual band package with a four-element lumped element match and are provided in the data sheet.
Table 4.1. Measured Sensitivities of the Ladder Two-Element and Four-Element Matchings Using Standard 20-Byte ZigBee
Packages (After UFL Connector Compensation)
Package Type Matching Type Sensitivity [dBm]
7x7 mm, 48-pin, Dual Band
Ladder 2-Element –99.1
Ladder 4-Element –98.5
The Rx test conclusions are as follows:
1. The Rx sensitivity variation resulting from the different package versions is lower than 1 dB and typically 0.5dB (see Appendix
2.1 Measured TX Emission).
2. The low-power reduced element matches have approximately 0.2–0.5 dB better sensitivity compared to their high power counter-
part. In other words, two-element vs. four-element ladder match, or two-element minimum BOM vs. Tline minimum BOM match.
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5. Conclusions
1. The minimal BOM Tline match has nearly the same fundamental power, harmonic levels, and current consumption as the four-
element lumped element match, but with lower cost.
2. Both the ladder four-element match and the minimal BOM Tline match complies with the U.S. FCC (~ –41 dBm EIRP) and EU
ETSI (~ –30 dBm EIRP) harmonic limits with large (>10 dB) margin up to power levels of ~ 20 dBm.
3. The two-element minimal BOM match is ETSI and FCC-compliant up to a 13 dBm power level, while the ladder two-element match
complies up to 10 dBm.
4. Both the minimal BOM matches and the lumped element matches work well with the different package versions without significant
effects on the output spectrum. The power variation is usually less than 0.5 dB, which is less than the chip-to-chip variation.
5. All matches with all EFR32 package versions have less than ~0.5 dB power variation across the entire 2.4 GHz band.
6. Typical total IC current consumption is ~30 mA at 10 dBm and ~135 mA at 20 dBm power levels. For power levels up to 13 dBm,
Silicon Labs recommends that the PA be supplied from the internal dc-dc converter. The current does not vary excessively with
different packages.
7. The cost of the minimal BOM matches is significantly lower because only one affordable, external multilayer type SMD inductor is
used. The ladder matches are more expensive because film type inductors are used.
8. The sensitivity of the minimal BOM matches is the same or slightly better than that of their ladder counterparts.
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Conclusions
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6. References
1. Christian Gentili: Microwave Amplifiers and Oscillators, McGraw-Hill, 1987, ISBN0-07-022995-3
2. MuRata: http://www.murata.com/products/inductor/chip/feature/rf
3. http://wcalc.sourceforge.net/cgi-bin/coplanar.cgi(Copyright © 2001-2009 Dan McMahill.CGIC, copyright 1996, 1997, 1998, 1999,
2000 by Thomas Boutell and Boutell.Com, Inc.. Permission is granted to use CGIC in any application, commercial or noncommer-
cial, at no cost.)
AN930: EFR32 2.4 GHz Matching Guide
References
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Appendix 1. PA Optimum Impedance Determination
The matching network should present an optimum impedance for the PA at the 2G4RF_IOP pin if a 50 Ω termination is applied at the
antenna port. The optimum impedance depends on the power level and the package version. Fortunately, as shown below, they are
quite close to each other, so one proper match is a good compromise for all versions and power levels. The optimum impedances are
determined empirically by load-pull methods.
Figure A below shows the 2.4 GHz load-pull curves measured at the TX pin of the 7x7 mm, 48-pin 2.4 GHz single band EFR version
with 20 dBm power setting. The optimum impedance point here is ~23.7+j7.1 Ω and is quite constant with frequency. For example, in
the middle of the 2.4 GHz band (2.45 GHz), it is only very slightly off (~24.1 + j7.2 Ω).
Figure B below shows the measured 20 dBm, 2.4 GHz load pull data for the 7x7 mm, 48-pin dual band EFR version at the TX pin.
Here, the optimum impedance is approximately 23 + j11.5 Ω. At 2.45 GHz, the optimum is slightly lower: ~21 + j10.4 Ω.
Figure C below shows the measured 20 dBm, 2.4 GHz load-pull data for the 5x5 mm, 32-pin single band EFR version at the TX pin.
The optimum impedance here is approximately 20 + j14 Ω.
Figure 1.1. Load-Pull Curves and Optimum TX Load Impedances at the 2G4RF_IOP Pin of the Different EFR32 Package Ver-
sions: a) 7x7 mm Dual Band, b) 7x7 mm Single Band, c) 5x5 mm Single Band, d) Optimum TX Impedances Shown in One
Smith Chart
The 2.4 GHz, 20 dBm level optimum termination impedances for the three EFR versions are shown together in D of the above figure.
As only one common match will be used for all variations, a compromise must be found. Fortunately, the three optimum impedances
are close to each other i.e., within the ~0.3 dB degradation load-pull circles if one chooses the middle point, so if a good compromise is
AN930: EFR32 2.4 GHz Matching Guide
PA Optimum Impedance Determination
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used, the power variation is less than 0.3 dB. According to this, the selected target impedance for further PA matching design is
Zload_opt = ~23 + j11.5 Ω.
Further, the optimum impedance does not depend much on the power level. At a power level of 10 dBm, the optimum termination is
only slightly off: Zload_opt_10dBm = ~20 + j10.6 Ω for the 7x7 mm dual band EFR version.
AN930: EFR32 2.4 GHz Matching Guide
PA Optimum Impedance Determination
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