EACA EG 3014 User manual

EG 3014
EG 302
1
EXPANSION
TECHNICAL MANUAL

PREFACE
This manual is written to give abrief view of the theory of operation and technical information of
the Expander EG3014 and the optional interface boards that can be added to it. The manual can be
regarded as areference or areminder to the experienced technical people. It is expected that the reader
should have the basic knowledge of digital electronics in order to make full use of this manual.
Please do not hesitate to inform us about any errors, mistakes and information out of date. We are
pleased to correct the mistakes and up-date this manual.
1981

TABLE OF CONTENTS
1. EG3014 EXPANDER PAGE
1.1 Buffers and Address Decode Logic __ _ ______.6
1.2 Memory (RAM) _____.____..____. 6
1.3 Floppy Disk Interface ________________ 7
1.3.1 Controller Chip and Clock __„__„___. 7
1.3.2 Drive Select __„„_„______. 7
1.3.3 Address Decode ____________ 8
1.3.4 Data Separation _____ ______. 8
1.3.4.1 Internal Data Separator __ _—__ _. __ _. 8
1.3.4.2 External Data Separator __„„____. 9
1.3.5 Side Select __. __ _ ______.11
1.3.6 Card-Edge Pin Assignemnt
for Floppy Disk Interface _—__„___ __ _.1
1
1.4 Parallel Printer Interface ____'„ ____ __.12
1.4.1 Printer Status _____„_____. 12
1.4.2 Card-Edge Pin Assignment
for Parallel Printer Interface —_______.12
1.5 Connectors for Further Expansion ________. .13
1.5.1 Pin Assignment for the 50-pin Connector ___. _„ „ .13
1.5.2 Pin Assignment for the 20-pin Connector —___—_.14
1.6 Power Supply and Regulators __ ____ ____ __.15
2. EG3020 RS-232-C INTERFACE ___ _ ___ ___.16
2.1 UART __„_____„____. 16
2.1.1 Control Bits ____-____ _ _.16
2.1.2 Clock __„________„. 16
2.2 Baud Rate Generator _____, -___ ___.17
2.3 Address Decode ____ ____ __.___. 17
2.4 TTL/E IALevel Shifters ___________ 18
2.5 Busses __-------_--_.18
2.5.1 Pin Assignment for the RS-232-C Bus _-_____.18
2.5.2 Pin Connections between the Expander and the RS-232-C Interface __ _.19
2.6 Voltage Regulator ___ ___ _ _ ____-.19
3. EG3021 DOUBLE DENSITY ADAPTER (FLOPPY DISK) _____.20
3.1 Introduction ______ _„____. 20
3.2 Floppy Disk Controllers ___________ 20
3.3 Chip Select Decode Logic and Multiplexer _____. __.20
3.4 16 MHz Clock Generator _„„_„„____. 21
3.5 Write Precompensation ___ _____ _ _ __ _.21
3.6 Data Separator ______ __ _ _ __.21
3.6.1 Single Density _. _____ ______ 21
3.6.2 Double Density __ _ _______ __.23
4. EG3022 S-100 BUS INTERFACE ____„___.24
4.1 introduction ___ _____ __ __ ___.24
4.2 Address Lines ____ —______ _ .24
4.3 Data Lines ____„_______ 24
4.4 Control/Status Lines _„_____ ____.24
4.5 Vectored Interrupt Lines __ „________.25
4.6 Power Lines _________ __ ____ .25

PAGE
4.7 Bus and Connector Pin Assignment ______ ___—.25
4.7.1 Pin Assignment for the 50-pin Connector between the Expander
and the S-100 Bus Interface Board. ------_.25
4.7.2 Pin Assignment for the Connectors between the S-100 Bus Interface
Board and the Mother Board. __— — — — -_26
4.7.2.1 50-pin PCB Solder-to-board Connector ____-.26
4.7.2.2 34-pin PCB Solder-to-board Connector —_—--.27
4.7.3 Pin Assignment for the S-100 Bus Connector on the Mother Board __.27
5. COMPONENT LAYOUT DIAGRAMS _____--_ -30
6. SCHEMATICS _„_____-----•35
APPENDIX A—Pin Connections between the Expander and the Video Genie System _.43

INTRODUCTION
The Expander EG3014 provides useful interfaces to the main unit of the Video Genie System. It
includes 32K bytes of dynamic RAM memory, floppy disk controller and interface, and parallel printer
interface. There are optional interface boards that can be added to the Expander. They are the RS-232-C
interface and S-100 Bus interface.
The circuits of these interfaces are described briefly part by part so that the users may understand
their Expander more quickly and modify it to suit their own use.

1. EG3014 EXPANDER
INTRODUCTION
This expander board can be divided into six parts:
1
)
buffers and address decode
2) memory (RAM)
3) floppy disk interface
4) parallel printer interface
5) connectors for further expansion
6) power supply and regulators
These functional blocks are illustrated in Fig 1.1.
Fig 1.1
ZJ
CQ
c
o
\n
C
Q.
X
CJ LU
Address Y//
Buffer
Data
Buffer
Control/
Status
Buffer
Address
Decode
Memory
(RAM)
Floppy
Disk
Interface
^
dParallel
Printer
Interface
Connectors
For
Expansion
"7^
_^
>Disk
Drive
Parallel
Printer
RS232C
Interface
or
S-100
Bus
Interface
Power
Supply &
Regulators
±5V
+12V
^+8V
±16V

1.1 BUFFERS AND ADDRESS DECODE LOGIC
The data lines, address lines, and control and status lines are buffered by 74LS244. The buffers
are Z28, Z30, Z33, Z26 and Z20. In order to minimize the ringing and transient on the signal lines,
resistance terminators (680 and 220 ohms) are added at the inputs of the address buffers and the
control and status buffers.
Z29 and Z32 provide the memory block select signals, 32K and 48K to control CAS of the
RAM's, Z34 generates the decoded read/write signals to the floppy disk interface. Z27 and Z31 give
enable signals of aserial port, F8H or F9H, and of aparallel printer port of FDH.
1.2 MEMORY (RAM)
This part consists of dynamic RAM chips, address multiplexer, data buffers (74LS244) and
control timing logic. The RAM chips are 4116, 16K x1bits each and of 250nsec access time. The
row and column addresses are obtained from two multiplexers, Z9 and Z19 (74LS157). The control
timing logic generates RAS, MUX and CAS from Z10, and the simplified circuit and timings are
shown in Fig 1.2.
We may get 16K byte RAM's from this expansion unit just by inserting RAM chips into the
sockets of Z11 through Z18. Z11 is the MSB and Z18 the LSB. Z1 through Z8 are sockets for the
higher 16K bytes of RAM.
Fig 1.2 GENERATION OF RAS, MUX AND CAS
(a)
RFSH >
MREQ >^CAS

Fig 1.2
(b) Timing Diagram
RAS, MREQ
RFSH
MUX
D
CAS
\
M1 Cycle
memory
J<—Ror WCycle H
T1 T2 T3 T4
row
/
col \
\r
T1 T2 T3
i
A_
r
1.3 FLOPPY DISK INTERFACE
1.3.1 Controller chip and Clock
The floppy disk controller (FDC) used is FD1771 which operates at 1MHz. This clock
is derived from a8MHz crystal oscillator and adivide-by eight counter, Z54. An interrupt for
areal time clock occurs every 25 msec. This 40 Hz interrupt signal is obtained from aseries
of dividers, Z54, Z50, Z45 and Z44.
1.3.2 Drive Select
In order to select adrive, it is required to write alogical one to the corresponding bit of
the latch, Z42. The data lines assigned for drive selection are as follows.
Port
37E0WR
Data Bit
D0
D1
D2
D3
(active 'one'
Drive Select Signal
DS1
DS2
DS3
DS4
(active 'zero')
Any time selecting adrive, asignal Motor On of about 2sec. duration is generated by the
one-shot, Z47 and sent to the drive to turn on its motor.

1.3.3 Address Decode
The address decode for this floppy disk interface is assigned as in Table 1.1.
Table 1.1
Control Signal
37E0RD
37E0WR
37ECRD
37ECWR
(active low)
Signal To
Interrupt Logic
Drive Select
Disk Controller
Disk Controller
Function
Read Interrupt Status
Select Drive®-
3
Read Data From Disk Controller
Write Data To Disk Controller
Transfer of data between the Disk Controller and CPU is accomplished by the following
signals in Table 1.2.
Table 1.2
Address
A1 A0
1
1
11
37ECRD 37ECWR
(RE) (WR)
Status Register Command Register
Track Register Track Register
Sector Register Sector Register
Data Register Data Register
1.3.4 Data Separation
1.3.4.1 Internal Data Separator
FD1771 provides an internal data separation by pulling HIGH the signals,
XTDS (pin 25) and FDCLOCK (pin 26). The raw READ DATA from the disk drive
is fed into FDDATA (pin 27 of FD1771). Note that FD1771 has the compatibility
of soft sectored recording format on the diskette.
Practical experience tells us that an external data separator is more reliable in
data recovery than the internal data separation. XTDS is pulled LOW to select
external data separation. The separated clock and data are fed into FDCLOCK and
FDDATA respectively.
In each case, select the jumpers J1 ,J3 and J4 referring to the schematics and
component layout diagram. Normally, these jumpers are connected in the mode of
external data separation.

1.3.4.2 External Data Separator
The external data separator can be simplified as in Fig 1.3a Fig 1.3b shows the
timings of the data separator.
Fig 1.3 EXTERNAL DATA SEPARATOR
a) Circuit
FROM
Z47-13 vREAD
DATA
Z55
cZ59 1r-.
tf> >- -»SEP DATA
">- i*SEP
CLOCK
Z59
9C
13
Z55
RLI
SQ- 10
3>13 1
FF1 FF3 Z56
>0.1
CK
R
>CK
Q3
R
11
23_
Z60
>->
SI
Q
Z59 Z56
13
10
S2
i> Q
R
11