Eads Astrium SMCS332SpW User manual

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 2 of 131
– All Rights Reserved – Copyright per DIN 34 –
Document Revision History
Revision Date Responsible Modifications / Reasons for Change
1.0 June-05 Uwe Liebstückel First release
1.1 Nov-05 Uwe Liebstückel Section 11.3 Special Behaviour added
Section 4.2.2.8 Checksum generation figure added
1.2 Nov-05 Uwe Liebstückel Section 11.3 Special Behaviour deleted
Section 12 Handling Empty Packets added
1.3 Jul-06 Uwe Liebstückel Section 12 Handling Empty Packets changed
Section 4.2.2.3 Updated
1.4 Sep-06 Stephan Fischer Section 12 editorial modifications (ESA comments)
All Rights Reserved – Copyright per DIN 34: Copying of this document, and giving it to others and the use or
communication of the contents thereof, are forbidden without express authority. Offenders are liable to the payment of
damages. All rights are reserved in the event of the grant of a patent or the registration of a utility model or design.
Proprietary Notice: This document is the property of EADS Astrium GmbH and contains material proprietary to EADS
Astrium GmbH. The contents are for confidential use only and are not to be disclosed to any others in any manner, in
whole or in part, except with the express written approval of EADS Astrium GmbH or to the provision of the relevant
contract.

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 3 of 131
– All Rights Reserved – Copyright per DIN 34 –
Table of Contents
1Scope and Objectives................................................................................................................................................7
1.1 List of applicable documents...............................................................................................................................7
1.2 Reference Documents .........................................................................................................................................7
1.3 List of Abbreviations...........................................................................................................................................8
2Introduction...............................................................................................................................................................9
2.1 Interfaces ..........................................................................................................................................................10
2.2 Operation Modes ..............................................................................................................................................11
2.3 SMCS332SpW Control by SpaceWire link........................................................................................................11
2.4 Wormhole Routing............................................................................................................................................11
2.5 PPU Functional Description ............................................................................................................................12
2.6 Fault Tolerance.................................................................................................................................................12
2.7 Software Support...............................................................................................................................................12
2.8 Application........................................................................................................................................................13
2.9 SMCS332SpW connected with the old SMCS332..............................................................................................13
3The SpaceWire link ................................................................................................................................................14
3.1 Data/Strobe SpaceWire signals ........................................................................................................................14
3.2 Character level flow control.............................................................................................................................15
3.3 Link speeds........................................................................................................................................................16
3.4 Errors on links..................................................................................................................................................16
3.5 SpaceWire state on start up ..............................................................................................................................17
3.6 Link connections...............................................................................................................................................17
4Register Set..............................................................................................................................................................18
4.1 Register address map........................................................................................................................................18
4.1.1 SMCS332SpW status and control registers .............................................................................................. 18
4.1.2 SMCS332SpW channel 1 status and control registers .............................................................................. 19
4.1.3 SMCS332SpW channel 2 status and control registers .............................................................................. 20
4.1.4 SMCS332SpW channel 3 status and control registers .............................................................................. 21
4.1.5 SMCS332SpW GPIO control registers ..................................................................................................... 22
4.1.6 Time code control registers....................................................................................................................... 22
4.2 Register Description .........................................................................................................................................23
4.2.1 General SMCS Registers .......................................................................................................................... 23
4.2.1.1 SMCS332SpW Interface Control Register (SICR) ............................................................................... 23
4.2.1.2 Transmit bitrate base Register (TRS_CTRL)........................................................................................ 23
4.2.1.3 Route Control Status Register (RT_CTRL) .......................................................................................... 24
4.2.1.4 Interrupt Status Register (ISR).............................................................................................................. 24
4.2.1.5 Interrupt Mask Register (IMR) ............................................................................................................. 27
4.2.1.6 COMI Chip Select0 Boundary Register (COMI_CS0R) ...................................................................... 27
4.2.1.7 COMI Arbitration Control Register (COMI_ACR) .............................................................................. 27
4.2.1.8 PRCI Register (PRCIR) ....................................................................................................................... 28
4.2.2 Channel 1 Registers .................................................................................................................................. 29
4.2.2.1 Channel 1 SpaceWire Mode Register (CH1_DSM_MODR)............................................................ 29
4.2.2.2 Channel 1 SpaceWire Command Register (CH1_DSM_CMDR)......................................................... 29

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 4 of 131
– All Rights Reserved – Copyright per DIN 34 –
4.2.2.3 Channel 1 Link SpaceWire Status Register (CH1_DSM_STAR)......................................................... 30
4.2.2.4 Channel 1 SpaceWire Test Register (CH1_DSM_TSTR) .................................................................... 31
4.2.2.5 Channel 1 Address Register (CH1_ADDR).......................................................................................... 31
4.2.2.6 Channel 1 Route Address Register (CH1_RT_ADDR) ........................................................................ 32
4.2.2.7 Channel 1 Protocol Status Register (CH1_PR_STAR)......................................................................... 32
4.2.2.8 Channel 1 Control Register 1 (CH1_CNTRL1).................................................................................... 33
4.2.2.9 Channel 1 Control Register 2 (CH1_CNTRL2).................................................................................... 34
4.2.2.10 Channel 1 Header Transaction ID (CH1_HTID) .............................................................................. 35
4.2.2.11 Channel 1 Header Control Byte (CH1_HCNTRL) ........................................................................... 35
4.2.2.12 Channel 1 Error Source Register 1 (CH1_ESR1) ............................................................................. 35
4.2.2.13 Channel 1 Error Source Register 2 (CH1_ESR2) ............................................................................. 36
4.2.2.14 Channel 1 COMI Configuration Register (CH1_COMICFG) .......................................................... 36
4.2.2.15 Channel 1 Transmit Start Address Register (CH1_TX_SAR) .......................................................... 37
4.2.2.16 Channel 1 Transmit End Address Register (CH1_TX_EAR) ........................................................... 38
4.2.2.17 Channel 1 Transmit Current Address Register (CH1_TX_CAR) ..................................................... 38
4.2.2.18 Channel 1 Transmit FIFO (CH1_TX_FIFO) .................................................................................... 39
4.2.2.19 Channel 1 Transmit EOP Bit Register (CH1_TX_EOPB) ................................................................ 39
4.2.2.20 Channel 1 Receive Start Address Register (CH1_RX_SAR) ........................................................... 39
4.2.2.21 Channel 1 Receive End Address Register (CH1_RX_EAR) ............................................................ 40
4.2.2.22 Channel 1 Receive Current Address Register (CH1_RX_CAR) ...................................................... 40
4.2.2.23 Channel 1 Receive FIFO (CH1_RX_FIFO)...................................................................................... 41
4.2.2.24 Channel 1 Status Register (CH1_STAR) .......................................................................................... 41
4.2.3 Channel 2 Registers .................................................................................................................................. 41
4.2.4 Channel 3 Registers .................................................................................................................................. 41
4.2.5 Time Code Registers................................................................................................................................. 42
4.2.5.1 Time Code Control Register (TIME_CNTRL) ..................................................................................... 42
4.2.5.2 Time Code Value Register (TIME_CODE).......................................................................................... 42
5SMCS332SpW Modes.............................................................................................................................................44
5.1 HOCI Data Transfer.........................................................................................................................................44
5.2 COMI Data Transfer ........................................................................................................................................45
5.3 COMI Arbitration .............................................................................................................................................45
5.4 Control by Link.................................................................................................................................................48
5.4.1 Selecting remote mode.............................................................................................................................. 48
5.4.2 Determination of the control link.............................................................................................................. 48
5.4.3 Protocol and Commands ........................................................................................................................... 48
5.4.4 Host Data Bus / GPIO Port ....................................................................................................................... 49
5.4.5 Restrictions ............................................................................................................................................... 49
5.5 Wormhole Routing............................................................................................................................................49
5.5.1 Overview................................................................................................................................................... 49
5.5.2 Wormhole routing on SMCS332SpW....................................................................................................... 50
5.5.3 Routing Implementation on SMCS332SpW ............................................................................................. 50
5.5.4 SMCS332332SpW Routing Examples...................................................................................................... 51
5.6 Header bytes generation...................................................................................................................................51
5.6.1 Header field control bit ............................................................................................................................. 51
5.6.2 Routing and Checksum Generation........................................................................................................... 53
5.7 Time Code Interface..........................................................................................................................................54
5.7.1 SMCS33SpW transmit time code ............................................................................................................. 54
5.7.2 SMCS332SpW receive time code............................................................................................................. 55
5.8 SMCS332SpW Version Control ........................................................................................................................55
6Programming and Operation Modes ....................................................................................................................56
6.1 SMCS332SpW Initialization..............................................................................................................................56
6.1.1 SMCS332SpW Interface Control Register ............................................................................................... 56
6.1.2 Transmit Bitrate Register (TRS_CTRL) ................................................................................................... 56

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 5 of 131
– All Rights Reserved – Copyright per DIN 34 –
6.1.3 SMCS332SpW Interrupt Status Register (ISR) ........................................................................................ 56
6.1.4 SMCS332SpW Interrupt Mask Register ................................................................................................... 57
6.1.5 Channel specific configuration registers ................................................................................................... 57
6.1.5.1 SpaceWire Mode Register (CHx_DSM_MODR)................................................................................. 57
6.1.5.2 COMI Configuration Register (CHx_COMICFG) ............................................................................... 57
6.1.5.3 Control Register 1 (CHx_CNTRL1) ..................................................................................................... 57
6.1.5.4 SpaceWire Command Register (CHx_DSM_CMDR) .......................................................................... 57
6.2 Data transfer via COMI....................................................................................................................................58
6.3 Data Transfer via HOCI...................................................................................................................................61
6.3.1 Special behaviour in case of SpaceWire link error ................................................................................... 62
7Signal Description...................................................................................................................................................64
8Electrical Specifications..........................................................................................................................................67
8.1 Absolute Maximum Ratings ..............................................................................................................................67
8.2 DC Electrical Characteristics...........................................................................................................................67
8.3 Power consumption...........................................................................................................................................68
8.4 PLL Filter .........................................................................................................................................................69
8.5 Power and Ground Guidelines .........................................................................................................................69
9Timing Parameters.................................................................................................................................................70
9.1 Clock Signals ....................................................................................................................................................70
9.2 Reset..................................................................................................................................................................72
9.3 Host Read..........................................................................................................................................................73
9.4 Host Write.........................................................................................................................................................75
9.5 COMI Read.......................................................................................................................................................77
9.6 COMI Write ......................................................................................................................................................78
9.7 COMI Arbitration .............................................................................................................................................79
9.8 CPUR, SES, Interrupt.......................................................................................................................................80
9.9 Links..................................................................................................................................................................81
9.10 Test Port (JTAG)...............................................................................................................................................82
10 Mechanical Data .....................................................................................................................................................84
10.1 Package Dimensions.........................................................................................................................................84
10.2 Pin Assignment .................................................................................................................................................85
11 Additional Informations.........................................................................................................................................87
11.1 Frequently Asked Questions .............................................................................................................................87
11.2 BSDL File for the SMCS332SpW......................................................................................................................90
12 Handling Empty Packets......................................................................................................................................110
12.1 Description .....................................................................................................................................................110
12.2 Workaround....................................................................................................................................................113
13 Simple Interprocessor Communication Protocol Specification ........................................................................114
13.1 Application Scenario.......................................................................................................................................114
13.2 Assumptions about the Environment...............................................................................................................115

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 6 of 131
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13.3 Service Specification.......................................................................................................................................115
13.3.1 Transport of data between two nodes...................................................................................................... 115
13.3.2 Execution of control commands.............................................................................................................. 116
13.3.2.1 Simple Control Commands ............................................................................................................. 116
13.3.2.2 Complex Control Commands.......................................................................................................... 117
13.4 Procedure Rules..............................................................................................................................................118
13.4.1 Acknowledgements................................................................................................................................. 118
13.4.2 Access to Command Signal Output Ports ............................................................................................... 119
13.4.3 Safety Critical Commands ...................................................................................................................... 119
13.4.4 Reset Commands .................................................................................................................................... 120
13.4.5 Shutdown Link Channel Operation / Restart Link Channel Operation................................................... 121
13.4.6 Read of Link Interface Status Register ................................................................................................... 121
13.5 Encoding (Format) of Transactions................................................................................................................122
13.5.1 Header and EOP Coding ......................................................................................................................... 122
13.5.2 Control Word Coding Specification........................................................................................................ 122
13.5.3 Link Interface Status Register Encoding................................................................................................. 124
13.5.4 Data Transfer Type Transactions ............................................................................................................ 125
13.5.5 Read Link Interface Status Register Transaction .................................................................................... 126
13.5.6 Enable Command Execution Transaction ............................................................................................... 127
13.5.7 Critical Simple Command Execution Transaction .................................................................................. 128
13.6 Glossary..........................................................................................................................................................129
14 Differences between the SMCS332SpW and the old SMCS332........................................................................130
14.1 Summary of changed/modified/added registers or register bits......................................................................130
14.2 Pin Modifications............................................................................................................................................131

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 7 of 131
– All Rights Reserved – Copyright per DIN 34 –
1Scope and Objectives
This document describes in detail the new SMCS332SpW. The SMCS332SpW provides an interface between
three SpaceWire links according to the SpaceWire Standard ECSS-E-50-12A and a data processing node like a
CPU.
1.1 List of applicable documents
Number Document
AD1 ECSS-E-50-12A
SpaceWire -Links, nodes,
routers and network
24 January 2003
AD2 SMCS332SpW_RS-01 SMCS332SpW
Requirements Specification
1.2 Reference Documents
The documents below have been used as support for establishing this document and contain background
information relating to the subjects addressed.
Number Document
RD1 Issue 2, 21.04.1999 SMCS332 User Manual

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 8 of 131
– All Rights Reserved – Copyright per DIN 34 –
1.3 List of Abbreviations
AD Applicable Document
API Application Programming Interface
ASIC Application Specific Integrated Circuit
CODEC COder / DECoder
COMI Communication Memory Interface
DPU Data Processing Unit
DSP Digital Signal Processor
EOP End Of Packet
EEP Error End Of Packet
ESC Escape
FCT Flow Control Token
FIFO First In First Out
FPGA Field Programmable Gate Array
GPIO General Purpose Input Output
JTAG Joint Testing Action Group
HOCI Host Control Interface
LVDS Low Voltage Differential Signalling
LSB Least Significant Bit
MSB Most Significant Bit
PCB Printed Circuit Board
PE Processing Element
PPU Protocol Processing Unit
PRCI Protocol Command Interface
SIC Simple Interprocessor Communication
SRAM Static Random Access Memory
SSRAM Synchronous Static Random Access Memory
SMCS Scalable Multichannel Communication Subsystem
TBC to be confirmed
TBD to be defined

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 9 of 131
– All Rights Reserved – Copyright per DIN 34 –
2Introduction
The SMCS332SpW provides an interface between 3 SpaceWire links according to the SpaceWire Standard ECSS-E-50-12A
specification and a data processing node consisting of a CPU and a communication data memory. The SMCS332SpW
provides HW supported execution of the major parts of the simple interprocessor communication protocol, particularly:
· transfer of data between two nodes of a multi-processor system with minimal host CPU intervention,
· execution of simple commands to provide basic features for system control functions,
· provision of fault tolerant features.
However, with disabling of features such as the protocol handling or with reduction of the transmit rate also low power usage
is supported.
SpaceWire
Receive
Transmit
Protocol
Channel1
Channel2
Channel3
COMI
HOCI
PRCI
JTAG
D/S RCV 1
D/S TRM 1
D/S RCV 2
D/S TRM 2
D/S TRM 3
D/S RCV 3
CMADR
CM_CONTROL
CMDATA
HADR
H_CONTROL
HDATA
HINTR
CPUR
SES
TEST
CLOCK
RESET
Figure 1: SMCS332SpW Block Diagram
Target applications are heterogeneous multi-processor systems supported by scalable interfaces including the little/big
endian byte swapping. The SMCS332SpW connects modules with different processors (e.g. ADSP21020, SHARC, ERC32,
TMS320C40). Any kind of network topology could be realized through the high speed point-to-point SpaceWire-links (see
chapter Applications in sectioon 2.8).

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 10 of 131
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2.1 Interfaces
The SMCS332SpW consists of the following blocks (See block diagram of the SMCS332SpW in Figure 1):
• 3 bidirectional SpaceWire [AD1] channels, all comprising the DS-link SpaceWire cell, receive and transmit
sections (each including FIFOs) and a protocol processing unit (PPU). Each channel allows full duplex
communication up to 200 Mbit/s in each direction. With protocol command execution a higher level of
communication is supported. Link disconnect detection and parity check at character level are performed. A
checksum generation for a check at packet level can be enabled.
The transmit rate is selectable between 1.25 and 200 Mbit/s. The start up transmit rate is 10 Mbit/s. For special
applications the data transmit rate can be programmed to values even below 10 Mbit/s; the lowest possible
SpaceWire transmit rate is 1.25 Mbit/s (the next values are 2.5 and 5 Mbit/s).
• Communication Memory Interface (COMI) performs autonomous accesses to the communication memory of the
module to store data received via the links or to read data to be transmitted via the links. The COMI consists of
individual memory address generators for the receive and transmit direction of every SpaceWire link channel. The
access to the memory is controlled via an arbitration unit providing a fair arbitration scheme. Two SMCS332SpW
can share one DPRAM without external arbitration logic.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type.
Operation in little or big endian mode is configurable through internal registers.
The COMI address bus is 16 bit wide allowing direct access of up to 64K words (32 bit) of the DPRAM. Two chip
select signals are provided to allow splitting of the 64k address space in two memory banks.
• Host Control Interface (HOCI) gives read and write access to the SMCS332SpW configuration registers and to the
SpaceWire channels for the controlling CPU. Viewed from the CPU, the interface behaves like a peripheral that
generates acknowledges to synchronize the data transfers and which is located somewhere in the CPU's address
space.
Packets can be transmitted or received directly via the HOCI. In this case the Communication Memory (DPRAM)
is not strictly needed. However, in this case the packet size should be limited to avoid frequent CPU interaction.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. The byte alignment can
be configured for little or big endian mode through an external pin.
Additionally the HOCI contains the interrupt signalling capability of the SMCS by providing an interrupt output,
the interrupt status register and interrupt mask register to the local CPU.
A special pin is provided to select between control of the SMCS332SpW by HOCI or by link. If control by link is
enabled, the host data bus functions as a 32-bit general purpose interface (GPIO).
• Protocol Command Interface (PRCI) that collects the decoded commands from all PPUs and forwards them to
external circuitry via 5 special pins.
• JTAG Test Interface that represents the boundary scan testing provisions specified by IEEE Standard 1149.1 of the
Joint Testing Action Group (JTAG). The SMCS' test access port and on-chip circuitry is fully compliant with the
IEEE 1149.1 specification. The test access port enables boundary scan testing of circuitry connected to the SMCS
I/O pins.