Eads Astrium SMCS332SpW User manual

SMCS332SpW
User Manual
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 2 of 131
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Document Revision History
Revision Date Responsible Modifications / Reasons for Change
1.0 June-05 Uwe Liebstückel First release
1.1 Nov-05 Uwe Liebstückel Section 11.3 Special Behaviour added
Section 4.2.2.8 Checksum generation figure added
1.2 Nov-05 Uwe Liebstückel Section 11.3 Special Behaviour deleted
Section 12 Handling Empty Packets added
1.3 Jul-06 Uwe Liebstückel Section 12 Handling Empty Packets changed
Section 4.2.2.3 Updated
1.4 Sep-06 Stephan Fischer Section 12 editorial modifications (ESA comments)
All Rights Reserved – Copyright per DIN 34: Copying of this document, and giving it to others and the use or
communication of the contents thereof, are forbidden without express authority. Offenders are liable to the payment of
damages. All rights are reserved in the event of the grant of a patent or the registration of a utility model or design.
Proprietary Notice: This document is the property of EADS Astrium GmbH and contains material proprietary to EADS
Astrium GmbH. The contents are for confidential use only and are not to be disclosed to any others in any manner, in
whole or in part, except with the express written approval of EADS Astrium GmbH or to the provision of the relevant
contract.

SMCS332SpW
User Manual
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Table of Contents
1Scope and Objectives................................................................................................................................................7
1.1 List of applicable documents...............................................................................................................................7
1.2 Reference Documents .........................................................................................................................................7
1.3 List of Abbreviations...........................................................................................................................................8
2Introduction...............................................................................................................................................................9
2.1 Interfaces ..........................................................................................................................................................10
2.2 Operation Modes ..............................................................................................................................................11
2.3 SMCS332SpW Control by SpaceWire link........................................................................................................11
2.4 Wormhole Routing............................................................................................................................................11
2.5 PPU Functional Description ............................................................................................................................12
2.6 Fault Tolerance.................................................................................................................................................12
2.7 Software Support...............................................................................................................................................12
2.8 Application........................................................................................................................................................13
2.9 SMCS332SpW connected with the old SMCS332..............................................................................................13
3The SpaceWire link ................................................................................................................................................14
3.1 Data/Strobe SpaceWire signals ........................................................................................................................14
3.2 Character level flow control.............................................................................................................................15
3.3 Link speeds........................................................................................................................................................16
3.4 Errors on links..................................................................................................................................................16
3.5 SpaceWire state on start up ..............................................................................................................................17
3.6 Link connections...............................................................................................................................................17
4Register Set..............................................................................................................................................................18
4.1 Register address map........................................................................................................................................18
4.1.1 SMCS332SpW status and control registers .............................................................................................. 18
4.1.2 SMCS332SpW channel 1 status and control registers .............................................................................. 19
4.1.3 SMCS332SpW channel 2 status and control registers .............................................................................. 20
4.1.4 SMCS332SpW channel 3 status and control registers .............................................................................. 21
4.1.5 SMCS332SpW GPIO control registers ..................................................................................................... 22
4.1.6 Time code control registers....................................................................................................................... 22
4.2 Register Description .........................................................................................................................................23
4.2.1 General SMCS Registers .......................................................................................................................... 23
4.2.1.1 SMCS332SpW Interface Control Register (SICR) ............................................................................... 23
4.2.1.2 Transmit bitrate base Register (TRS_CTRL)........................................................................................ 23
4.2.1.3 Route Control Status Register (RT_CTRL) .......................................................................................... 24
4.2.1.4 Interrupt Status Register (ISR).............................................................................................................. 24
4.2.1.5 Interrupt Mask Register (IMR) ............................................................................................................. 27
4.2.1.6 COMI Chip Select0 Boundary Register (COMI_CS0R) ...................................................................... 27
4.2.1.7 COMI Arbitration Control Register (COMI_ACR) .............................................................................. 27
4.2.1.8 PRCI Register (PRCIR) ....................................................................................................................... 28
4.2.2 Channel 1 Registers .................................................................................................................................. 29
4.2.2.1 Channel 1 SpaceWire Mode Register (CH1_DSM_MODR)............................................................ 29
4.2.2.2 Channel 1 SpaceWire Command Register (CH1_DSM_CMDR)......................................................... 29

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4.2.2.3 Channel 1 Link SpaceWire Status Register (CH1_DSM_STAR)......................................................... 30
4.2.2.4 Channel 1 SpaceWire Test Register (CH1_DSM_TSTR) .................................................................... 31
4.2.2.5 Channel 1 Address Register (CH1_ADDR).......................................................................................... 31
4.2.2.6 Channel 1 Route Address Register (CH1_RT_ADDR) ........................................................................ 32
4.2.2.7 Channel 1 Protocol Status Register (CH1_PR_STAR)......................................................................... 32
4.2.2.8 Channel 1 Control Register 1 (CH1_CNTRL1).................................................................................... 33
4.2.2.9 Channel 1 Control Register 2 (CH1_CNTRL2).................................................................................... 34
4.2.2.10 Channel 1 Header Transaction ID (CH1_HTID) .............................................................................. 35
4.2.2.11 Channel 1 Header Control Byte (CH1_HCNTRL) ........................................................................... 35
4.2.2.12 Channel 1 Error Source Register 1 (CH1_ESR1) ............................................................................. 35
4.2.2.13 Channel 1 Error Source Register 2 (CH1_ESR2) ............................................................................. 36
4.2.2.14 Channel 1 COMI Configuration Register (CH1_COMICFG) .......................................................... 36
4.2.2.15 Channel 1 Transmit Start Address Register (CH1_TX_SAR) .......................................................... 37
4.2.2.16 Channel 1 Transmit End Address Register (CH1_TX_EAR) ........................................................... 38
4.2.2.17 Channel 1 Transmit Current Address Register (CH1_TX_CAR) ..................................................... 38
4.2.2.18 Channel 1 Transmit FIFO (CH1_TX_FIFO) .................................................................................... 39
4.2.2.19 Channel 1 Transmit EOP Bit Register (CH1_TX_EOPB) ................................................................ 39
4.2.2.20 Channel 1 Receive Start Address Register (CH1_RX_SAR) ........................................................... 39
4.2.2.21 Channel 1 Receive End Address Register (CH1_RX_EAR) ............................................................ 40
4.2.2.22 Channel 1 Receive Current Address Register (CH1_RX_CAR) ...................................................... 40
4.2.2.23 Channel 1 Receive FIFO (CH1_RX_FIFO)...................................................................................... 41
4.2.2.24 Channel 1 Status Register (CH1_STAR) .......................................................................................... 41
4.2.3 Channel 2 Registers .................................................................................................................................. 41
4.2.4 Channel 3 Registers .................................................................................................................................. 41
4.2.5 Time Code Registers................................................................................................................................. 42
4.2.5.1 Time Code Control Register (TIME_CNTRL) ..................................................................................... 42
4.2.5.2 Time Code Value Register (TIME_CODE).......................................................................................... 42
5SMCS332SpW Modes.............................................................................................................................................44
5.1 HOCI Data Transfer.........................................................................................................................................44
5.2 COMI Data Transfer ........................................................................................................................................45
5.3 COMI Arbitration .............................................................................................................................................45
5.4 Control by Link.................................................................................................................................................48
5.4.1 Selecting remote mode.............................................................................................................................. 48
5.4.2 Determination of the control link.............................................................................................................. 48
5.4.3 Protocol and Commands ........................................................................................................................... 48
5.4.4 Host Data Bus / GPIO Port ....................................................................................................................... 49
5.4.5 Restrictions ............................................................................................................................................... 49
5.5 Wormhole Routing............................................................................................................................................49
5.5.1 Overview................................................................................................................................................... 49
5.5.2 Wormhole routing on SMCS332SpW....................................................................................................... 50
5.5.3 Routing Implementation on SMCS332SpW ............................................................................................. 50
5.5.4 SMCS332332SpW Routing Examples...................................................................................................... 51
5.6 Header bytes generation...................................................................................................................................51
5.6.1 Header field control bit ............................................................................................................................. 51
5.6.2 Routing and Checksum Generation........................................................................................................... 53
5.7 Time Code Interface..........................................................................................................................................54
5.7.1 SMCS33SpW transmit time code ............................................................................................................. 54
5.7.2 SMCS332SpW receive time code............................................................................................................. 55
5.8 SMCS332SpW Version Control ........................................................................................................................55
6Programming and Operation Modes ....................................................................................................................56
6.1 SMCS332SpW Initialization..............................................................................................................................56
6.1.1 SMCS332SpW Interface Control Register ............................................................................................... 56
6.1.2 Transmit Bitrate Register (TRS_CTRL) ................................................................................................... 56

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6.1.3 SMCS332SpW Interrupt Status Register (ISR) ........................................................................................ 56
6.1.4 SMCS332SpW Interrupt Mask Register ................................................................................................... 57
6.1.5 Channel specific configuration registers ................................................................................................... 57
6.1.5.1 SpaceWire Mode Register (CHx_DSM_MODR)................................................................................. 57
6.1.5.2 COMI Configuration Register (CHx_COMICFG) ............................................................................... 57
6.1.5.3 Control Register 1 (CHx_CNTRL1) ..................................................................................................... 57
6.1.5.4 SpaceWire Command Register (CHx_DSM_CMDR) .......................................................................... 57
6.2 Data transfer via COMI....................................................................................................................................58
6.3 Data Transfer via HOCI...................................................................................................................................61
6.3.1 Special behaviour in case of SpaceWire link error ................................................................................... 62
7Signal Description...................................................................................................................................................64
8Electrical Specifications..........................................................................................................................................67
8.1 Absolute Maximum Ratings ..............................................................................................................................67
8.2 DC Electrical Characteristics...........................................................................................................................67
8.3 Power consumption...........................................................................................................................................68
8.4 PLL Filter .........................................................................................................................................................69
8.5 Power and Ground Guidelines .........................................................................................................................69
9Timing Parameters.................................................................................................................................................70
9.1 Clock Signals ....................................................................................................................................................70
9.2 Reset..................................................................................................................................................................72
9.3 Host Read..........................................................................................................................................................73
9.4 Host Write.........................................................................................................................................................75
9.5 COMI Read.......................................................................................................................................................77
9.6 COMI Write ......................................................................................................................................................78
9.7 COMI Arbitration .............................................................................................................................................79
9.8 CPUR, SES, Interrupt.......................................................................................................................................80
9.9 Links..................................................................................................................................................................81
9.10 Test Port (JTAG)...............................................................................................................................................82
10 Mechanical Data .....................................................................................................................................................84
10.1 Package Dimensions.........................................................................................................................................84
10.2 Pin Assignment .................................................................................................................................................85
11 Additional Informations.........................................................................................................................................87
11.1 Frequently Asked Questions .............................................................................................................................87
11.2 BSDL File for the SMCS332SpW......................................................................................................................90
12 Handling Empty Packets......................................................................................................................................110
12.1 Description .....................................................................................................................................................110
12.2 Workaround....................................................................................................................................................113
13 Simple Interprocessor Communication Protocol Specification ........................................................................114
13.1 Application Scenario.......................................................................................................................................114
13.2 Assumptions about the Environment...............................................................................................................115

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13.3 Service Specification.......................................................................................................................................115
13.3.1 Transport of data between two nodes...................................................................................................... 115
13.3.2 Execution of control commands.............................................................................................................. 116
13.3.2.1 Simple Control Commands ............................................................................................................. 116
13.3.2.2 Complex Control Commands.......................................................................................................... 117
13.4 Procedure Rules..............................................................................................................................................118
13.4.1 Acknowledgements................................................................................................................................. 118
13.4.2 Access to Command Signal Output Ports ............................................................................................... 119
13.4.3 Safety Critical Commands ...................................................................................................................... 119
13.4.4 Reset Commands .................................................................................................................................... 120
13.4.5 Shutdown Link Channel Operation / Restart Link Channel Operation................................................... 121
13.4.6 Read of Link Interface Status Register ................................................................................................... 121
13.5 Encoding (Format) of Transactions................................................................................................................122
13.5.1 Header and EOP Coding ......................................................................................................................... 122
13.5.2 Control Word Coding Specification........................................................................................................ 122
13.5.3 Link Interface Status Register Encoding................................................................................................. 124
13.5.4 Data Transfer Type Transactions ............................................................................................................ 125
13.5.5 Read Link Interface Status Register Transaction .................................................................................... 126
13.5.6 Enable Command Execution Transaction ............................................................................................... 127
13.5.7 Critical Simple Command Execution Transaction .................................................................................. 128
13.6 Glossary..........................................................................................................................................................129
14 Differences between the SMCS332SpW and the old SMCS332........................................................................130
14.1 Summary of changed/modified/added registers or register bits......................................................................130
14.2 Pin Modifications............................................................................................................................................131

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1Scope and Objectives
This document describes in detail the new SMCS332SpW. The SMCS332SpW provides an interface between
three SpaceWire links according to the SpaceWire Standard ECSS-E-50-12A and a data processing node like a
CPU.
1.1 List of applicable documents
Number Document
AD1 ECSS-E-50-12A
SpaceWire -Links, nodes,
routers and network
24 January 2003
AD2 SMCS332SpW_RS-01 SMCS332SpW
Requirements Specification
1.2 Reference Documents
The documents below have been used as support for establishing this document and contain background
information relating to the subjects addressed.
Number Document
RD1 Issue 2, 21.04.1999 SMCS332 User Manual

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1.3 List of Abbreviations
AD Applicable Document
API Application Programming Interface
ASIC Application Specific Integrated Circuit
CODEC COder / DECoder
COMI Communication Memory Interface
DPU Data Processing Unit
DSP Digital Signal Processor
EOP End Of Packet
EEP Error End Of Packet
ESC Escape
FCT Flow Control Token
FIFO First In First Out
FPGA Field Programmable Gate Array
GPIO General Purpose Input Output
JTAG Joint Testing Action Group
HOCI Host Control Interface
LVDS Low Voltage Differential Signalling
LSB Least Significant Bit
MSB Most Significant Bit
PCB Printed Circuit Board
PE Processing Element
PPU Protocol Processing Unit
PRCI Protocol Command Interface
SIC Simple Interprocessor Communication
SRAM Static Random Access Memory
SSRAM Synchronous Static Random Access Memory
SMCS Scalable Multichannel Communication Subsystem
TBC to be confirmed
TBD to be defined

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2Introduction
The SMCS332SpW provides an interface between 3 SpaceWire links according to the SpaceWire Standard ECSS-E-50-12A
specification and a data processing node consisting of a CPU and a communication data memory. The SMCS332SpW
provides HW supported execution of the major parts of the simple interprocessor communication protocol, particularly:
· transfer of data between two nodes of a multi-processor system with minimal host CPU intervention,
· execution of simple commands to provide basic features for system control functions,
· provision of fault tolerant features.
However, with disabling of features such as the protocol handling or with reduction of the transmit rate also low power usage
is supported.
SpaceWire
Receive
Transmit
Protocol
Channel1
Channel2
Channel3
COMI
HOCI
PRCI
JTAG
D/S RCV 1
D/S TRM 1
D/S RCV 2
D/S TRM 2
D/S TRM 3
D/S RCV 3
CMADR
CM_CONTROL
CMDATA
HADR
H_CONTROL
HDATA
HINTR
CPUR
SES
TEST
CLOCK
RESET
Figure 1: SMCS332SpW Block Diagram
Target applications are heterogeneous multi-processor systems supported by scalable interfaces including the little/big
endian byte swapping. The SMCS332SpW connects modules with different processors (e.g. ADSP21020, SHARC, ERC32,
TMS320C40). Any kind of network topology could be realized through the high speed point-to-point SpaceWire-links (see
chapter Applications in sectioon 2.8).

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2.1 Interfaces
The SMCS332SpW consists of the following blocks (See block diagram of the SMCS332SpW in Figure 1):
• 3 bidirectional SpaceWire [AD1] channels, all comprising the DS-link SpaceWire cell, receive and transmit
sections (each including FIFOs) and a protocol processing unit (PPU). Each channel allows full duplex
communication up to 200 Mbit/s in each direction. With protocol command execution a higher level of
communication is supported. Link disconnect detection and parity check at character level are performed. A
checksum generation for a check at packet level can be enabled.
The transmit rate is selectable between 1.25 and 200 Mbit/s. The start up transmit rate is 10 Mbit/s. For special
applications the data transmit rate can be programmed to values even below 10 Mbit/s; the lowest possible
SpaceWire transmit rate is 1.25 Mbit/s (the next values are 2.5 and 5 Mbit/s).
• Communication Memory Interface (COMI) performs autonomous accesses to the communication memory of the
module to store data received via the links or to read data to be transmitted via the links. The COMI consists of
individual memory address generators for the receive and transmit direction of every SpaceWire link channel. The
access to the memory is controlled via an arbitration unit providing a fair arbitration scheme. Two SMCS332SpW
can share one DPRAM without external arbitration logic.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type.
Operation in little or big endian mode is configurable through internal registers.
The COMI address bus is 16 bit wide allowing direct access of up to 64K words (32 bit) of the DPRAM. Two chip
select signals are provided to allow splitting of the 64k address space in two memory banks.
• Host Control Interface (HOCI) gives read and write access to the SMCS332SpW configuration registers and to the
SpaceWire channels for the controlling CPU. Viewed from the CPU, the interface behaves like a peripheral that
generates acknowledges to synchronize the data transfers and which is located somewhere in the CPU's address
space.
Packets can be transmitted or received directly via the HOCI. In this case the Communication Memory (DPRAM)
is not strictly needed. However, in this case the packet size should be limited to avoid frequent CPU interaction.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. The byte alignment can
be configured for little or big endian mode through an external pin.
Additionally the HOCI contains the interrupt signalling capability of the SMCS by providing an interrupt output,
the interrupt status register and interrupt mask register to the local CPU.
A special pin is provided to select between control of the SMCS332SpW by HOCI or by link. If control by link is
enabled, the host data bus functions as a 32-bit general purpose interface (GPIO).
• Protocol Command Interface (PRCI) that collects the decoded commands from all PPUs and forwards them to
external circuitry via 5 special pins.
• JTAG Test Interface that represents the boundary scan testing provisions specified by IEEE Standard 1149.1 of the
Joint Testing Action Group (JTAG). The SMCS' test access port and on-chip circuitry is fully compliant with the
IEEE 1149.1 specification. The test access port enables boundary scan testing of circuitry connected to the SMCS
I/O pins.

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2.2 Operation Modes
According to the different protocol formats expected for the operation of the SMCS332SpW, two major operation modes are
implemented into the SMCS332SpW. The operation modes are chosen individually for each link channel by setting the
respective configuration registers via the HOCI or via the link.
• Transparent Mode (default after reset): This mode allows complete transparent data transfer between two nodes
without performing any interpretation of the data bytes and without generating any acknowledges. It is completely
up to the host CPU to interpret the received data and to generate acknowledges if required.
The SMCS332SpW accepts EOP and EEP control tokens as packet delimiters and generates autonomously EOP or
no EOP (as configured) marker after each end of a transmission packet.
This mode also includes as a special sub mode:
• Wormhole routing: This mode allows hardware routing of packets by the SMCS332SpW.
• Simple Interprocessor Communication (SIC) Protocol Mode: This mode executes the simple interprocessor
communication protocol as described in chapter 13. The following capabilities of the protocol are implemented into
the SMCS332SpW:
• interpretation of the first 4 data characters as the header bytes of the protocol
• autonomous execution of the simple control commands as described in the protocol specification
• autonomous acknowledgement of received packets if configured
In transmit direction no interpretation of the data is performed. This means that for transmit packets, the four header
bytes must be generated by the host CPU and must be available as the first data read from the communication
memory. EOP control characters are automatically inserted by the SMCS332SpW if one configured transfer from
the communication memory has finished.
2.3 SMCS332SpW Control by SpaceWire link
A feature of the SMCS332SpW is the possibility to control the SMCS332SpW not only via HOCI but via one of the three
links. This allows to use the SMCS332SpW in systems without a local controller (µController, FPGA etc.). Since the HOCI
is no longer used in this operation mode, it is instead available as a set of general purpose I/O (GPIO) lines. The detailed
description of this operation mode is given in section 5.4.
2.4 Wormhole Routing
The SMCS332SpW introduces a wormhole routing function similar to the routing implemented in the SpaceWire Router.
Each of the three links and the SMCS332SpW itself can be assigned an eight bit address. When routing is enabled in the
SMCS332SpW, the first byte of a packet will be interpreted as the address destination byte, analyzed and removed from the
packet (header deletion). If this address matches one of the two other link addresses or the SMCS332SpW address assigned
previously, the packet will be automatically forwarded to this link or the FIFO of the SMCS332SpW. If the header byte does
not match a link address, the packet will be written to the internal FIFO as well and an error interrupt (maskable) will be
raised.

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2.5 PPU Functional Description
Since the Protocol Processing Unit (PPU) determines a major part of the SMCS332SpW functionality, the principal blocks of
the PPU and their function are described here. This functionality is provided for every SpaceWire channel of the
SMCS332SpW.
• Protocol Execution Unit: This unit serves as the main controller of the PPU block. It receives the character from the
SpaceWire cell and interprets (in protocol mode) the four header data characters received after an EOP control
character. If the address field matches the link channel address and the command field contains a valid command
then forwarding of data into the receive FIFO is enabled. If the command field contains a "simple control
command" then the execution request is forwarded to the command execution unit.
The protocol execution unit also enables forwarding of header data characters to the acknowledge generator and
provides an error signal in case of address mismatch, wrong commands or disabled safety critical "simple control
commands".
The protocol execution unit is disabled in "transparent" or “wormhole routing” operation mode.
• Receive, Transmit, Acknowledge: the transmit and receive FIFOs decouple the SpaceWire link related operations
from the SMCS332SpW related operations in all modes and such allows to keep the speed of the different units
even when the source or sink of data is temporarily blocked.
In the protocol mode a further FIFO (acknowledge FIFO) is used to decouple sending of acknowledges from
receiving new data when the transmit path is currently occupied by a running packet transmission.
• Command Execution Unit: This unit performs activating resp. deactivating of the CPU reset and the specific
external signals and provides the capability to reset one or all links inside the SMCS332SpW, all actions requested
by the decoded commands from the protocol execution unit.
The unit contains a register controlling the enable/disable state of safety critical commands which is set into the
'enable' state upon command request and which is reset after a safety critical command has been executed.
The CPU reset and the specific external signals are forwarded to the Protocol Command Interface (PRCI).
2.6 Fault Tolerance
The SpaceWire standard specifies low level checks as link disconnect, credit value, sequence and parity at token level. The
SMCS332SpW provides, through the Protocol Processing Unit, features to reset a link or all links inside the SMCS332SpW,
to reset the local CPU or to send special signals to the CPU commanded via the links.
Additionally it is possible to enable a checksum coder/decoder to have fault detection capabilities at packet level.
2.7 Software Support
The SMCS332SpW is supported by VSPWorks from Wind River, a commercially available distributed real-time kernel. It is
a multi-tasking as well as a multi-processor Operating System. The main goals are to enable programming at a higher level to
configure and to perform communication and to administer the tasks on a board with multiple processes running in parallel.
The VSPWorks kernel supports multiple processors and application specific chips, e.g. the SHARC, ADSP21020,
TMS320C40, SPARC ERC32 etc. Thus it is possible to run a heterogeneous multiprocessor system with a single Operating
System without consideration of the hardware platform.

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2.8 Application
The SMCS332SpW can be used for single board systems where standardised high speed interfaces are needed. Even "non-
intelligent" modules such as A/D-converter or sensor interfaces can be assembled with the SMCS332SpW because of the
"control by link" feature. The complete control of the SMCS332SpW can be done via link from a central controller-node.
The SMCS332SpW is a very high speed, scalable link-interface chip with fault tolerance features. The initial exploitation is
for use in multi-processor systems where the standardization or the high speed of the links is an important issue and where
reliability is a requirement. Further application examples are heterogeneous systems (as shown in Figure 2) or modules
without any communication features as special image compression chips, certain signal processors (ADSP21020, MC56000),
application specific programmable logic or mass memory.
Heterogeneous Systems. These systems are often used for applications where different kind of tasks are to be processed.
Figure 2 below shows an application with multiple processing modules using the SMCS332SpW for interprocessor
communication.
Figure 2: Multiprocessor System with SMCS332SpW link connections
2.9 SMCS332SpW connected with the old SMCS332
The new ECSS-E-50-12A SpaceWire standard, used by the SMCS332SpW and the IEEE-1355 standard used by the old
SMCS332 are compatible, however the old SMCS332 has a slightly different startup behavior, the SMCS332 must be
started first on a link connecting with the SMCS332SpW.

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3The SpaceWire link
The SpaceWire standard [AD1] defines a full duplex bit serial point to point link with a raw transmit rate of up to 400
Mbit/sec. The link consists of 2 signals in each direction, one for strobe and one for data. By coding the strobe that it only
changes level when the data does not, clock recovery and data synchronization can be achieved by XOR-ing of data and
strobe signals without having the need to run the strobe at very high frequencies. The Character level defines the data and
control characters used to manage the flow of data across a link. The exchange level of the protocol is used to implement
flow control which avoids overflow of the front end buffers. Also error detection is provided by implemented parity checks
during transmission and by timeout supervision in case of inter-connect failures.
The SpaceWire standard aims only to define a transport medium between two nodes and covers the protocol layers only up
to the packet level. This has two consequences:
• packets with address headers allow to use this link standard in networks using routers,
• since the standard does not define the data payload within the packets, an efficient transaction layer definition is
missing.
To compensate for these deficiencies of the SpaceWire specification, the SMCS332SpW implementations (the
SMCS332SpW and the SMCS116SpW) introduce an (optional) transaction layer extension to the SpaceWire protocol
standard. This high-level protocol extension supports applications in fault tolerant systems, heterogeneous architectures,
feature power saving modes and remote configuration of the communication controller and autonomous command execution.
With this flexible and powerful protocol, the SpaceWire link has many advantages over commonly used interface solutions
such as RS-485 etc.
3.1 Data/Strobe SpaceWire signals
The SpaceWire links use a protocol with two wires in each direction, one for data and one to carry a strobe signal and are
also referred to as data/strobe (DS-Links). Each DS pair carries characters and an encoded clock. The characters can be data
or control characters. The figure below shows the format of data and control characters on the data and strobe wires. Data
characters are 10 bits long and consist of a parity bit, a control flag which is set to 0 to indicate a data character and 8 bits of
data. Control characters are 4 bits long and consist of a parity bit, a control flag which is set to 1 to indicate a control
character, and 2 bits to indicate the type of control character. One of the four possible control characters is the escape code
ESC. The ESC code is used to form control codes. Two control codes are specified, the NULL code and the time code. The
NULL code is transmitted whenever a link is not sending data or control characters. The time code is used to distribute
system time over a SpaceWire network, which comprises a ESC control character followed by a single data character.
The DS-Link protocol ensures that only one of the two wires of the data strobe pair has an edge in each bit time. The levels
on the data wire give the data bits transmitted. The strobe signal changes whenever the data signal does not. These two
signals encode a clock together with the data bits, permitting asynchronous detection of the data at the receiving end. The
data and control characters are of different lengths, for this reason the parity bit in any characters covers the parity of the data
or control bits in the previous characters, and the control flag in the same character, as shown in the above figure. This
allows single bit errors in the character type flag to be detected. Odd parity checking is used. Thus the parity bit is set/unset
to ensure that the bits covered, inclusive of the parity bit (see below figure), always contain an odd number of 1’s. The
coding of the characters is shown in the table below To ensure the immediate detection of parity errors and to enable link
disconnection to be detected NULL code are sent in the absence of other tokens.

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Character Type Abbreviation Coding
Data character P0DDDDDDDD
control characters:
Flow control FCT P100
Normal End of Packet EOP P101
Error End of Packet EEP P110
Escape ESC P111
control codes:
Null NULL ESC + FCT
P1110100
Time code ESC + DATA
P11110DDDDDDDD
P = Parity bit
D = Data bit
3.2 Character level flow control
Character level flow control is performed in each SpaceWire module, and the additional flow control characters used are not
visible to the higher-level packet protocol. The character level flow control mechanism prevents a sender from overrunning
the input buffer of a receiving link. Each receiving link input contains a buffer for at least 8 normal-characters (16 normal-
characters of buffering is in fact provided). Normal-characters are data character and EOP/EEP. Whenever the link input has
sufficient buffering available to consume a further 8 normal-characters a FCT is transmitted on the associated link output,
and this FCT gives the sender permission to transmit of further 8 normal-characters. Once the sender has transmitted 8
normal-characters it waits until it receives another FCT before transmitting any more tokens. The provision of more than 8
normal-characters of buffering on each link input ensures that in practice the next FCT is received before the previous block
of 8 normal-characters has been fully transmitted, so the character level flow control does not restrict the maximum
bandwidth of the link.
For further information see [AD1]

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3.3 Link speeds
The SpaceWire links can support a range of communication speeds, which are programmed by writing to registers. At reset
all links are configured to run at the base speed of 10 Mbits/sec. Only the transmission speed of a link is programmed as
reception is asynchronous. This means that links running at different speeds can be connected, provided that each device is
capable of receiving at the speed of the connected transmitter. The transmission speeds of all of the links on a given device
are related to the maximum transmission rate programmed for the complete device. This maximum transmission rate is
programmed through the transmit bitrate base register TRS_CTRL described in section 4.2.1.2. This max. transmission
bitrate is divided down to obtain the transmission frequency for each link. The division factor can be programmed separately
for each link via the Channel Link SpaceWire Mode Register CH_x_DSM_MODR register described in section 4.2.2.1.
This arrangement allows each link to be run at different transmission speeds, as shown in the table below (shown for
minimum and maximum link speeds):
Max. Transmit Speed Link Speed Divider Link Speed [Mbit/s]
1 80
2 40
4 20
8 10
16 5
32 2,5
80
(TRS_CTRL = 0x08)
64 1,25 (min. Link speed)
1 200 (max. Link speed)
2 100
4 50
8 25
16 12,5
32 6,25
200
(TRS_CTRL = 0x14)
64 3,125
3.4 Errors on links
Link inputs can detect parity and disconnection conditions as errors. A single bit odd parity system will detect single bit
errors at the character level. The protocol to transmit NULL's in the absence of other characters enables disconnection of a
link to be detected. A disconnection error indicates that:
• the link has been physically disconnected;
• an error has occurred on the link or at the other end of the link, which may have then stopped transmitting.
The status bits in the CH_x_DSM_STAR registers flags that a parity, credit, sequence (ESC) and/or disconnect error has
occurred on the link. The errors can be detected independently. When a SpaceWire channel detects a parity, credit or
sequence error it halts its output. This is detected as a disconnect error at the other end of the link, causing this to halt its
output also. Detection of an error causes the link to be stopped. Thus, the disconnect behavior ensures that both ends are
stopped. Each end can then be restarted.

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The following procedure can be used to restart a link following an error (routing is assumed disabled):
1) Disconnect is detected (cause: error)
2) SMCS332SpW enters "exchange of silence"
if the corresponding interrupt mask bit is enabled, the SMCS332SpW HINTR* signal will be asserted.
3) The transmit section is reset by the SMCS332SpW after an error has occurred. Any currently on-going
transmit transfer via COMI is stopped.
The user can decide to read the receive-FIFO (if not empty) and then to reset the receive section or to reset
the receive section immediately without reading the receive-FIFO.
Resetting the receive section is done by setting and clearing bit1 in register CHx_CNTRL2.
If the protocol mode is used the protocol unit should be reset by setting and clearing bit2 in register
CHx_CNTRL2.
4) If the auto start bit (bit2, CHx_DSM_CMDR) is set, the link will start automatically after the "protocol of
silence", otherwise the user has to start the link by setting bit1 in CHx_DSM_CMDR.
The configuration registers are not affected by the disconnect error.
5) New transmit and receive transfers can be started.
3.5 SpaceWire state on start up
After power-on all LinkData and LinkStrobe signals are low, without clocks. Following power-on reset an initialization
sequence sets the speed of the link clock. The DS-Links are initially inactive. They are configured and started by
configuration writes. Their status can be determined by configuration reads.
Each link must be explicitly started by writing to the Start Transmit Node bit in its CHx_DSM_CMDR register. When a
SpaceWire link is started up it transmits NULL's. Data may not be transferred over the link until the receiving link has sent a
FCT, which it will do as soon as it has been started. In remote mode (control by link) however, the SMCS332SpW will send
characters as soon as it receives a NULL on one of the three links, the control link.
The receiving link receives and correctly decodes the characters. However, only when the receiving link has been explicitly
started by writing across the (internal) configuration bus can it send characters back. NULL's are then sent until data is
required.
A start up sequence between SpaceWire devices cannot be defined in general. The start up depends heavily on the system
(user) requirements and consequently on the procedure defined at system level to initialize the system or to recover from an
error.
No master-slave arrangement is necessary. The SpaceWire links are "hot plug" able., which means SpaceWire links can be
connected together at any time.
3.6 Link connections
SpaceWire links are TTL compatible and intended to be used in electrically quiet environments, between devices on a single
printed circuit board or between two boards via a backplane. Direct connection may be made between devices separated by a
distance of less than 200 millimeters. For longer distances a matched 100 ohm transmission line should be used together with
differential link transceivers (LVDS). The inputs and outputs have been designed to have minimum skew at the 1.5 V TTL
threshold. Buffers may be used for very long transmissions. If so, their overall propagation delay should be stable within the
skew tolerance of the link, although the absolute value of the delay is immaterial.
For more information see [AD1].

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4Register Set
This chapter describes the SMCS332SpW registers which can be read or written by the HOCI or via the link (in case the
"control by link" is enabled) to control SMCS332SpW operations. All SMCS332SpW control operations are performed by
writes or reads of the respective registers. Most of the control operations are obvious from the content of the registers.
General Conventions:
- bit 0 (D0) = least significant bit,
- bit 7 (D7) = most significant bit (or bit 15 or bit 31)
- Dx:0 means data bit x until bit 0.
4.1 Register address map
The addresses of the SMCS332SpW registers are directly mapped with pins HADR7 - 0. The tables below shows the
addresses of all the SMCS332SpW registers depending on the HOCI port width.
4.1.1 SMCS332SpW status and control registers
Port Width /
Address (hex)
32 16 8
Register Function Reset
Value
(hex)
Access
00 00 00 SICR SMCS332SpW Interface Control Register 00 r / w
01 01 01 TRS_CTRL Transmit-Speed-Base Register 0A r / w
02 02 02 RT_CTRL Routing Enable / Status Register 00 r / w
03 03 03 reserved 00
04 04
06
04
05
06
07
ISR Interrupt Status Register 04010040 ro
08 08
0A
08
09
0A
0B
IMR Interrupt Mask Register 00000000 r / w
0C 0C 0C COMI_CS0R COMI Chip Select 0 upper address boundary
Register
FF r / w
0D 0D 0D reserved 00
0E 0E 0E COMI_ACR COMI Arbitration Control Register 08 r / w
0F 0F 0F PRCIR PRCI Register 00 r / w

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4.1.2 SMCS332SpW channel 1 status and control registers
Port Width /
Address (hex)
32 16 8
Register Function Reset
Value
(hex)
Access
10 10 10 CH1_DSM_MODR channel 1 DSM mode Register 00 r / w
11 11 11 CH1_DSM_CMDR channel 1 DSM command Register 00 r / w
12 12 12 CH1_DSM_STAR channel 1 DSM status Register 00 r / w
13 13 13 CH1_DSM_TSTR channel 1 DSM test Register 00 r / w
14 14 14 CH1_ADDR channel 1 address Register 00 r / w
15 15 15 CH1_RT_ADDR channel 1 Route Address Register 00 r / w
16 16 16 CH1_PR_STAR channel 1 Protocol Status Register 04 r / w
17 17 17 reserved 00 ro
18 18 18 CH1_CNTRL1 channel 1 control Register 1 00 r / w
19 19 19 CH1_CNTRL2 channel 1 control Register 2 00 r / w
1A 1A 1A CH1_HTID channel 1 Header Transaction ID byte 00 ro
1B 1B 1B CH1_HCNTRL channel 1 Header control byte 00 ro
1C 1C 1C CH1_ESR1 channel 1 detailed error source register 1 00 r / w
1D 1D 1D CH1_ESR2 channel 1 detailed error source register 2 00 r / w
1E 1E 1E reserved 00 ro
1F 1F 1F CH1_COMICFG channel 1 COMI configuration register 00 r / w
20 20 20
21
CH1_TX_SAR channel 1 transmit Start Address Register 0000 r / w
22 22 22
23
CH1_TX_EAR channel 1 transmit End Address Register 0000 r / w
24 24 24
25
CH1_TX_CAR channel 1 transmit Current Address Register 0000 ro
26 26 26 CH1_TX_FIFO channel 1 transmit FIFO -- wo
27 27 27 CH1_TX_EOPB channel 1 transmit EOP Bit Register -- wo
28 28 28
29
CH1_RX_SAR channel 1 receive Start Address Register 0000 r / w
2A 2A 2A
2B
CH1_RX_EAR channel 1 receive End Address Register 0000 r / w
2C 2C 2C
2D
CH1_RX_CAR channel 1 receive Current Address Register 0000 ro
2E 2E 2E CH1_RX_FIFO channel 1 receive FIFO xxxxxxxx ro
2F 2F 2F CH1_STAR channel 1 Status Register 01 ro

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4.1.3 SMCS332SpW channel 2 status and control registers
Port Width /
Address (hex)
32 16 8
Register Function Reset
Value
(hex)
Access
30 30 30 CH2_DSM_MODR channel 2 DSM mode Register 00 r / w
31 31 31 CH2_DSM_CMDR channel 2 DSM command Register 00 r / w
32 32 32 CH2_DSM_STAR channel 2 DSM status Register 00 r / w
33 33 33 CH2_DSM_TSTR channel 2 DSM test Register 00 r / w
34 34 34 CH2_ADDR channel 2 address Register 00 r / w
35 35 35 CH2_RT_ADDR channel 2 Route Address Register 00 r / w
36 36 36 CH2_PR_STAR channel 2 Protocol Status Register 04 r / w
37 37 37 reserved 00 ro
38 38 38 CH2_CNTRL1 channel 2 control Register 1 00 r / w
39 39 39 CH2_CNTRL2 channel 2 control Register 2 00 r / w
3A 3A 3A CH2_HTID channel 2 Header Transaction ID byte 00 ro
3B 3B 3B CH2_HCNTRL channel 2 Header control byte 00 ro
3C 3C 3C CH2_ESR1 channel 2 detailed error source register 1 00 r / w
3D 3D 3D CH2_ESR2 channel 2 detailed error source register 2 00 r / w
3E 3E 3E reserved 00 ro
3F 3F 3F CH2_COMICFG channel 2 COMI configuration register 00 r / w
40 40 40
41
CH2_TX_SAR channel 2 transmit Start Address Register 00 r / w
42 42 42
43
CH2_TX_EAR channel 2 transmit End Address Register 00 r / w
44 44 44
45
CH2_TX_CAR channel 2 transmit Current Address Register 00 ro
46 46 46 CH2_TX_FIFO channel 2 transmit FIFO 00 wo
47 47 47 CH2_TX_EOPB channel 2 transmit EOP Bit Register 00 wo
48 48 48
49
CH2_RX_SAR channel 2 receive Start Address Register 00 r / w
4A 4A 4A
4B
CH2_RX_EAR channel 2 receive End Address Register 00 r / w
4C 4C 4C
4D
CH2_RX_CAR channel 2 receive Current Address Register 00 ro
4E 4E 4E CH2_RX_FIFO channel 2 receive FIFO xxxxxxxx ro
4F 4F 4F CH2_STAR channel 2 Status Register 01 ro