Embedded Artists LPC3250 User manual

LPC3250 Developer’s Kit - User‟s Guide
Copyright 2011 © Embedded Artists AB
EA2-USG-0902 Rev C
LPC3250 Developer’s Kit
User’s Guide
Get Up-and-Running Quickly and
Start Developing Your Applications On Day 1!

LPC3250 Developer’s Kit - User’s Guide
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Copyright 2011 © Embedded Artists AB
Embedded Artists AB
Davidshallsgatan 16
SE-211 45 Malmö
Sweden
[e-mail]
http://www.EmbeddedArtists.com
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LPC3250 Developer’s Kit - User’s Guide
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Copyright 2011 © Embedded Artists AB
Table of Contents
1Document Revision History 5
2Introduction 6
2.1 Features 6
2.2 ESD and Handling Precaution 7
2.3 LPC3250 Core Voltage Precaution 8
2.4 Other Products from Embedded Artists 8
2.4.1 Design and Production Services 8
2.4.2 OEM / Education / QuickStart Boards and Kits 8
3LPC3250 OEM Board Design 9
3.1 LPC3250 OEM Board Schematics 9
3.1.1 Schematic Page 2: Misc 9
3.1.2 Schematic Page 3: Powering 10
3.1.3 Schematic Page 4: External Memories 10
3.1.4 Schematic Page 5: Digital and Analog IO 11
3.1.5 Schematic Page 6: Ethernet Interface 11
3.1.6 Schematic Page 7: USB Interface 11
3.1.7 Schematic Page 8: Expansion Connector 12
3.2 Usage of CPU Pins 12
3.3 LPC3250 OEM Board Mechanical Dimensions and Connector 15
3.4 Things to note about the LPC3250 OEM Board 16
3.4.1 LPC3250 Adjustable Core Voltage 16
3.4.2 NAND FLASH Bad Block 16
3.4.3 Brand of Memory Chips 16
3.4.4 LPC3250 Peripherals 17
4QVGA Base Board Design 18
4.1 QVGA Base Board Schematics 18
4.2 Signal Mapping to QVGA Base Board 18
4.3 Jumpers 25
4.3.1 Default Jumper Positions 26
4.3.2 Illegal Jumper Combinations 26
4.4 Connectors 27
4.4.1 Mictor-38 ETM Connector 27
4.5 Important Components 28
4.6 USB Interface 29
4.6.1 USB Interface Note 29
5Getting Started 31
5.1 Initial Setup and Powering 31
5.2 FTDI USB Driver 31
5.2.1 USB Driver Behavior 34
5.3 Building Sample Applications 34

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5.3.1 Compile Using CodeSourcery 35
5.3.2 Compile Using Keil’s uVision 36
5.4 Booting 36
5.4.1 Kickstart Loader 36
5.4.2 Stage 1 Loader 36
5.4.3 Service Boot 42
6Further Information 45

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1 Document Revision History
Revision
Date
Description
A
2009-10-05
First official revision of document
B
2010-10-18
Added section (4.6) about USB device interface.
Updated rework instruction in section (4.6) for USB device interface
and R100.
Corrected section 5.4.3 about service boot jumpers.
Updated to rev 1.3 of OEM board schematic.
C
2011-10-26
Updated section 5.4.2 about how to store an application in NAND
flash and execute from external memory.
Prepared the document for public release

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Copyright 2011 © Embedded Artists AB
2 Introduction
Thank you for buying Embedded Artists‟ LPC3250 Developer’s Kit based on NXP‟s ARM926EJ-S
LPC3250 microcontroller.
This document is a User‟s Guide that describes the LPC3250 OEM Board and the QVGA Base Board
hardware design. It is the User‟s Manual for both the LPC3250 Developer’s Kit as well as for just the
LPC3250 OEM Board.
2.1 Features
Embedded Artists‟LPC3250 Developer‟s Kit with NXP‟s ARM926EJ-S LPC3250 microcontroller lets
you get up-and-running quickly. The small sized OEM board offers many unique features that ease
your learning curve and speed up your program development. The board has also been designed for
OEM applications with volume discount available. The features of the LPC3250 OEM Board are:
NXP's ARM926EJ-S LPC3250 microcontroller in BGA package, with 256 KByte internal RAM
External data memory: 64 MB DDR SDRAM (16-bit databus width)
External FLASH memories: 128 MB (1Gbit) NAND FLASH and 4 MB (32Mbit) SPI-NOR
FLASH
13.0000 MHz crystal for cpu
256 Kbit I2C E2PROM for storing non-volatile parameters
Buffered 16-bit data bus for external expansion
200 pos expansion connector (SODIMM-200 format, 0.6mm pitch)
Almost all LPC3250 pins available (except dedicated pins for on-board memories and
internal powering)
3.15-3.3V powering
Onboard reset generation
5 LEDs
Compact SODIMM size: 66 x 48 mm
Eight layer PCB design for compact design and best noise immunity
There is an accompanying QVGA Base Board that can be used for initial prototyping work. This base
board was originally developed for the LPC2478 processor and the associated LPC2478 OEM Board
in SODIMM format. Some interfaces, for example the CAN bus and ETM, do not exist on the LPC3250
and can hence not be used. The features of the QVGA Base Board are:
3.2 inch QVGA TFT color LCD with touch screen (4-wire version)
18-bit RGB interface to display
Connectors
200 pos, 0.6mm pitch SODIMM connector for the LPC3250 OEM Board
Expansion connector with all LCD controller signals, for custom displays
Expansion connector with all SODIMM interface signals
Ethernet connector (RJ45)
CAN interface & connector (cannot be used with the LPC3250 OEM Board)
MMC/SD interface & connector

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JTAG connector
Pads for ETM connector (cannot be used with the LPC3250 OEM Board)
Interfaces
USB OTG interface & connector
USB host interface & connector
Full modem RS232 on UART #1 (cannot be used on 32-bit databus cpu boards, but
RxD2/TxD2 can alternatively be connected to the RS232 interface)
Dual CAN interface & connector (cannot be used with the LPC3250 OEM Board)
IrDA transceiver interface
Power
Power supply, either via USB or external 9-15V DC
Other
5-key joystick
3-axis accelerometer
5 push-button keys (four via I2C and one on „gpi01/service_n‟(P2.10))
9 LEDs (8 via I2C and one on „gpi01/service_n‟(P2.10))
Analog input
USB-to-serial bridge on UART #5 (FT232R) and ISP functionality
Reset push-button and LED
250x150 mm in size
2.2 ESD and Handling Precaution
Please note that the LPC3250 OEM Board and QVGA Base Board come without any case/box and all
components are exposed for finger touches –and therefore extra attention must be paid to ESD
(Electro-Static Discharge) precaution.
Make it a habit always to first touch the metal surface of one of the USB or SC/MMC connectors
for a few seconds with both hands before touching any other parts of the boards. That way, you
will have the same electrical potential as the board and therefore minimize the risk for ESD damages.
Never touch directly on the LPC3250 OEM Board and in general as little as possible on the QVGA
Base Board. The push-buttons on the QVGA Base Board have grounded shields to minimize the effect
of ESD.
Note that Embedded Artists does not replace boards that have been damaged by ESD.
Do not exercise excessive pressure on the LCD glass area. That will damage the display. Also, do not
apply pressure on the two flex cables connecting the LCD. These are relatively sensitive and can be
damaged if too much pressure is applied to them.
Note that Embedded Artists does not replace boards where the LCD has been improperly
handled.

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2.3 LPC3250 Core Voltage Precaution
The core voltage for the LPC3250 can be dynamically changed, via I2C commands sent to the
LTC3447 voltage converter. The voltage can be set to up to 2V. Note that this is above the limits of the
core voltage. Read the LPC3250 datasheet for details (the absolute maximum core voltage allowed is
1.39V).
Note that Embedded Artists do not replace LPC3250 OEM boards where the core voltage
(VDD(CORE)) has been raised above 1.39 Volt. It is the user’s responsibility not to exceed the
voltage specification found in the datasheet.
2.4 Other Products from Embedded Artists
Embedded Artists have a broad range of LPC1xxx/LPC2xxx/LPC3xxx based boards that are very low
cost and developed for prototyping / development as well as for OEM applications. Modifications for
OEM applications can be done easily, even for modest production volumes. Contact Embedded Artists
for further information about design and production services.
2.4.1 Design and Production Services
Embedded Artists provide design services for custom designs, either completely new or modification to
existing boards. Specific peripherals and I/O can be added easily to different designs, for example,
communication interfaces, specific analog or digital I/O, and power supplies. Embedded Artists has a
broad, and long, experience in designing industrial electronics in general and with NXP‟s
LPC1xxx/LPC2xxx/LPC3xxx microcontroller family in specific. Our competence also includes wireless
and wired communication for embedded systems. For example IEEE802.11b/g (WLAN), Bluetooth™,
ZigBee™, ISM RF, Ethernet, CAN, RS485, and Fieldbuses.
2.4.2 OEM / Education / QuickStart Boards and Kits
Visit Embedded Artists‟ home page, www.EmbeddedArtists.com, for information about other OEM /
Education / QuickStart boards / kits or contact your local distributor.

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3 LPC3250 OEM Board Design
Please read the LPC3250 OEM Board datasheet and associated schematic for information about the
board. Some additional information about the LPC3250 OEM Board is presented below.
3.1 LPC3250 OEM Board Schematics
3.1.1 Schematic Page 2: Misc
3.1.1.1 Crystals
The microprocessor crystal frequency is 13.0000 MHz, which is the recommended frequency from
NXP. An internal PLL can create many other frequencies from this, like 208 MHz and 266 MHz.
The LPC3250 has an internal real-time clock (RTC) block that can be used to provide real-time and
alarm function. A 32.768 kHz crystal gives the base frequency for the RTC. The RTC block can be
powered via a separate supply (for example from a battery or high-capacity capacitor). The 32.768 kHz
can also be used as main oscillator via a PLL: 32.768 kHz x 397 = 13.009 MHz.
Note that the clocking structure is different from the LPC2xxx family. It is a more complex
structure but also much more versatile and flexible. There is no shortcut but to read the
LPC3250 User’s Manual in detail to understand the options and settings.
3.1.1.2 Booting
The LPC3250 starts executing from an on-chip ROM, containing the bootloader. Note that the
LPC3250 does not contain any on-chip FLASH memory. Program code must be loaded from an
external source into the on-chip SRAM.
The default boot is from an external memory (see LPC3250 User‟s Manual for details). Program code
is typically stored in NAND or SPI-NOR flash.
By pulling pin GPI_01/SERVICE_N low, UART boot mode is activated. This is a method for
downloading code from the PC, for example for programming the bootloader for the first time. Note that
pin GPI_01/SERVICE_N can be pulled low by pressing the “P2.10” key on the QVGA Base Board.
3.1.1.3 JTAG interface
The JTAG interface is a standard ARM-compatible JTAG interface.
3.1.1.4 SPI NOR FLASH
There is a 32Mbit (4 MByte) NOR flash connected to the SPI bus. Embedded Artists can choose to
mount, either S25FL032P from Spansion, AT45DB321 from Atmel, or other, on the board depending
on component availability at the time of production. Mounted chips will be supported by the LPC3250
bootloader. However, commands used to program the memory differ. Chip id should always be read
out to determine exact type mounted.
3.1.1.5 Reset Generation
The reset generation is handled by a standard voltage supervisor chip, CAT811R from Catalyst
Semiconductor. The reset signal will be held active (i.e., low) until the supply voltages, +3.3V, is within
margins (above 2.63V). The reset duration is typically 200 mS (consult the CAT811R datasheet for
exact details). The output reset signal is push/pull output that is converted to an open-collector / open-
drain output via the 74LVC1G125 buffer. An external reset source can pull the reset signal low (with an
open-collector/open-drain output). The RESET_N input on the LPC3250 has a 1.2V voltage range
(voltage domain: VDD_RTC). A 74LVC1G125 buffer makes sure this voltage range is not exceeded by
the external signal RESET_IN (which has 3.3V range).

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3.1.1.6 I2C E2PROM
There is a 256 kbit E2PROM accessible via the I2C interface (I2C1). The LPC3250 has two on-chip I2C
communication channels (I2C1 and I2C2). More peripheral units are easily connected to the two-wire
I2C bus, just as long as the addresses do not collide. The address of the 256kbit E2PROM is 0xA0,
which is also indicated in the schematic.
There are 2.2 kohm pull-up resistors (pull-ups are always needed on I2C busses) on the board on both
I2C channels.
3.1.2 Schematic Page 3: Powering
3.1.2.1 1.2V and 1.8V Fixed Voltages
The LPC3250 requires three fixed voltages; 1.2V for the core, 1.8V for the memory interface and 3.15-
3.3V for the rest of the i/o interfaces. The 1.2V and 1.8V voltages are generated by two LM3671MF
step-down switching regulators from National Semiconductor. These regulators are capable of
generating 600mA, which by far exceed the needed current by the LPC3250 and other components on
the LPC3250 OEM Board. The 3.15-3.3V voltage is the input voltage to the LPC3250 OEM Board, see
below.
The Real-time clock also needs a 1.2V power, which is generated by a LDO (MIC5232).
3.1.2.2 1.2V Adjustable Core Voltage
The core 1.2V voltage is adjustable and is generated by the step down switching regulator LTC3447
from Linear Technologies. This regulator is capable of generating 600mA, which also by far exceed the
needed current by the LPC3250. The adjustment is done via an I2C channel, I2C1 in the LPC3250
case. The core voltage can be adjusted as a power save feature. By lowering the voltage (down to
0.9V), the total power consumption can be lowered but the clock frequency of the core must then also
be lowered. This is a trade-off that is important for hand held/portable equipment. Note that it is the
user’s responsibility not to program the LTC3447 to generate too high core voltage, which is
possible. The LTC3447 can generate voltages up to 2V, which by far exceed the limits for the
LPC3250.
See the LPC3250 datasheet for exact details about voltage ranges, but it is in the region of 1.1-1.39V.
Also see the LTC3447 datasheet for details about how to adjust the voltage (it is a write-only register).
The I2C address for the LTC3447 is indicated in the schematic.
Note that a core voltage of 1.35V should be programmed when working with the external DDR
SDRAM.
3.1.2.3 Input Voltage
The input voltage to the LPC3250 OEM Board is given by the requirements of the LPC3250. The
recommended input voltage range is 3.15V to 3.3V. The input supply must be stable but there are no
special needs for bulk capacitors close to the power pins on the expansion connectors. The needed
capacitors are placed close to the switched step down switching regulators on the LPC3250 OEM
Board.
Note that the LPC3250 OEM Board is sensitive to input noise on the input voltage. The peak-to-peak
noise should be below 10mV. A linear regulator to feed the input voltage is strongly recommended.
3.1.3 Schematic Page 4: External Memories
Page 4 of the schematic contains the external memory interface and the external memories. The
memory interface uses a 16-bit databus and operates at 1.8V level, which minimizes power
consumption.

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3.1.3.1 DDR SDRAM
A 512 MBit (64 MByte) Mobile DDR SDRAM is used (MT46H32M16LF from Micron). The chip is
powered by 1.8V and is organized as 32Mbit x16, i.e. it has 16-bit databus width. The chip is
connected to EMC_DYCS0_N (memory bank #0 for dynamic RAM) at address range 0x8000 0000 –
0x9FFF FFFF.
Note that memory bank #1 for dynamic RAM is not available (i.e., signal EMC_DYCS1_N is not used).
3.1.3.2 NAND Flash
A 1 Gbit (128 MByte) NAND flash is used (K9F1G08U0A-P from Samsung). The chip is powered by
3.3V and has 8-bit databus width. The NAND flash builds on a single-level cell (SLC) technology and
has a page size of 2112 bytes (2,048 + 64 bytes). Note that the chip is not directly accessible via the
memory bus. Instead, all accesses must be done via the on-chip NAND flash controller of the
LPC3250.
3.1.3.3 Buffers to External Interface
The LPC3250 memory interface is available on the expansion connector. The data bus width is 16-bits
on the external interface. The relevant signals are buffered. The following four static memory regions
are available for external access:
External static bank #0 (0xE000 0000 –0xE0FF FFFF)
16-bit databus width and 16MByte in size.
External static bank #1 (0xE100 0000 –0xE1FF FFFF)
16-bit databus width and 16MByte in size.
External static bank #2 (0xE200 0000 –0xE2FF FFFF)
16-bit databus width and 16MByte in size.
External static bank #3 (0xE300 0000 –0xE3FF FFFF)
16-bit databus width and 16MByte in size.
By default (R44 = 0 ohm, R43 not mounted), signal N_ABUF_EN is pulled low and the two buffers for
address and control signals (U13 and U14) are enabled and act as output (from the LPC3250 OEM
Board).
The buffered version of the LPC3250 signal OE controls the direction of the data bus buffer (U15).
During read operations the buffer acts as an input and during write operations it acts as an output. The
data bus buffer is controlled by the signals BLS0 and BLS1, each controlling lower and upper bytes of
the 16-bit databus. These signals are active when accessing the external static memory regions.
The buffers are dual voltage buffers and act as level translators between the internal 1.8V signal levels
and the external levels. Connect the external bus voltage to VDD_EXT. See the datasheet of
74AVCA164245 for exact details about voltage range. Normally 3.3V powering is used on the external
side.
3.1.4 Schematic Page 5: Digital and Analog IO
Page 5 of the schematic contains all digital and analog signals plus three LEDs controlled by signals
P2.10 - P2.12.
3.1.5 Schematic Page 6: Ethernet Interface
An external PHY (DP83848 from National Semiconductor) implements a 100/10Mbps Ethernet
interface. The external PHY is connected to the Ethernet MAC on the LPC3250 via the RMII interface.
3.1.6 Schematic Page 7: USB Interface
There is a USB 2.0 (OTG, Host, Device) interface on the LPC3250. An external PHY (ISP1301) is
needed for the cpu.

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3.1.7 Schematic Page 8: Expansion Connector
The LPC3250 OEM Board integrates the core part of a typical LPC3250 board design with a
reasonable large amount of external memories. All relevant signals of LPC3250 are available on the
200 pos, 0.6mm pitch expansion connector (SODIMM-200 format). See the next section for a detailed
list of available pins.
3.2 Usage of CPU Pins
Almost all pins of the LPC3250 are directly available on the expansion connectors. Only in a few cases
pins are used for dedicated functionality like (dynamic) memory control signals, chip select signals and
power supply. Such pins are not available on the expansion connector. The table below lists all pins
and their possible restrictions.
Pin
Available on expansion connector
ADIN0 (TS_XM)
ADIN1 (TS_YM)
ADIN2 (TS_AUX_IN)
TS_XOUT
TS_YOUT
Yes
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
Yes, but I2C-E2PROM (U5 –24LC256) and
core voltage generator (U7, LTC3447)
connected to I2C1 pins.
Note that these signals have 2.2K pull-up
resistors.
SPI1_CLK / SCK0
SPI1_DATIO / MOSI0 / MCFB2
SPI1_DATIN / MISO0 / GPI_25 / MCFB1
GPIO_05 / SSEL0 / MCFB0
Yes, but note that SPI NOR flash is
connected to these signals.
HIGHCORE / LCDVD[17]
ONSW
Yes
Note that HIGHCORE signal can control
adjustable core voltage of R28 mounted
(normally not mounted).
I2S1TX_CLK / MAT3.0
I2S1TX_SDA / MAT3.1
I2S1TX_WS / CAP3.0
MS_BS / MAT2.1
MS_DIO0 / MAT0.0
MS_DIO1 / MAT0.1
MS_DIO2 / MAT0.2
MS_DIO3 / MAT0.3
MS_SCLK / MAT2.0
P0.0 / I2S1RX_CLK
P0.1 / I2S1RX_WS
P0.2 / I2S0RX_SDA / LCDVD[4]
P0.3 / I2S0RX_CLK / LCDVD[5]
P0.4 / I2S0RX_WS / LCDVD[6]
P0.5 / I2S0TX_SDA / LCDVD[7]
P0.6 / I2S0TX_CLK / LCDVD[12]
P0.7 / I2S0TX_WS / LCDVD[13]
PWM_OUT1 / LCDVD[16]
PWM_OUT2 / LCDVD[19]
SPI2_CLK / SCK1 / LCDVD[23]
SPI2_DATIN / MISO1 / LCDVD[21] / GPI_27
Yes
Note:
Pull-up on GPI_01/SERVICE_N
GPO_01 and GPO_14 controls
LED1/LED2
GPI_03 has pull-down resistor
GPI_05 has pull-down resistor
GPI_28 has pull-up resistor
U7_HCTS/CAP0.1/LCDCLKIN/
GPI_22 has pull-up resistor
GPO_19 controls NAND write protect
signal

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SPI2_DATIO / MOSI1 / LCDVD[20]
SYSCLKEN / LCDVD[15]
TST_CLK2
U1_RX / CAP1.0 / GPI_15
U1_TX
U2_HCTS / U3_CTS / GPI_16
U2_RX / U3_DSR / GPI_17
U2_TX / U3_DTR
U3_RX / GPI_18
U3_TX
U5_RX / GPI_20
U5_TX
U6_IRRX / GPI_21
U6_IRTX
U7_HCTS / CAP0.1 / LCDCLKIN / GPI_22
U7_RX / CAP0.0 / LCDVD[10] / GPI_23
U7_TX / MAT1.1 / LCDVD[11]
GPI_00 / I2S1RX_SDA
GPI_01 / SERVICE_N
GPI_02 / CAP2.0 / ENET_RXD3
GPI_03
GPI_04 / SPI1_BUSY
GPI_05 / U3_DC
GPI_06 / HSTIM_CAP / ENET_RXD2
GPI_07 / CAP4.0 / MCABORT
GPI_08 / KEY_COL6 / SPI2_BUSY / ENET_RX_DV
GPI_09 / KEY_COL7 / ENET_COL
GPI_19 / U4_RX
GPI_28 / U3_RI
GPIO_00
GPIO_01
GPIO_04 / SSEL1 / LCDVD[22]
GPO_00 / TST_CLK1
GPO_01
GPO_02 / MAT1.0 / LCDVD[0]
GPO_03 / LCDVD[1]
GPO_04
GPO_05
GPO_06 / LCDVD[18]
GPO_07 / LCDVD[2]
GPO_08 / LCDVD[8]
GPO_09 / LCDVD[9]
GPO_10 / MC2B / LCDPWR
GPO_11
GPO_12 / MC2A / LCDLE
GPO_13 / MC1B / LCDDCLK
GPO_14
GPO_15 / MC1A / LCDFP
GPO_16 / MC0B / LCDENAB / LCDM
GPO_17
GPO_18 / MC0A / LCDLP
GPO_19
GPO_20
GPO_21 / U4_TX / LCDVD[3]
GPO_22 / U7_HRTS / LCDVD[14]
GPO_23 / U2_HRTS / U3_RTS
EMC_D19/P2.0
EMC_D20/P2.1
EMC_D21/P2.2
Yes
Note that signals can only be P2 signals, not

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EMC_D22/P2.3
EMC_D23/P2.4
EMC_D24/P2.5
EMC_D25/P2.6
EMC_D26/P2.7
EMC_D27/P2.8
EMC_D28/P2.9
EMC_D29/P2.10
EMC_D30/P2.11
EMC_D31/P2.12
EMC databus.
P2.10 controls LED3
P2.11 controls LED4
P2.12 controls LED5
USB_ATX_INT_N
USB_DAT_VP / U5_RX
USB_I2C_SCL
USB_I2C_SDA
USB_OE_TP_N
USB_SE0_ VM / U5_TX
No, connected to on-board USB transceiver,
ISP1301
KEY_COL1 / ENET_RX_CLK / ENET_REF_CLK
KEY_COL2 / ENET_RX_ER
KEY_COL3 / ENET_CRS
KEY_COL4 / ENET_RXD0
KEY_COL5 / ENET_RXD1
KEY_ROW3 / ENET_TX_EN
KEY_ROW4 / ENET_TXD0
KEY_ROW5 / ENET_TXD1
GPIO_02 / KEY_ROW6 / ENET_MDC
GPIO_03 / KEY_ROW7 / ENET_MDIO
No, connected to on-board Ethernet PHY,
DP83848
EMC_A00 –EMC_A23
Yes, but only available via the address bus
buffer
EMC_D00 –EMC_D15
Yes, but only available via the data bus buffer
EMC_BLS0
EMC_BLS1
EMC_CS0_N
EMC_CS1_N
EMC_CS2_N
EMC_CS3_N
EMC_OE_N
EMC_WR_N
Yes, but only available via the buffer
FLASH_ALE
FLASH_CE_N
FLASH_IO00 –FLASH_IO07
FLASH_RD_N
FLASH_RDY
FLASH_WR_N
No, used for on-board NAND flash memory.
EMC_CAS_N
EMC_CKE0
EMC_CLK
EMC_DQM0
EMC_DQM1
EMC_DYCS0_N
EMC_RAS_N
EMC_D16/EMC_DQS0
EMC_D17/EMC_DQS1
EMC_D18/EMC_CLK_N
No, used for on-board DDR SDRAM.

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EMC_BLS2
EMC_BLS3
EMC_CKE1
EMC_CLKIN
EMC_DQM2
EMC_DQM3
EMC_DYCS1_N
No. These signals are not used and not
available.
KEY_COL0 / ENET_TX_CLK
KEY_ROW0 / ENET_TX_ER
KEY_ROW1 / ENET_TXD2
KEY_ROW2 / ENET_TXD3
No. These signals are not used and not
available.
Note that three (of four) signals can become
available if 0 ohm resistors are mounted:
KEYROW0, mount R93
KEYROW1, mount R94
KEYCOL0, mount R91
JTAG signals
Yes
RESET_N
RESOUT_N
Yes
Note pull-up resistor on RESET_IN and
internal open-drain driving of RESET_IN
RTCX_IN
RTCX_OUT
SYSX_IN
SYSX_OUT
No, directly connected to on-board crystals
All VDD and VSS pins
No, not directly accessible, but ground is
available and 3.15-3.3V input voltage
PLL397_LOOP
No, internal on-board connection to signal.
The QVGA Base Board illustrates how to typically connect external interfaces (like USB, external
memory devices, etc) to the LPC3250 OEM Board. Study this schematic (also found in this document)
for details.
3.3 LPC3250 OEM Board Mechanical Dimensions and Connector
Figure 1 below contains a drawing of the board that includes mechanical measures. See SODIMM-200
standard for exact measures. 1.8V keying is used (SODIMM-200 boards are either 1.8V or 2.5V
keyed).

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Figure 1 –LPC3152 OEM Board Mechanical Dimensions
The SODIMM-200 format is a standard and there are many connectors that are suitable from many
different manufactures. The many sources also keep the connector cost very low. Note that the
connector should be 1.8V keyed.
One suitable connector is 0-1473005-4 from Tyco/AMP. Basically any SODIMM, DDR2, 200pos, 1.8V,
right-angled connector will do.
3.4 Things to note about the LPC3250 OEM Board
3.4.1 LPC3250 Adjustable Core Voltage
The core voltage for the LPC3250 is adjustable via I2C commands sent to the LTC3447 voltage
converter. The core voltage should always be increased to 1.35 volt in order for external mobile DDR
SDRAM to function properly. Initialization code that increase the adjustable core voltage to 1.35V can
be downloaded from Embedded Artists support pages.
Note that it is the user’s responsibility not to program the LTC3447 to generate too high core
voltage, which is possible. The LTC3447 can generate voltages up to 2V, which by far exceed the
limits for the LPC3250.
3.4.2 NAND FLASH Bad Block
The NAND Flash is the K9F1G08U0A from Samsung and has 1 GBit capacity. The chip may include
invalid blocks when shipped from factory. A maximum of 20 invalid blocks may exist initially, i.e., 1004-
1024 valid blocks. Additional invalid blocks may develop while being used. Invalid blocks are defined
as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. More
information about appropriate management of invalid blocks can be found in technical notes and
datasheet from Samsung.
3.4.3 Brand of Memory Chips
Note that there is no guarantee for a certain brand or version of memory chips; SPI-NOR flash, parallel
NAND flash and mobile DDR SDRAM. The lifetime of memory chips is limited and availability can also
be limited from time to time. Embedded Artists make every effort to mount the original design chip on
the board. In case that is impossible a compatible chip will instead be mounted without any prior
notice. There can be small programming differences between mounted brands. The application
66 mm
48 mm
1.8V keying of SODIMM board

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program shall always read the chip id of flash devices to make certain which chip is actually mounted
on the board.
The support page contains datasheets to the different memory devices and information about mounted
devices on different board versions.
3.4.4 LPC3250 Peripherals
The key scan interface peripheral cannot be used with the LPC3250 OEM Board because the Ethernet
interface is active.

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4 QVGA Base Board Design
Please read the QVGA Base Board schematic for information about the board. Some additional
information about the QVGA Base Board is presented below.
4.1 QVGA Base Board Schematics
The QVGA Base Board contains a number of interfaces and connectors to the LPC3250 OEM Board.
The design can be viewed as a reference schematic for custom designs around the LPC3250 OEM
Board.
4.2 Signal Mapping to QVGA Base Board
The QVGA Base Board was originally developed for the LPC2478 processor and the associated
LPC2478 OEM Board in SODIMM format. The silk screen on the base board therefore reflects
the LPC2478 signal names.
The table below lists differences between the LPC3250 and LPC2478 OEM Boards in their SODIMM
interface. The table also lists what functionality that is connected to the different signals.
SODIMM
pin
number
LPC2478 OEM
Board
LPC3250 OEM
Board
QVGA Base Board
Comment
1
ETH_TXP
ETH_TXP
Ethernet i/f
2
ETH_RXP
ETH_RXP
Ethernet i/f
3
ETH_TXN
ETH_TXN
Ethernet i/f
4
ETH_RXN
ETH_RXN
Ethernet i/f
5
ETH_VDD
ETH_VDD
Ethernet i/f
6
ETH_GND
ETH_GND
Ethernet i/f
7
ETH_LED1
ETH_LED1
Ethernet i/f
8
ETH_LED2
ETH_LED2
Ethernet i/f
9
VBAT_IN
VBAT_IN
0.33F backup cap on vbat signal
10
ALARM
ONSW
Connected to alarm-LED (active high)
ONSW functionality
not demonstrated/
supported on
QVGA Base Board.
11
RESET_IN
RESET_IN
Connects to RESET push-button and USB-to-
serial bridge (for automatic ISP functionality)
12
RESET_OUT
RESET_OUT
Connects to RESET LED indicator.
Used to reset PCA9532 and QVGA display.
13
ETH_PHY_PD
ETH_PHY_PD
Part of Ethernet i/f, can be connected to
SODIMM pin 118
14
JTAG_DBGEN
JTAG_DBGEN
Connected to „JTAG Enable‟ jumper
15
JTAG_TCK
JTAG_TCK
Connected to standard 20 pos (2x10 pin)
JTAG connector
16
JTAG_RTCK
JTAG_RTCK
Connected to standard 20 pos (2x10 pin)
JTAG connector
17
JTAG_NTRST
JTAG_NTRST
Connected to standard 20 pos (2x10 pin)
JTAG connector
18
JTAG_TMS
JTAG_TMS
Connected to standard 20 pos (2x10 pin)

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JTAG connector
19
JTAG_TDI
JTAG_TDI
Connected to standard 20 pos (2x10 pin)
JTAG connector
20
JTAG_TDO
JTAG_TDO
Connected to standard 20 pos (2x10 pin)
JTAG connector
21
V3A
VDDA
Positive reference for trimming potentiometer
22
VREF
NC (can be VCCA)
Can be connected VDDA(V3A)
23
VSSA
VSSA
Negative reference for trimming potentiometer
24
GND
GND
GND
25
P2.0
GPO_10
LCDPWR signal, power enable for QVGA
display. Also connects to ETM pads, if
connector mounted.
ETM cannot be
used
26
P2.1
GPO_12
LCDLE signal. Not used by design. Also
connects to ETM pads, if connector mounted.
ETM cannot be
used
27
P2.2
GPO_13
LCDDCLK signal, dot clock for QVGA display.
Also connects to ETM pads, if connector
mounted.
ETM cannot be
used
28
P2.3
GPO_15
LCDFP signal, vsync for QVGA display. Also
connects to ETM pads, if connector mounted.
ETM cannot be
used
29
P2.4
GPO_16
LCDENAB signal, data enable for QVGA
display. Also connects to ETM pads, if
connector mounted.
ETM cannot be
used
30
P2.5
GPO_18
LCDLP signal, hsync for QVGA display. Also
connects to ETM pads, if connector mounted.
ETM cannot be
used
31
P2.6
P0.2
LCD databit 4. Also connects to ETM pads, if
connector mounted.
ETM cannot be
used
32
P2.7
P0.3
LCD databit 5. Also connects to ETM pads, if
connector mounted.
ETM cannot be
used
33
P2.8
P0.4
LCD databit 6. Also connects to ETM pads, if
connector mounted.
ETM cannot be
used
34
P2.9
P0.5
LCD databit 7. Also connects to ETM pads, if
connector mounted.
ETM cannot be
used
35
P2.10
GPI_01
Connected to push-button (for enabling
bootloader during reset or EINT0 input). Also
connects to LED (active low).
Connects to USB-to-serial bridge (for
automatic ISP functionality)
Enable UART
booting by pulling
signal low at reset
36
P2.11
U7_HCTS
LCDCLKIN, an external clock signal can be
feed to this pin.
37
VCC
VCC
38
GND
GND
39
VCC
VCC
40
GND
GND
41
P0.29-USBA-DP
NC (can be
KEYROW0)
Connects to USB device/OTG interface
USB Device/OTG
i/f not used
42
P0.31-USBB-DP
USB_CONN_DP
Connects to USB host interface
USB Host interface
is connected to the
LPC3250
43
P0.30-USBA-DM
NC (can be
Connects to USB device/OTG interface
USB Device/OTG

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KEYROW1)
i/f not used
44
USBB-DM
USB_CONN_DN
Connects to USB host interface
USB Host interface
is connected to the
LPC3250
45
P2.12
GPO_06
LCD databit 18
46
P2.13
PWMOUT2
LCD databit 19
47
P0.0
U6_IRTX
Can be connected to RD1 for CAN channel
#1, can also connect to IrDA transceiver
CAN interface
cannot be used by
the LPC3250.
IrDA can be used
48
P0.1
U6_IRRX
Can be connected to TD1 for CAN channel
#1, can also connect to IrDA transceiver
CAN interface
cannot be used by
the LPC3250.
IrDA can be used
49
P0.2
U5_TX
Can be connected to USB-to-serial bridge
(TxD on UART #5. Note that the silk screen
text says UART#0)
Possible to boot
over UART#5
50
P0.3
U5_RX
Can be connected to USB-to-serial bridge
(RxD on UART #5. Note that the silk screen
text says UART#0)
Possible to boot
over UART#5
51
P0.4
GPO_02
LCD databit 0, can also be connected to RD2
for CAN channel #2
CAN i/f cannot be
used
52
P0.5
GPO_03
LCD databit 1, can also be connected to TD2
for CAN channel #2
CAN i/f cannot be
used
53
P0.6
GPO_08
LCD databit 8
54
P0.7
GPO_09
LCD databit 9
55
P0.8
PWMOUT1
LCD databit 16
56
P0.9
HICORE
LCD databit 17
57
P0.10
U1_TX
Can be connected to RS232 interface (TxD)
58
P0.11
U1_RX
Can be connected to RS232 interface (RxD)
59
P0.12
USB_VBUS_CTRL
Can be connected to enable USB-host power
switch
60
P0.13
GPO_17
Can be connected to LED (active low) for
USB-host indicator
61
P0.14
GPO_20
Can be connected to USB-device enable-
device signal
62
P0.15
SPI1_CLK
QVGA display and Touch screen serial
interface (SPI-SCK)
63
P0.16
GPO_04
QVGA display serial interface (SSEL)
64
P0.17
SPI1_DATIN
QVGA display and Touch screen serial
interface (SPI-MISO)
65
P0.18
SPI1_DATIO
QVGA display and Touch screen serial
interface (SPI-MOSI)
66
P0.19
GPO_05
QVGA display serial interface (command/data
select)
67
P0.20
GPO_11
Touch screen serial interface (SSEL)
68
P0.21
TS_XP
No special usage on QVGA Base Board
69
P0.22
TS_YP
No special usage on QVGA Base Board