Hitachi H8S/2199 User manual

Hitachi Single-Chip Microcomputer
H8S/2199 Series
H8S/2199
HD6432199
H8S/2198
HD6432198
H8S/2197
HD6432197
H8S/2196
HD6432196
H8S/2199F-ZTAT™
HD64F2199
Hardware Manual
ADE-602-191
Rev 1.0
2/15/00
Hitachi, Ltd.

Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.

Rev. 1.0, 02/00, page i of 19
Contents
Section 1 Overview........................................................................................................... 1
1.1 Overview........................................................................................................................... 1
1.2 Internal Block Diagram..................................................................................................... 7
1.3 Pin Arrangement and Functions........................................................................................ 8
1.3.1 Pin Arrangement............................................................................................... 8
1.3.2 Pin Functions.................................................................................................... 9
Section 2 CPU.................................................................................................................... 17
2.1 Overview........................................................................................................................... 17
2.1.1 Features............................................................................................................. 17
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU............................... 18
2.1.3 Differences from H8/300 CPU......................................................................... 18
2.1.4 Differences from H8/300H CPU ...................................................................... 19
2.2 CPU Operating Modes...................................................................................................... 20
2.3 Address Space................................................................................................................... 25
2.4 Register Configuration...................................................................................................... 26
2.4.1 Overview .......................................................................................................... 26
2.4.2 General Registers.............................................................................................. 27
2.4.3 Control Registers.............................................................................................. 28
2.4.4 Initial Register Values ...................................................................................... 29
2.5 Data Formats..................................................................................................................... 30
2.5.1 General Register Data Formats......................................................................... 30
2.5.2 Memory Data Formats...................................................................................... 32
2.6 Instruction Set................................................................................................................... 33
2.6.1 Overview .......................................................................................................... 33
2.6.2 Instructions and Addressing Modes.................................................................. 34
2.6.3 Table of Instructions Classified by Function.................................................... 35
2.6.4 Basic Instruction Formats................................................................................. 45
2.6.5 Notes on Use of Bit-Manipulation Instructions................................................ 46
2.7 Addressing Modes and Effective Address Calculation..................................................... 47
2.7.1 Addressing Mode.............................................................................................. 47
2.7.2 Effective Address Calculation.......................................................................... 50
2.8 Processing States............................................................................................................... 54
2.8.1 Overview .......................................................................................................... 54
2.8.2 Reset State ........................................................................................................ 55
2.8.3 Exception-Handling State................................................................................. 56
2.8.4 Program Execution State .................................................................................. 57
2.8.5 Power-Down State............................................................................................ 58
2.9 Basic Timing..................................................................................................................... 59

Rev. 1.0, 02/00, page ii of 19
2.9.1 Overview .......................................................................................................... 59
2.9.2 On-Chip Memory (ROM, RAM)...................................................................... 59
2.9.3 On-Chip Supporting Module Access Timing ................................................... 60
Section 3 MCU Operating Modes................................................................................ 61
3.1 Overview........................................................................................................................... 61
3.1.1 Operating Mode Selection................................................................................ 61
3.1.2 Register Configuration...................................................................................... 61
3.2 Register Descriptions........................................................................................................62
3.2.1 Mode Control Register (MDCR)...................................................................... 62
3.2.2 System Control Register (SYSCR)................................................................... 62
3.3 Operating Mode (Mode 1) ................................................................................................ 63
3.4 Address Map in Each Operating Mode............................................................................. 64
Section 4 Power-Down State......................................................................................... 67
4.1 Overview........................................................................................................................... 67
4.1.1 Register Configuration...................................................................................... 71
4.2 Register Descriptions........................................................................................................72
4.2.1 Standby Control Register (SBYCR)................................................................. 72
4.2.2 Low-Power Control Register (LPWRCR)........................................................ 74
4.2.3 Timer Register A (TMA).................................................................................. 76
4.2.4 Module Stop Control Register (MSTPCR)....................................................... 77
4.3 Medium-Speed Mode........................................................................................................ 78
4.4 Sleep Mode....................................................................................................................... 79
4.4.1 Sleep Mode....................................................................................................... 79
4.4.2 Clearing Sleep Mode ........................................................................................ 79
4.5 Module Stop Mode ........................................................................................................... 80
4.5.1 Module Stop Mode........................................................................................... 80
4.6 Standby Mode................................................................................................................... 81
4.6.1 Standby Mode................................................................................................... 81
4.6.2 Clearing Standby Mode.................................................................................... 81
4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode ...................... 81
4.7 Watch Mode...................................................................................................................... 83
4.7.1 Watch Mode ..................................................................................................... 83
4.7.2 Clearing Watch Mode....................................................................................... 83
4.8 Subsleep Mode.................................................................................................................. 84
4.8.1 Subsleep Mode ................................................................................................. 84
4.8.2 Clearing Subsleep Mode................................................................................... 84
4.9 Subactive Mode ................................................................................................................ 85
4.9.1 Subactive Mode................................................................................................ 85
4.9.2 Clearing Subactive Mode ................................................................................. 85
4.10 Direct Transition............................................................................................................... 86
4.10.1 Overview of Direct Transition.......................................................................... 86

Rev. 1.0, 02/00, page iii of 19
Section 5 Exception Handling....................................................................................... 87
5.1 Overview........................................................................................................................... 87
5.1.1 Exception Handling Types and Priority............................................................ 87
5.1.2 Exception Handling Operation......................................................................... 88
5.1.3 Exception Sources and Vector Table................................................................ 88
5.2 Reset.................................................................................................................................. 90
5.2.1 Overview .......................................................................................................... 90
5.2.2 Reset Sequence................................................................................................. 90
5.2.3 Interrupts after Reset......................................................................................... 91
5.3 Interrupts........................................................................................................................... 92
5.4 Trap Instruction................................................................................................................. 93
5.5 Stack Status after Exception Handling.............................................................................. 94
5.6 Notes on Use of the Stack................................................................................................. 95
Section 6 Interrupt Controller.......................................................................................... 97
6.1 Overview........................................................................................................................... 97
6.1.1 Features............................................................................................................. 97
6.1.2 Block Diagram.................................................................................................. 98
6.1.3 Pin Configuration ............................................................................................. 99
6.1.4 Register Configuration...................................................................................... 99
6.2 Register Descriptions........................................................................................................ 100
6.2.1 System Control Register (SYSCR)................................................................... 100
6.2.2 Interrupt Control Registers A to D (ICRA to ICRD)........................................ 101
6.2.3 IRQ Enable Register (IENR)............................................................................ 102
6.2.4 IRQ Edge Select Registers (IEGR)................................................................... 103
6.2.5 IRQ Status Register (IRQR)............................................................................. 104
6.2.6 Port Mode Register (PMR1)............................................................................. 105
6.3 Interrupt Sources............................................................................................................... 106
6.3.1 External Interrupts............................................................................................ 106
6.3.2 Internal Interrupts ............................................................................................. 107
6.3.3 Interrupt Exception Vector Table..................................................................... 108
6.4 Interrupt Operation............................................................................................................ 111
6.4.1 Interrupt Control Modes and Interrupt Operation............................................. 111
6.4.2 Interrupt Control Mode 0.................................................................................. 113
6.4.3 Interrupt Control Mode 1.................................................................................. 115
6.4.4 Interrupt Exception Handling Sequence........................................................... 118
6.4.5 Interrupt Response Times................................................................................. 119
6.5 Usage Notes...................................................................................................................... 120
6.5.1 Contention between Interrupt Generation and Disabling ................................. 120
6.5.2 Instructions that Disable Interrupts................................................................... 121
6.5.3 Interrupts during Execution of EEPMOV Instruction ...................................... 121

Rev. 1.0, 02/00, page iv of 19
Section 7 ROM.................................................................................................................. 123
7.1 Overview........................................................................................................................... 123
7.1.1 Block Diagram.................................................................................................. 123
7.2 Overview of Flash Memory.............................................................................................. 124
7.2.1 Features............................................................................................................. 124
7.2.2 Block Diagram.................................................................................................. 125
7.2.3 Flash Memory Operating Modes...................................................................... 126
7.2.4 Pin Configuration ............................................................................................. 130
7.2.5 Register Configuration...................................................................................... 130
7.3 Flash Memory Register Descriptions................................................................................ 131
7.3.1 Flash Memory Control Register 1 (FLMCR1) ................................................. 131
7.3.2 Flash Memory Control Register 2 (FLMCR2) ................................................. 134
7.3.3 Erase Block Register 1 (EBR1)........................................................................ 137
7.3.4 Erase Block Register 2 (EBR2)........................................................................ 137
7.3.5 Serial/Timer Control Register (STCR)............................................................. 138
7.4 On-Board Programming Modes........................................................................................ 140
7.4.1 Boot Mode........................................................................................................ 141
7.4.2 User Program Mode.......................................................................................... 146
7.5 Programming/Erasing Flash Memory............................................................................... 147
7.5.1 Program Mode (n=1 when the target address range is H'00000 to H'3FFFF
and n=2 when the target address range is H'40000 to H'47FFF) ...................... 147
7.5.2 Program-Verify Mode ...................................................................................... 148
7.5.3 Erase Mode (n = 1 when the target address range is H'00000 to H'3FFFF
and n = 2 when the target address range is H'40000 to H'47FFF).................... 150
7.5.4 Erase-Verify Mode (n = 1 when the target address range is H'00000 to H'3FFFF
and n = 2 when the target address range is H'40000 to H'47FFF).................... 152
7.6 Flash Memory Protection.................................................................................................. 153
7.6.1 Hardware Protection......................................................................................... 153
7.6.2 Software Protection .......................................................................................... 154
7.6.3 Error Protection ................................................................................................ 155
7.7 Interrupt Handling when Programming/Erasing Flash Memory....................................... 156
7.8 Flash Memory Writer Mode ............................................................................................. 157
7.8.1 Writer Mode Setting......................................................................................... 157
7.8.2 Socket Adapters and Memory Map.................................................................. 157
7.8.3 Writer Mode Operation..................................................................................... 158
7.8.4 Memory Read Mode......................................................................................... 159
7.8.5 Auto-Program Mode......................................................................................... 162
7.8.6 Auto-Erase Mode.............................................................................................. 164
7.8.7 Status Read Mode............................................................................................. 165
7.8.8 Status Polling.................................................................................................... 167
7.8.9 Writer Mode Transition Time........................................................................... 168
7.8.10 Notes on Memory Programming ...................................................................... 168

Rev. 1.0, 02/00, page v of 19
7.9 Notes when Converting the F–ZTAT Application Software to the Mask-ROM
Versions............................................................................................................................ 169
Section 8 RAM.................................................................................................................. 171
8.1 Overview........................................................................................................................... 171
8.1.1 Block Diagram.................................................................................................. 171
Section 9 Clock Pulse Generator.................................................................................. 173
9.1 Overview........................................................................................................................... 173
9.1.1 Block Diagram.................................................................................................. 173
9.1.2 Register Configuration...................................................................................... 173
9.2 Register Descriptions........................................................................................................ 174
9.2.1 Standby Control Register (SBYCR)................................................................. 174
9.2.2 Low-Power Control Register (LPWRCR)........................................................ 175
9.3 Oscillator........................................................................................................................... 176
9.3.1 Connecting a Crystal Resonator ....................................................................... 176
9.3.2 External Clock Input......................................................................................... 178
9.4 Duty Adjustment Circuit................................................................................................... 181
9.5 Medium-Speed Clock Divider.......................................................................................... 181
9.6 Bus Master Clock Selection Circuit.................................................................................. 181
9.7 Subclock Oscillator Circuit............................................................................................... 182
9.7.1 Connecting 32.768 kHz Crystal Resonator....................................................... 182
9.7.2 When Subclock is not Needed.......................................................................... 183
9.8 Subclock Waveform Shaping Circuit................................................................................ 183
9.9 Notes on the Resonator..................................................................................................... 183
Section 10 I/O Port.............................................................................................................. 185
10.1 Overview........................................................................................................................... 185
10.1.1 Port Functions................................................................................................... 185
10.1.2 Port Input.......................................................................................................... 185
10.1.3 MOS Pull-Up Transistors ................................................................................. 188
10.2 Port 0................................................................................................................................. 189
10.2.1 Overview .......................................................................................................... 189
10.2.2 Register Configuration...................................................................................... 190
10.2.3 Pin Functions.................................................................................................... 191
10.2.4 Pin States .......................................................................................................... 191
10.3 Port 1................................................................................................................................. 192
10.3.1 Overview .......................................................................................................... 192
10.3.2 Register Configuration...................................................................................... 192
10.3.3 Pin Functions.................................................................................................... 196
10.3.4 Pin States .......................................................................................................... 197
10.4 Port 2................................................................................................................................. 198
10.4.1 Overview .......................................................................................................... 198

Rev. 1.0, 02/00, page vi of 19
10.4.2 Register Configuration...................................................................................... 198
10.4.3 Pin Functions.................................................................................................... 201
10.4.4 Pin States .......................................................................................................... 203
10.5 Port 3................................................................................................................................. 204
10.5.1 Overview .......................................................................................................... 204
10.5.2 Register Configuration...................................................................................... 204
10.5.3 Pin Functions.................................................................................................... 208
10.5.4 Pin States .......................................................................................................... 211
10.6 Port 4................................................................................................................................. 212
10.6.1 Overview .......................................................................................................... 212
10.6.2 Register Configuration...................................................................................... 212
10.6.3 Pin Functions.................................................................................................... 215
10.6.4 Pin States .......................................................................................................... 217
10.7 Port 6................................................................................................................................. 218
10.7.1 Overview .......................................................................................................... 218
10.7.2 Register Configuration...................................................................................... 219
10.7.3 Pin Functions.................................................................................................... 224
10.7.4 Operation.......................................................................................................... 226
10.7.5 Pin States .......................................................................................................... 227
10.8 Port 7................................................................................................................................. 228
10.8.1 Overview .......................................................................................................... 228
10.8.2 Register Configuration...................................................................................... 229
10.8.3 Pin Functions.................................................................................................... 234
10.8.4 Operation.......................................................................................................... 235
10.8.5 Pin States .......................................................................................................... 236
10.9 Port 8................................................................................................................................. 237
10.9.1 Overview .......................................................................................................... 237
10.9.2 Register Configuration...................................................................................... 238
10.9.3 Pin Functions.................................................................................................... 244
10.9.4 Pin States .......................................................................................................... 246
Section 11 Timer A............................................................................................................. 247
11.1 Overview........................................................................................................................... 247
11.1.1 Features............................................................................................................. 247
11.1.2 Block Diagram.................................................................................................. 248
11.1.3 Register Configuration...................................................................................... 248
11.2 Register Descriptions........................................................................................................ 249
11.2.1 Timer Mode Register A (TMA)........................................................................ 249
11.2.2 Timer Counter A (TCA)................................................................................... 251
11.2.3 Module Stop Control Register (MSTPCR)....................................................... 251
11.3 Operation .......................................................................................................................... 252
11.3.1 Operation as the Interval Timer........................................................................ 252
11.3.2 Operation as Clock Timer................................................................................. 252

Rev. 1.0, 02/00, page vii of 19
11.3.3 Initializing the Counts....................................................................................... 252
Section 12 Timer B............................................................................................................. 253
12.1 Overview........................................................................................................................... 253
12.1.1 Features............................................................................................................. 253
12.1.2 Block Diagram.................................................................................................. 253
12.1.3 Pin Configuration ............................................................................................. 254
12.1.4 Register Configuration...................................................................................... 254
12.2 Register Descriptions........................................................................................................ 255
12.2.1 Timer Mode Register B (TMB)........................................................................ 255
12.2.2 Timer Counter B (TCB).................................................................................... 257
12.2.3 Timer Load Register B (TLB).......................................................................... 257
12.2.4 Port Mode Register A (PMRA)........................................................................ 258
12.2.5 Module Stop Control Register (MSTPCR)....................................................... 259
12.3 Operation .......................................................................................................................... 260
12.3.1 Operation as the Interval Timer........................................................................ 260
12.3.2 Operation as the Auto Reload Timer................................................................ 260
12.3.3 Event Counter................................................................................................... 260
Section 13 Timer J............................................................................................................... 261
13.1 Overview........................................................................................................................... 261
13.1.1 Features............................................................................................................. 261
13.1.2 Block Diagram.................................................................................................. 261
13.1.3 Pin Configuration ............................................................................................. 263
13.1.4 Register Configuration...................................................................................... 263
13.2 Register Descriptions........................................................................................................ 264
13.2.1 Timer Mode Register J (TMJ).......................................................................... 264
13.2.2 Timer J Control Register (TMJC)..................................................................... 267
13.2.3 Timer J Status Register (TMJS)........................................................................ 270
13.2.4 Timer Counter J (TCJ)...................................................................................... 271
13.2.5 Timer Counter K (TCK)................................................................................... 271
13.2.6 Timer Load Register J (TLJ) ............................................................................ 272
13.2.7 Timer Load Register K (TLK).......................................................................... 272
13.2.8 Module Stop Control Register (MSTPCR)....................................................... 273
13.3 Operation .......................................................................................................................... 274
13.3.1 8-bit Reload Timer (TMJ-1)............................................................................. 274
13.3.2 8-bit Reload Timer (TMJ-2)............................................................................. 274
13.3.3 Remote Controlled Data Transmission............................................................. 275
13.3.4 TMJ-2 Expansion Function .............................................................................. 278
Section 14 Timer L.............................................................................................................. 279
14.1 Overview........................................................................................................................... 279
14.1.1 Features............................................................................................................. 279

Rev. 1.0, 02/00, page viii of 19
14.1.2 Block Diagram.................................................................................................. 280
14.1.3 Register Configuration...................................................................................... 281
14.2 Register Descriptions........................................................................................................ 282
14.2.1 Timer L Mode Register (LMR)........................................................................ 282
14.2.2 Linear Time Counter (LTC) ............................................................................. 284
14.2.3 Reload/Compare Match Register (RCR) .......................................................... 284
14.2.4 Module Stop Control Register (MSTPCR)....................................................... 285
14.3 Operation .......................................................................................................................... 286
14.3.1 Compare Match Clear Operation...................................................................... 286
Section 15 Timer R............................................................................................................. 289
15.1 Overview........................................................................................................................... 289
15.1.1 Features............................................................................................................. 289
15.1.2 Block Diagram.................................................................................................. 289
15.1.3 Pin Configuration ............................................................................................. 291
15.1.4 Register Configuration...................................................................................... 291
15.2 Register Descriptions........................................................................................................ 292
15.2.1 Timer R Mode Register 1 (TMRM1) ............................................................... 292
15.2.2 Timer R Mode Register 2 (TMRM2) ............................................................... 294
15.2.3 Timer R Control/Status Register (TMRCS)...................................................... 297
15.2.4 Timer R Capture Register 1 (TMRCP1)........................................................... 299
15.2.5 Timer R Capture Register 2 (TMRCP2)........................................................... 300
15.2.6 Timer R Load Register 1 (TMRL1).................................................................. 300
15.2.7 Timer R Load Register 2 (TMRL2).................................................................. 301
15.2.8 Timer R Load Register 3 (TMRL3).................................................................. 301
15.2.9 Module Stop Control Register (MSTPCR)....................................................... 302
15.3 Operation .......................................................................................................................... 303
15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1 .............. 303
15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2 .............. 304
15.3.3 Reload Counter Timer TMRU-3....................................................................... 304
15.3.4 Mode Identification .......................................................................................... 305
15.3.5 Reeling Controls............................................................................................... 305
15.3.6 Acceleration and Braking Processes of the Capstan Motor.............................. 305
15.3.7 Slow Tracking Mono-Multi Function............................................................... 306
15.4 Interrupt Cause.................................................................................................................. 308
15.5 Settings for Respective Functions..................................................................................... 309
15.5.1 Mode Identification .......................................................................................... 309
15.5.2 Reeling Controls............................................................................................... 310
15.5.3 Slow Tracking Mono-Multi Function............................................................... 310
15.5.4 Acceleration and Braking Processes of the Capstan Motor.............................. 311
Section 16 Timer X1........................................................................................................... 313
16.1 Overview........................................................................................................................... 313