Hitachi H8S/2199 User manual

Hitachi Single-Chip Microcomputer
H8S/2199 Series
H8S/2199
HD6432199
H8S/2198
HD6432198
H8S/2197
HD6432197
H8S/2196
HD6432196
H8S/2199F-ZTAT™
HD64F2199
Hardware Manual
ADE-602-191
Rev 1.0
2/15/00
Hitachi, Ltd.

Cautions
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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semiconductor products.

Rev. 1.0, 02/00, page i of 19
Contents
Section 1 Overview........................................................................................................... 1
1.1 Overview........................................................................................................................... 1
1.2 Internal Block Diagram..................................................................................................... 7
1.3 Pin Arrangement and Functions........................................................................................ 8
1.3.1 Pin Arrangement............................................................................................... 8
1.3.2 Pin Functions.................................................................................................... 9
Section 2 CPU.................................................................................................................... 17
2.1 Overview........................................................................................................................... 17
2.1.1 Features............................................................................................................. 17
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU............................... 18
2.1.3 Differences from H8/300 CPU......................................................................... 18
2.1.4 Differences from H8/300H CPU ...................................................................... 19
2.2 CPU Operating Modes...................................................................................................... 20
2.3 Address Space................................................................................................................... 25
2.4 Register Configuration...................................................................................................... 26
2.4.1 Overview .......................................................................................................... 26
2.4.2 General Registers.............................................................................................. 27
2.4.3 Control Registers.............................................................................................. 28
2.4.4 Initial Register Values ...................................................................................... 29
2.5 Data Formats..................................................................................................................... 30
2.5.1 General Register Data Formats......................................................................... 30
2.5.2 Memory Data Formats...................................................................................... 32
2.6 Instruction Set................................................................................................................... 33
2.6.1 Overview .......................................................................................................... 33
2.6.2 Instructions and Addressing Modes.................................................................. 34
2.6.3 Table of Instructions Classified by Function.................................................... 35
2.6.4 Basic Instruction Formats................................................................................. 45
2.6.5 Notes on Use of Bit-Manipulation Instructions................................................ 46
2.7 Addressing Modes and Effective Address Calculation..................................................... 47
2.7.1 Addressing Mode.............................................................................................. 47
2.7.2 Effective Address Calculation.......................................................................... 50
2.8 Processing States............................................................................................................... 54
2.8.1 Overview .......................................................................................................... 54
2.8.2 Reset State ........................................................................................................ 55
2.8.3 Exception-Handling State................................................................................. 56
2.8.4 Program Execution State .................................................................................. 57
2.8.5 Power-Down State............................................................................................ 58
2.9 Basic Timing..................................................................................................................... 59

Rev. 1.0, 02/00, page ii of 19
2.9.1 Overview .......................................................................................................... 59
2.9.2 On-Chip Memory (ROM, RAM)...................................................................... 59
2.9.3 On-Chip Supporting Module Access Timing ................................................... 60
Section 3 MCU Operating Modes................................................................................ 61
3.1 Overview........................................................................................................................... 61
3.1.1 Operating Mode Selection................................................................................ 61
3.1.2 Register Configuration...................................................................................... 61
3.2 Register Descriptions........................................................................................................62
3.2.1 Mode Control Register (MDCR)...................................................................... 62
3.2.2 System Control Register (SYSCR)................................................................... 62
3.3 Operating Mode (Mode 1) ................................................................................................ 63
3.4 Address Map in Each Operating Mode............................................................................. 64
Section 4 Power-Down State......................................................................................... 67
4.1 Overview........................................................................................................................... 67
4.1.1 Register Configuration...................................................................................... 71
4.2 Register Descriptions........................................................................................................72
4.2.1 Standby Control Register (SBYCR)................................................................. 72
4.2.2 Low-Power Control Register (LPWRCR)........................................................ 74
4.2.3 Timer Register A (TMA).................................................................................. 76
4.2.4 Module Stop Control Register (MSTPCR)....................................................... 77
4.3 Medium-Speed Mode........................................................................................................ 78
4.4 Sleep Mode....................................................................................................................... 79
4.4.1 Sleep Mode....................................................................................................... 79
4.4.2 Clearing Sleep Mode ........................................................................................ 79
4.5 Module Stop Mode ........................................................................................................... 80
4.5.1 Module Stop Mode........................................................................................... 80
4.6 Standby Mode................................................................................................................... 81
4.6.1 Standby Mode................................................................................................... 81
4.6.2 Clearing Standby Mode.................................................................................... 81
4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode ...................... 81
4.7 Watch Mode...................................................................................................................... 83
4.7.1 Watch Mode ..................................................................................................... 83
4.7.2 Clearing Watch Mode....................................................................................... 83
4.8 Subsleep Mode.................................................................................................................. 84
4.8.1 Subsleep Mode ................................................................................................. 84
4.8.2 Clearing Subsleep Mode................................................................................... 84
4.9 Subactive Mode ................................................................................................................ 85
4.9.1 Subactive Mode................................................................................................ 85
4.9.2 Clearing Subactive Mode ................................................................................. 85
4.10 Direct Transition............................................................................................................... 86
4.10.1 Overview of Direct Transition.......................................................................... 86

Rev. 1.0, 02/00, page iii of 19
Section 5 Exception Handling....................................................................................... 87
5.1 Overview........................................................................................................................... 87
5.1.1 Exception Handling Types and Priority............................................................ 87
5.1.2 Exception Handling Operation......................................................................... 88
5.1.3 Exception Sources and Vector Table................................................................ 88
5.2 Reset.................................................................................................................................. 90
5.2.1 Overview .......................................................................................................... 90
5.2.2 Reset Sequence................................................................................................. 90
5.2.3 Interrupts after Reset......................................................................................... 91
5.3 Interrupts........................................................................................................................... 92
5.4 Trap Instruction................................................................................................................. 93
5.5 Stack Status after Exception Handling.............................................................................. 94
5.6 Notes on Use of the Stack................................................................................................. 95
Section 6 Interrupt Controller.......................................................................................... 97
6.1 Overview........................................................................................................................... 97
6.1.1 Features............................................................................................................. 97
6.1.2 Block Diagram.................................................................................................. 98
6.1.3 Pin Configuration ............................................................................................. 99
6.1.4 Register Configuration...................................................................................... 99
6.2 Register Descriptions........................................................................................................ 100
6.2.1 System Control Register (SYSCR)................................................................... 100
6.2.2 Interrupt Control Registers A to D (ICRA to ICRD)........................................ 101
6.2.3 IRQ Enable Register (IENR)............................................................................ 102
6.2.4 IRQ Edge Select Registers (IEGR)................................................................... 103
6.2.5 IRQ Status Register (IRQR)............................................................................. 104
6.2.6 Port Mode Register (PMR1)............................................................................. 105
6.3 Interrupt Sources............................................................................................................... 106
6.3.1 External Interrupts............................................................................................ 106
6.3.2 Internal Interrupts ............................................................................................. 107
6.3.3 Interrupt Exception Vector Table..................................................................... 108
6.4 Interrupt Operation............................................................................................................ 111
6.4.1 Interrupt Control Modes and Interrupt Operation............................................. 111
6.4.2 Interrupt Control Mode 0.................................................................................. 113
6.4.3 Interrupt Control Mode 1.................................................................................. 115
6.4.4 Interrupt Exception Handling Sequence........................................................... 118
6.4.5 Interrupt Response Times................................................................................. 119
6.5 Usage Notes...................................................................................................................... 120
6.5.1 Contention between Interrupt Generation and Disabling ................................. 120
6.5.2 Instructions that Disable Interrupts................................................................... 121
6.5.3 Interrupts during Execution of EEPMOV Instruction ...................................... 121

Rev. 1.0, 02/00, page iv of 19
Section 7 ROM.................................................................................................................. 123
7.1 Overview........................................................................................................................... 123
7.1.1 Block Diagram.................................................................................................. 123
7.2 Overview of Flash Memory.............................................................................................. 124
7.2.1 Features............................................................................................................. 124
7.2.2 Block Diagram.................................................................................................. 125
7.2.3 Flash Memory Operating Modes...................................................................... 126
7.2.4 Pin Configuration ............................................................................................. 130
7.2.5 Register Configuration...................................................................................... 130
7.3 Flash Memory Register Descriptions................................................................................ 131
7.3.1 Flash Memory Control Register 1 (FLMCR1) ................................................. 131
7.3.2 Flash Memory Control Register 2 (FLMCR2) ................................................. 134
7.3.3 Erase Block Register 1 (EBR1)........................................................................ 137
7.3.4 Erase Block Register 2 (EBR2)........................................................................ 137
7.3.5 Serial/Timer Control Register (STCR)............................................................. 138
7.4 On-Board Programming Modes........................................................................................ 140
7.4.1 Boot Mode........................................................................................................ 141
7.4.2 User Program Mode.......................................................................................... 146
7.5 Programming/Erasing Flash Memory............................................................................... 147
7.5.1 Program Mode (n=1 when the target address range is H'00000 to H'3FFFF
and n=2 when the target address range is H'40000 to H'47FFF) ...................... 147
7.5.2 Program-Verify Mode ...................................................................................... 148
7.5.3 Erase Mode (n = 1 when the target address range is H'00000 to H'3FFFF
and n = 2 when the target address range is H'40000 to H'47FFF).................... 150
7.5.4 Erase-Verify Mode (n = 1 when the target address range is H'00000 to H'3FFFF
and n = 2 when the target address range is H'40000 to H'47FFF).................... 152
7.6 Flash Memory Protection.................................................................................................. 153
7.6.1 Hardware Protection......................................................................................... 153
7.6.2 Software Protection .......................................................................................... 154
7.6.3 Error Protection ................................................................................................ 155
7.7 Interrupt Handling when Programming/Erasing Flash Memory....................................... 156
7.8 Flash Memory Writer Mode ............................................................................................. 157
7.8.1 Writer Mode Setting......................................................................................... 157
7.8.2 Socket Adapters and Memory Map.................................................................. 157
7.8.3 Writer Mode Operation..................................................................................... 158
7.8.4 Memory Read Mode......................................................................................... 159
7.8.5 Auto-Program Mode......................................................................................... 162
7.8.6 Auto-Erase Mode.............................................................................................. 164
7.8.7 Status Read Mode............................................................................................. 165
7.8.8 Status Polling.................................................................................................... 167
7.8.9 Writer Mode Transition Time........................................................................... 168
7.8.10 Notes on Memory Programming ...................................................................... 168

Rev. 1.0, 02/00, page v of 19
7.9 Notes when Converting the F–ZTAT Application Software to the Mask-ROM
Versions............................................................................................................................ 169
Section 8 RAM.................................................................................................................. 171
8.1 Overview........................................................................................................................... 171
8.1.1 Block Diagram.................................................................................................. 171
Section 9 Clock Pulse Generator.................................................................................. 173
9.1 Overview........................................................................................................................... 173
9.1.1 Block Diagram.................................................................................................. 173
9.1.2 Register Configuration...................................................................................... 173
9.2 Register Descriptions........................................................................................................ 174
9.2.1 Standby Control Register (SBYCR)................................................................. 174
9.2.2 Low-Power Control Register (LPWRCR)........................................................ 175
9.3 Oscillator........................................................................................................................... 176
9.3.1 Connecting a Crystal Resonator ....................................................................... 176
9.3.2 External Clock Input......................................................................................... 178
9.4 Duty Adjustment Circuit................................................................................................... 181
9.5 Medium-Speed Clock Divider.......................................................................................... 181
9.6 Bus Master Clock Selection Circuit.................................................................................. 181
9.7 Subclock Oscillator Circuit............................................................................................... 182
9.7.1 Connecting 32.768 kHz Crystal Resonator....................................................... 182
9.7.2 When Subclock is not Needed.......................................................................... 183
9.8 Subclock Waveform Shaping Circuit................................................................................ 183
9.9 Notes on the Resonator..................................................................................................... 183
Section 10 I/O Port.............................................................................................................. 185
10.1 Overview........................................................................................................................... 185
10.1.1 Port Functions................................................................................................... 185
10.1.2 Port Input.......................................................................................................... 185
10.1.3 MOS Pull-Up Transistors ................................................................................. 188
10.2 Port 0................................................................................................................................. 189
10.2.1 Overview .......................................................................................................... 189
10.2.2 Register Configuration...................................................................................... 190
10.2.3 Pin Functions.................................................................................................... 191
10.2.4 Pin States .......................................................................................................... 191
10.3 Port 1................................................................................................................................. 192
10.3.1 Overview .......................................................................................................... 192
10.3.2 Register Configuration...................................................................................... 192
10.3.3 Pin Functions.................................................................................................... 196
10.3.4 Pin States .......................................................................................................... 197
10.4 Port 2................................................................................................................................. 198
10.4.1 Overview .......................................................................................................... 198

Rev. 1.0, 02/00, page vi of 19
10.4.2 Register Configuration...................................................................................... 198
10.4.3 Pin Functions.................................................................................................... 201
10.4.4 Pin States .......................................................................................................... 203
10.5 Port 3................................................................................................................................. 204
10.5.1 Overview .......................................................................................................... 204
10.5.2 Register Configuration...................................................................................... 204
10.5.3 Pin Functions.................................................................................................... 208
10.5.4 Pin States .......................................................................................................... 211
10.6 Port 4................................................................................................................................. 212
10.6.1 Overview .......................................................................................................... 212
10.6.2 Register Configuration...................................................................................... 212
10.6.3 Pin Functions.................................................................................................... 215
10.6.4 Pin States .......................................................................................................... 217
10.7 Port 6................................................................................................................................. 218
10.7.1 Overview .......................................................................................................... 218
10.7.2 Register Configuration...................................................................................... 219
10.7.3 Pin Functions.................................................................................................... 224
10.7.4 Operation.......................................................................................................... 226
10.7.5 Pin States .......................................................................................................... 227
10.8 Port 7................................................................................................................................. 228
10.8.1 Overview .......................................................................................................... 228
10.8.2 Register Configuration...................................................................................... 229
10.8.3 Pin Functions.................................................................................................... 234
10.8.4 Operation.......................................................................................................... 235
10.8.5 Pin States .......................................................................................................... 236
10.9 Port 8................................................................................................................................. 237
10.9.1 Overview .......................................................................................................... 237
10.9.2 Register Configuration...................................................................................... 238
10.9.3 Pin Functions.................................................................................................... 244
10.9.4 Pin States .......................................................................................................... 246
Section 11 Timer A............................................................................................................. 247
11.1 Overview........................................................................................................................... 247
11.1.1 Features............................................................................................................. 247
11.1.2 Block Diagram.................................................................................................. 248
11.1.3 Register Configuration...................................................................................... 248
11.2 Register Descriptions........................................................................................................ 249
11.2.1 Timer Mode Register A (TMA)........................................................................ 249
11.2.2 Timer Counter A (TCA)................................................................................... 251
11.2.3 Module Stop Control Register (MSTPCR)....................................................... 251
11.3 Operation .......................................................................................................................... 252
11.3.1 Operation as the Interval Timer........................................................................ 252
11.3.2 Operation as Clock Timer................................................................................. 252

Rev. 1.0, 02/00, page vii of 19
11.3.3 Initializing the Counts....................................................................................... 252
Section 12 Timer B............................................................................................................. 253
12.1 Overview........................................................................................................................... 253
12.1.1 Features............................................................................................................. 253
12.1.2 Block Diagram.................................................................................................. 253
12.1.3 Pin Configuration ............................................................................................. 254
12.1.4 Register Configuration...................................................................................... 254
12.2 Register Descriptions........................................................................................................ 255
12.2.1 Timer Mode Register B (TMB)........................................................................ 255
12.2.2 Timer Counter B (TCB).................................................................................... 257
12.2.3 Timer Load Register B (TLB).......................................................................... 257
12.2.4 Port Mode Register A (PMRA)........................................................................ 258
12.2.5 Module Stop Control Register (MSTPCR)....................................................... 259
12.3 Operation .......................................................................................................................... 260
12.3.1 Operation as the Interval Timer........................................................................ 260
12.3.2 Operation as the Auto Reload Timer................................................................ 260
12.3.3 Event Counter................................................................................................... 260
Section 13 Timer J............................................................................................................... 261
13.1 Overview........................................................................................................................... 261
13.1.1 Features............................................................................................................. 261
13.1.2 Block Diagram.................................................................................................. 261
13.1.3 Pin Configuration ............................................................................................. 263
13.1.4 Register Configuration...................................................................................... 263
13.2 Register Descriptions........................................................................................................ 264
13.2.1 Timer Mode Register J (TMJ).......................................................................... 264
13.2.2 Timer J Control Register (TMJC)..................................................................... 267
13.2.3 Timer J Status Register (TMJS)........................................................................ 270
13.2.4 Timer Counter J (TCJ)...................................................................................... 271
13.2.5 Timer Counter K (TCK)................................................................................... 271
13.2.6 Timer Load Register J (TLJ) ............................................................................ 272
13.2.7 Timer Load Register K (TLK).......................................................................... 272
13.2.8 Module Stop Control Register (MSTPCR)....................................................... 273
13.3 Operation .......................................................................................................................... 274
13.3.1 8-bit Reload Timer (TMJ-1)............................................................................. 274
13.3.2 8-bit Reload Timer (TMJ-2)............................................................................. 274
13.3.3 Remote Controlled Data Transmission............................................................. 275
13.3.4 TMJ-2 Expansion Function .............................................................................. 278
Section 14 Timer L.............................................................................................................. 279
14.1 Overview........................................................................................................................... 279
14.1.1 Features............................................................................................................. 279

Rev. 1.0, 02/00, page viii of 19
14.1.2 Block Diagram.................................................................................................. 280
14.1.3 Register Configuration...................................................................................... 281
14.2 Register Descriptions........................................................................................................ 282
14.2.1 Timer L Mode Register (LMR)........................................................................ 282
14.2.2 Linear Time Counter (LTC) ............................................................................. 284
14.2.3 Reload/Compare Match Register (RCR) .......................................................... 284
14.2.4 Module Stop Control Register (MSTPCR)....................................................... 285
14.3 Operation .......................................................................................................................... 286
14.3.1 Compare Match Clear Operation...................................................................... 286
Section 15 Timer R............................................................................................................. 289
15.1 Overview........................................................................................................................... 289
15.1.1 Features............................................................................................................. 289
15.1.2 Block Diagram.................................................................................................. 289
15.1.3 Pin Configuration ............................................................................................. 291
15.1.4 Register Configuration...................................................................................... 291
15.2 Register Descriptions........................................................................................................ 292
15.2.1 Timer R Mode Register 1 (TMRM1) ............................................................... 292
15.2.2 Timer R Mode Register 2 (TMRM2) ............................................................... 294
15.2.3 Timer R Control/Status Register (TMRCS)...................................................... 297
15.2.4 Timer R Capture Register 1 (TMRCP1)........................................................... 299
15.2.5 Timer R Capture Register 2 (TMRCP2)........................................................... 300
15.2.6 Timer R Load Register 1 (TMRL1).................................................................. 300
15.2.7 Timer R Load Register 2 (TMRL2).................................................................. 301
15.2.8 Timer R Load Register 3 (TMRL3).................................................................. 301
15.2.9 Module Stop Control Register (MSTPCR)....................................................... 302
15.3 Operation .......................................................................................................................... 303
15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1 .............. 303
15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2 .............. 304
15.3.3 Reload Counter Timer TMRU-3....................................................................... 304
15.3.4 Mode Identification .......................................................................................... 305
15.3.5 Reeling Controls............................................................................................... 305
15.3.6 Acceleration and Braking Processes of the Capstan Motor.............................. 305
15.3.7 Slow Tracking Mono-Multi Function............................................................... 306
15.4 Interrupt Cause.................................................................................................................. 308
15.5 Settings for Respective Functions..................................................................................... 309
15.5.1 Mode Identification .......................................................................................... 309
15.5.2 Reeling Controls............................................................................................... 310
15.5.3 Slow Tracking Mono-Multi Function............................................................... 310
15.5.4 Acceleration and Braking Processes of the Capstan Motor.............................. 311
Section 16 Timer X1........................................................................................................... 313
16.1 Overview........................................................................................................................... 313

Rev. 1.0, 02/00, page ix of 19
16.1.1 Features............................................................................................................. 313
16.1.2 Block Diagram.................................................................................................. 314
16.1.3 Pin Configuration ............................................................................................. 315
16.1.4 Register Configuration...................................................................................... 316
16.2 Register Descriptions........................................................................................................ 317
16.2.1 Free Running Counter (FRC) ........................................................................... 317
16.2.2 Output Comparing Registers A and B (OCRA and OCRB)............................. 318
16.2.3 Input Capture Registers A Through D (ICRA Through ICRD)........................ 319
16.2.4 Timer Interrupt Enabling Register (TIER) ....................................................... 321
16.2.5 Timer Control/Status Register X (TCSRX)...................................................... 324
16.2.6 Timer Control Register X (TCRX)................................................................... 328
16.2.7 Timer Output Comparing Control Register (TOCR)........................................ 330
16.2.8 Module Stop Control Register (MSTPCR)....................................................... 332
16.3 Operation .......................................................................................................................... 333
16.3.1 Operation of Timer X1 ..................................................................................... 333
16.3.2 Counting Timing of the FRC............................................................................ 334
16.3.3 Output Comparing Signal Outputting Timing.................................................. 335
16.3.4 FRC Clearing Timing....................................................................................... 335
16.3.5 Input Capture Signal Inputting Timing............................................................. 336
16.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing......................... 337
16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing..................... 338
16.3.8 Overflow Flag (CVF) Setting Up Timing......................................................... 338
16.4 Operation Mode of Timer X1 ........................................................................................... 339
16.5 Interrupt Causes................................................................................................................ 340
16.6 Exemplary Uses of Timer X1 ........................................................................................... 341
16.7 Precautions when Using Timer X1................................................................................... 342
16.7.1 Competition between Writing and Clearing with the FRC............................... 342
16.7.2 Competition between Writing and Counting Up with the FRC........................ 343
16.7.3 Competition between Writing and Comparing Match with the OCR............... 344
16.7.4 Changing Over the Internal Clocks and Counter Operations............................ 345
Section 17 Watchdog Timer (WDT).............................................................................. 347
17.1 Overview........................................................................................................................... 347
17.1.1 Features............................................................................................................. 347
17.1.2 Block Diagram.................................................................................................. 348
17.1.3 Register Configuration...................................................................................... 349
17.2 Register Descriptions........................................................................................................ 350
17.2.1 Watchdog Timer Counter (WTCNT)................................................................ 350
17.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................ 350
17.2.3 System Control Register (SYSCR)................................................................... 353
17.2.4 Notes on Register Access ................................................................................. 354
17.3 Operation .......................................................................................................................... 355
17.3.1 Watchdog Timer Operation.............................................................................. 355

Rev. 1.0, 02/00, page x of 19
17.3.2 Interval Timer Operation.................................................................................. 356
17.3.3 Timing of Setting of Overflow Flag (OVF)...................................................... 357
17.4 Interrupts........................................................................................................................... 358
17.5 Usage Notes...................................................................................................................... 358
17.5.1 Contention between Watchdog Timer Counter (WTCNT)
Write and Increment......................................................................................... 358
17.5.2 Changing Value of CKS2 to CKS0 .................................................................. 359
17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode ............ 359
Section 18 8-Bit PWM....................................................................................................... 361
18.1 Overview........................................................................................................................... 361
18.1.1 Features............................................................................................................. 361
18.1.2 Block Diagram.................................................................................................. 361
18.1.3 Pin Configuration ............................................................................................. 362
18.1.4 Register Configuration...................................................................................... 362
18.2 Register Descriptions........................................................................................................ 363
18.2.1 8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) ....... 363
18.2.2 8-bit PWM Control Register (PW8CR)............................................................ 364
18.2.3 Port Mode Register 3 (PMR3).......................................................................... 365
18.2.4 Module Stop Control Register (MSTPCR)....................................................... 366
18.3 8-Bit PWM Operation....................................................................................................... 367
Section 19 12-Bit PWM .................................................................................................... 369
19.1 Overview........................................................................................................................... 369
19.1.1 Features............................................................................................................. 369
19.1.2 Block Diagram.................................................................................................. 370
19.1.3 Pin Configuration ............................................................................................. 371
19.1.4 Register Configuration...................................................................................... 371
19.2 Register Descriptions........................................................................................................ 372
19.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR)....................................... 372
19.2.2 12-Bit PWM Data Registers (DPWDR, CPWDR)........................................... 375
19.3 Operation .......................................................................................................................... 376
19.3.1 Output Waveform............................................................................................. 376
Section 20 14-Bit PWM .................................................................................................... 379
20.1 Overview........................................................................................................................... 379
20.1.1 Features............................................................................................................. 379
20.1.2 Block Diagram.................................................................................................. 380
20.1.3 Pin Configuration ............................................................................................. 380
20.1.4 Register Configuration...................................................................................... 381
20.2 Register Descriptions........................................................................................................ 382
20.2.1 PWM Control Register (PWCR) ...................................................................... 382
20.2.2 PWM Data Registers U and L (PWDRU, PWDRL)......................................... 383

Rev. 1.0, 02/00, page xi of 19
20.2.3 Module Stop Control Register (MSTPCR)....................................................... 384
20.3 14-Bit PWM Operation..................................................................................................... 385
Section 21 Prescalar Unit.................................................................................................. 387
21.1 Overview........................................................................................................................... 387
21.1.1 Features............................................................................................................. 387
21.1.2 Block Diagram.................................................................................................. 388
21.1.3 Pin Configuration ............................................................................................. 389
21.1.4 Register Configuration...................................................................................... 389
21.2 Registers............................................................................................................................ 390
21.2.1 Input Capture Register 1 (ICR1)....................................................................... 390
21.2.2 Prescalar Unit Control/Status Register (PCSR)................................................ 390
21.2.3 Port Mode Register 1 (PMR1).......................................................................... 393
21.3 Noise Cancel Circuit......................................................................................................... 394
21.4 Operation .......................................................................................................................... 394
21.4.1 Prescalar S (PSS).............................................................................................. 394
21.4.2 Prescalar W (PSW)........................................................................................... 395
21.4.3 Stable Oscillation Wait Time Count................................................................. 395
21.4.4 8-bit PWM........................................................................................................ 396
21.4.5 8-bit Input Capture Using ,& Pin...................................................................... 396
21.4.6 Frequency Division Clock Output.................................................................... 396
Section 22 Serial Communication Interface 1 (SCI1) .............................................. 397
22.1 Overview........................................................................................................................... 397
22.1.1 Features............................................................................................................. 397
22.1.2 Block Diagram.................................................................................................. 399
22.1.3 Pin Configuration ............................................................................................. 400
22.1.4 Register Configuration...................................................................................... 400
22.2 Register Descriptions........................................................................................................ 401
22.2.1 Receive Shift Register 1 (RSR1)...................................................................... 401
22.2.2 Receive Data Register 1 (RDR1)...................................................................... 401
22.2.3 Transmit Shift Register 1 (TSR1)..................................................................... 402
22.2.4 Transmit Data Register 1 (TDR1) .................................................................... 402
22.2.5 Serial Mode Register 1 (SMR1) ....................................................................... 403
22.2.6 Serial Control Register 1 (SCR1) ..................................................................... 406
22.2.7 Serial Status Register 1 (SSR1)........................................................................ 410
22.2.8 Bit Rate Register 1 (BRR1).............................................................................. 413
22.2.9 Serial Interface Mode Register 1 (SCMR1)...................................................... 420
22.2.10 Module Stop Control Register (MSTPCR)....................................................... 421
22.3 Operation .......................................................................................................................... 422
22.3.1 Overview .......................................................................................................... 422
22.3.2 Operation in Asynchronous Mode.................................................................... 424
22.3.3 Multiprocessor Communication Function ........................................................ 434

Rev. 1.0, 02/00, page xii of 19
22.3.4 Operation in Synchronous Mode...................................................................... 442
22.4 SCI Interrupts.................................................................................................................... 450
22.5 Usage Notes...................................................................................................................... 451
Section 23 I2C Bus Interface (IIC)................................................................................. 459
23.1 Overview........................................................................................................................... 459
23.1.1 Features............................................................................................................. 459
23.1.2 Block Diagram.................................................................................................. 460
23.1.3 Pin Configuration ............................................................................................. 461
23.1.4 Register Configuration...................................................................................... 462
23.2 Register Descriptions........................................................................................................ 463
23.2.1 I2C Bus Data Register (ICDR).......................................................................... 463
23.2.2 Slave Address Register (SAR).......................................................................... 466
23.2.3 Second Slave Address Register (SARX).......................................................... 468
23.2.4 I2C Bus Mode Register (ICMR)........................................................................ 469
23.2.5 I2C Bus Control Register (ICCR)...................................................................... 473
23.2.6 I2C Bus Status Register (ICSR)......................................................................... 480
23.2.7 Serial/Timer Control Register (STCR)............................................................. 484
23.2.8 DDC Switch Register (DDCSWR)................................................................... 485
23.2.9 Module Stop Control Register (MSTPCR)....................................................... 488
23.3 Operation .......................................................................................................................... 489
23.3.1 I2C Bus Data Format......................................................................................... 489
23.3.2 Master Transmit Operation............................................................................... 490
23.3.3 Master Receive Operation ................................................................................ 494
23.3.4 Slave Receive Operation................................................................................... 496
23.3.5 Slave Transmit Operation................................................................................. 499
23.3.6 IRIC Setting Timing and SCL Control............................................................. 500
23.3.7 Automatic Switching from Formatless Transfer to I2C
Bus Format Transfer......................................................................................... 502
23.3.8 Noise Canceler.................................................................................................. 503
23.3.9 Sample Flowcharts............................................................................................ 503
23.3.10 Initializing Internal Status................................................................................. 507
23.4 Usage Notes...................................................................................................................... 509
Section 24 A/D Converter................................................................................................. 513
24.1 Overview........................................................................................................................... 513
24.1.1 Features............................................................................................................. 513
24.1.2 Block Diagram.................................................................................................. 514
24.1.3 Pin Configuration ............................................................................................. 515
24.1.4 Register Configuration...................................................................................... 516
24.2 Register Descriptions........................................................................................................ 517
24.2.1 Software-Triggered A/D Result Register (ADR).............................................. 517
24.2.2 Hardware-Triggered A/D Result Register (AHR) ............................................ 517

Rev. 1.0, 02/00, page xiii of 19
24.2.3 A/D Control Register (ADCR)......................................................................... 518
24.2.4 A/D Control/Status Register (ADCSR)............................................................ 521
24.2.5 Trigger Select Register (ADTSR)..................................................................... 524
24.2.6 Port Mode Register 0 (PMR0).......................................................................... 524
24.2.7 Module Stop Control Register (MSTPCR)....................................................... 525
24.3 Interface to Bus Master..................................................................................................... 526
24.4 Operation .......................................................................................................................... 527
24.4.1 Software-Triggered A/D Conversion................................................................ 527
24.4.2 Hardware- or External-Triggered A/D Conversion.......................................... 528
24.5 Interrupt Sources............................................................................................................... 529
Section 25 Address Trap Controller (ATC)................................................................. 531
25.1 Overview........................................................................................................................... 531
25.1.1 Features............................................................................................................. 531
25.1.2 Block Diagram.................................................................................................. 531
25.1.3 Register Configuration...................................................................................... 532
25.2 Register Descriptions........................................................................................................ 532
25.2.1 Address Trap Control Register (ATCR)........................................................... 532
25.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0)................................................ 534
25.3 Precautions in Usage......................................................................................................... 535
25.3.1 Basic Operations............................................................................................... 535
25.3.2 Enabling............................................................................................................ 537
25.3.3 Bcc Instruction.................................................................................................. 537
25.3.4 BSR Instruction ................................................................................................ 541
25.3.5 JSR Instruction ................................................................................................. 542
25.3.6 JMP Instruction................................................................................................. 544
25.3.7 RTS Instruction................................................................................................. 545
25.3.8 SLEEP Instruction............................................................................................ 546
25.3.9 Competing Interrupt ......................................................................................... 550
Section 26 Servo Circuits.................................................................................................. 555
26.1 Overview........................................................................................................................... 555
26.1.1 Functions .......................................................................................................... 555
26.1.2 Block Diagram.................................................................................................. 556
26.2 Servo Port ......................................................................................................................... 557
26.2.1 Overview .......................................................................................................... 557
26.2.2 Block Diagram.................................................................................................. 557
26.2.3 Pin Configuration ............................................................................................. 560
26.2.4 Register Configuration...................................................................................... 561
26.2.5 Register Description ......................................................................................... 561
26.2.6 DFG/DPG Input Signals................................................................................... 565
26.3 Reference Signal Generators............................................................................................. 566
26.3.1 Overview .......................................................................................................... 566

Rev. 1.0, 02/00, page xiv of 19
26.3.2 Block Diagram.................................................................................................. 566
26.3.3 Register Configuration...................................................................................... 568
26.3.4 Register Description ......................................................................................... 569
26.3.5 Operation.......................................................................................................... 574
26.4 HSW (Head-switch) Timing Generator ............................................................................ 589
26.4.1 Overview .......................................................................................................... 589
26.4.2 Block Diagram.................................................................................................. 589
26.4.3 HSW Timing Generator Configuration ............................................................ 591
26.4.4 Register Configuration...................................................................................... 592
26.4.5 Register Description ......................................................................................... 592
26.4.6 Operation.......................................................................................................... 606
26.4.7 Interrupts........................................................................................................... 612
26.4.8 Cautions............................................................................................................ 613
26.5 High-Speed Switching Circuit for Four-Head Special Playback...................................... 614
26.5.1 Overview .......................................................................................................... 614
26.5.2 Block Diagram.................................................................................................. 614
26.5.3 Pin Configuration ............................................................................................. 615
26.5.4 Register Description ......................................................................................... 615
26.6 Drum Speed Error Detector .............................................................................................. 618
26.6.1 Overview .......................................................................................................... 618
26.6.2 Block Diagram.................................................................................................. 618
26.6.3 Register Configuration...................................................................................... 620
26.6.4 Register Description ......................................................................................... 621
26.6.5 Operation.......................................................................................................... 626
26.6.6 fHCorrection in Trick Play Mode ..................................................................... 628
26.7 Drum Phase Error Detector............................................................................................... 629
26.7.1 Overview .......................................................................................................... 629
26.7.2 Block Diagram.................................................................................................. 630
26.7.3 Register Configuration...................................................................................... 631
26.7.4 Register Description ......................................................................................... 632
26.7.5 Operation.......................................................................................................... 635
26.7.6 Phase Comparison ............................................................................................ 637
26.8 Capstan Speed Error Detector........................................................................................... 638
26.8.1 Overview .......................................................................................................... 638
26.8.2 Block Diagram.................................................................................................. 639
26.8.3 Register Configuration...................................................................................... 640
26.8.4 Register Description ......................................................................................... 641
26.8.5 Operation.......................................................................................................... 646
26.9 Capstan Phase Error Detector........................................................................................... 648
26.9.1 Overview .......................................................................................................... 648
26.9.2 Block Diagram.................................................................................................. 648
26.9.3 Register Configuration...................................................................................... 650
26.9.4 Register Description ......................................................................................... 651

Rev. 1.0, 02/00, page xv of 19
26.9.5 Operation.......................................................................................................... 654
26.10 X-Value and Tracking Adjustment Circuit....................................................................... 656
26.10.1 Overview .......................................................................................................... 656
26.10.2 Block Diagram.................................................................................................. 656
26.10.3 Register Description ......................................................................................... 658
26.11 Digital Filters .................................................................................................................... 661
26.11.1 Overview .......................................................................................................... 661
26.11.2 Block Diagram.................................................................................................. 662
26.11.3 Arithmetic Buffer ............................................................................................. 664
26.11.4 Register Configuration...................................................................................... 665
26.11.5 Register Description ......................................................................................... 666
26.11.6 Filter Characteristics......................................................................................... 674
26.11.7 Operations in Case of Transient Response ....................................................... 676
26.11.8 Initialization of Z-1 ............................................................................................ 676
26.12 Additional V Signal Generator ......................................................................................... 678
26.12.1 Overview .......................................................................................................... 678
26.12.2 Pin Configuration ............................................................................................. 679
26.12.3 Register Configuration...................................................................................... 679
26.12.4 Register Description ......................................................................................... 679
26.12.5 Additional V Pulse Signal ................................................................................ 681
26.13 CTL Circuit....................................................................................................................... 684
26.13.1 Overview .......................................................................................................... 684
26.13.2 Block Diagram.................................................................................................. 685
26.13.3 Pin Configuration ............................................................................................. 686
26.13.4 Register Configuration...................................................................................... 686
26.13.5 Register Description ......................................................................................... 687
26.13.6 Operation.......................................................................................................... 701
26.13.7 CTL Input Section ............................................................................................ 704
26.13.8 Duty Discriminator........................................................................................... 707
26.13.9 CTL Output Section.......................................................................................... 713
26.13.10 Trapezoid Waveform Circuit............................................................................. 716
26.13.11 Note on CTL Interrupt...................................................................................... 717
26.14 Frequency Dividers........................................................................................................... 718
26.14.1 Overview .......................................................................................................... 718
26.14.2 CTL Frequency Divider.................................................................................... 718
26.14.3 CFG Frequency Divider ................................................................................... 722
26.14.4 DFG Noise Removal Circuit............................................................................. 731
26.15 Sync Signal Detector......................................................................................................... 733
26.15.1 Overview .......................................................................................................... 733
26.15.2 Block Diagram.................................................................................................. 734
26.15.3 Pin Configuration ............................................................................................. 735
26.15.4 Register Configuration...................................................................................... 735
26.15.5 Register Description ......................................................................................... 736

Rev. 1.0, 02/00, page xvi of 19
26.15.6 Noise Detection ................................................................................................ 744
26.15.7 Activation of the Sync Signal Detector ............................................................ 747
26.16 Servo Interrupt.................................................................................................................. 748
26.16.1 Overview .......................................................................................................... 748
26.16.2 Register Configuration...................................................................................... 748
26.16.3 Register Description ......................................................................................... 748
Section 27 Sync Separator for OSD and Data Slicer................................................ 757
27.1 Overview........................................................................................................................... 757
27.1.1 Features............................................................................................................. 758
27.1.2 Block Diagram.................................................................................................. 758
27.1.3 Pin Configuration ............................................................................................. 760
27.1.4 Register Configuration...................................................................................... 760
27.2 Register Description.......................................................................................................... 761
27.2.1 Sync Separation Input Mode Register (SEPIMR) ............................................ 761
27.2.2 Sync Separation Control Register (SEPCR)..................................................... 765
27.2.3 Sync Separation AFC Control Register (SEPACR) ......................................... 768
27.2.4 Horizontal Sync Signal Threshold Register (HVTHR) .................................... 770
27.2.5 Vertical Sync Signal Threshold Register (VVTHR)......................................... 773
27.2.6 Field Detection Window Register (FWIDR).................................................... 775
27.2.7 H Complement and Mask Timing Register (HCMMR) ................................... 777
27.2.8 Noise Detection Counter (NDETC).................................................................. 779
27.2.9 Noise Detection Level Register (NDETR)....................................................... 780
27.2.10 Data Slicer Detection Window Register (DDETWR) ...................................... 781
27.2.11 Internal Sync Frequency Register (INFRQR)................................................... 783
27.3 Operation .......................................................................................................................... 784
27.3.1 Selecting Source Signals for Sync Separation.................................................. 784
27.3.2 Vsync Separation.............................................................................................. 790
27.3.3 Hsync Separation.............................................................................................. 791
27.3.4 Field Detection ................................................................................................. 792
27.3.5 Noise Detection ................................................................................................ 792
27.3.6 Automatic Frequency Controller (AFC)........................................................... 793
27.3.7 Module Stop Control Register (MSTPCR)....................................................... 797
Section 28 Data Slicer........................................................................................................ 799
28.1 Overview........................................................................................................................... 799
28.1.1 Features............................................................................................................. 799
28.1.2 Block Diagram.................................................................................................. 800
28.1.3 Pin Configuration ............................................................................................. 801
28.1.4 Register Configuration...................................................................................... 802
28.1.5 Data Slicer Use Conditions............................................................................... 802
28.2 Register Description.......................................................................................................... 803
28.2.1 Slice Even- (Odd-) Field Mode Register (SEVFD, SODFD)........................... 803

Rev. 1.0, 02/00, page xvii of 19
28.2.2 Slice Line Setting Registers 1 to 4 (SLINE1 to SLINE4)................................. 807
28.2.3 Slice Detection Registers 1 to 4 (SDTCT1 to SDTCT4).................................. 808
28.2.4 Slice Data Registers 1 to 4 (SDATA1 to SDATA4)......................................... 811
28.2.5 Module Stop Control Register (MSTPCR)....................................................... 812
28.2.6 Monitor Output Setting Register (DOUT)........................................................ 813
28.3 Operation .......................................................................................................................... 814
28.3.1 Slice Line Specification.................................................................................... 814
28.3.2 Slice Sequence.................................................................................................. 817
Section 29 On-Screen Display (OSD)........................................................................... 819
29.1 Overview........................................................................................................................... 819
29.1.1 Features............................................................................................................. 819
29.1.2 Block Diagram.................................................................................................. 821
29.1.3 Pin Configuration ............................................................................................. 822
29.1.4 Register Configuration...................................................................................... 823
29.1.5 TV Formats and Display Modes....................................................................... 824
29.2 Description of Display Functions...................................................................................... 824
29.2.1 Superimposed Mode and Text Display Mode .................................................. 824
29.2.2 Character Configuration ................................................................................... 825
29.2.3 On-Screen Display Configuration .................................................................... 826
29.3 Settings in Character Units ............................................................................................... 827
29.3.1 Character Configuration ................................................................................... 827
29.3.2 Character Colors............................................................................................... 827
29.3.3 Halftones/Cursors............................................................................................. 828
29.3.4 Blinking............................................................................................................ 829
29.3.5 Button Display.................................................................................................. 830
29.3.6 Character Data ROM (OSDROM).................................................................... 831
29.3.7 Display Data RAM (OSDRAM)....................................................................... 833
29.4 Settings in Row Units ....................................................................................................... 838
29.4.1 Button Patterns ................................................................................................. 838
29.4.2 Display Enlargement ........................................................................................ 838
29.4.3 Character Brightness......................................................................................... 838
29.4.4 Cursor Color, Brightness, Halftone Levels....................................................... 838
29.4.5 Row Registers (CLINEn, n = rows 1 to 12)...................................................... 840
29.5 Settings in Screen Units.................................................................................................... 845
29.5.1 Display Positions.............................................................................................. 845
29.5.2 Turning the OSD Display On and Off.............................................................. 846
29.5.3 Display Method ................................................................................................ 846
29.5.4 Blinking Period................................................................................................. 846
29.5.5 Borders ............................................................................................................. 847
29.5.6 Background Color and Brightness.................................................................... 847
29.5.7 Character, Cursor, and Background Chroma Saturation................................... 847
29.5.8 Display Position Registers (HPOS and VPOS) ................................................ 848

Rev. 1.0, 02/00, page xviii of 19
29.5.9 Screen Control Register (DCNTL)................................................................... 850
29.6 Other Settings.................................................................................................................... 855
29.6.1 TV Format ........................................................................................................ 855
29.6.2 Display Data RAM Control.............................................................................. 855
29.6.3 Timing of OSD Display Updates Using Register Rewriting ............................ 855
29.6.4 4fsc/2fsc............................................................................................................ 855
29.6.5 OSDV Interrupts............................................................................................... 855
29.6.6 OSD Format Register (DFORM)...................................................................... 856
29.7 Digital Output ................................................................................................................... 860
29.7.1 R, G, and B Outputs.......................................................................................... 860
29.7.2 YCO and YBO Outputs.................................................................................... 863
29.7.3 Digital Output Specification Register (DOUT)................................................ 864
29.7.4 Module Stop Control Register (MTSTPCR) .................................................... 866
29.8 Notes on OSD Font Creation ............................................................................................ 868
29.8.1 Note 1 on Font Creation (Font Width).............................................................. 868
29.8.2 Note 2 on Font Creation (Borders)................................................................... 868
29.8.3 Note 3 on Font Creation (Blinking).................................................................. 870
29.8.4 Note 4 on Font Creation (Buttons) ................................................................... 871
29.9 OSD Oscillator, AFC, and Dot Clock............................................................................... 872
29.9.1 Sync Signals .................................................................................................... 872
29.9.2 AFC Circuit ...................................................................................................... 872
29.9.3 Dot Clock.......................................................................................................... 872
29.9.4 4/2fsc ................................................................................................................ 873
29.10 OSD Operation in CPU Operation Modes........................................................................ 875
29.11 Character Data ROM (OSDROM) Access by CPU.......................................................... 876
29.11.1 Serial Timer Control Register (STCR)............................................................. 876
Section 30 Electrical Characteristics.............................................................................. 877
30.1 Absolute Maximum Ratings ............................................................................................. 877
30.2 Electrical Characteristics of HD6432199, HD6432198, HD6432197, and
HD6432196....................................................................................................................... 878
30.2.1 DC Characteristics of HD6432199, HD6432198, HD6432197,
and HD6432196................................................................................................ 878
30.2.2 Allowable Output Currents of HD6432199, HD6432198, HD6432197,
and HD6432196................................................................................................ 885
30.2.3 AC Characteristics of HD6432199, HD6432198, HD6432197,
and HD6432196................................................................................................ 886
30.2.4 Serial Interface Timing of HD6432199, HD6432198, HD6432197,
and HD6432196................................................................................................ 889
30.2.5 A/D Converter Characteristics of HD6432199, HD6432198, HD6432197,
and HD6432196................................................................................................ 893
30.2.6 Servo Section Electrical Characteristics of HD6432199, HD6432198,
HD6432197, and HD6432196.......................................................................... 894