ON Semiconductor AX5045 Owner's manual

©Semiconductor Components Industries, LLC, 2019
March, 2021 − Rev. 1 1Publication Order Number:
AND9902/D
AND9902/D
AX5045 Programming
Manual
Ultra-Low Power Narrow-Band Sub GHz
(60−1050 MHz) RF Transceiver with
Integrated +23 dBm High Power Amplifier
OVERVIEW
AX5045 is a true single chip low-power CMOS
transceiver for narrow band applications. A fully integrated
VCO support most carrier frequencies from 60 MHz to
1050 MHz. The on-chip transceiver consists of a fully
integrated RF front-end with modulator, and demodulator.
Base band data processing is implemented in an advanced
and flexible communication controller that enables user
friendly communication via the SPI interface.
An on-chip low power oscillator as well as Wake-on-radio
enable very low power standby applications. Figure 1 shows
the block diagram of the AX5045.
Figure 1. Functional Block Diagram of the AX5045
AX5045
5
RX_P
6
RX_N
IF Filter &
AGC PGAs
AGC
Crystal
Oscillator
typ.
16 MHz
FOUT
FXTAL
Communication Controller &
Serial Interface
Divider
ADC
Digital IF
channel
filter
LNA
De-
modulator
Encoder
Framing
FIFO
Modulator
Mixer
28
CLKP
27
CLKN
Chip configuration
13
SYSCLK
VDD_IO
Voltage
Regulator
POR
3
TX_P
Low Power
Oscillator
640 Hz/10kHz
Forward Error
Correction
25
GPADC1
26
GPADC2
12
DATA
DCLK
11
8
FILT
VDD_ANA
14
SEL
15
CLK
16
MISO
17
MOSI
19
IRQ
20
PWRAMP
21
ANTSEL
23,1
23
Radio Controller
timing and packet
References
Wake on Radio
Registers
SPI
RF Frequency
Generation
Subsystem
RF Output
60 MHz –
1.05 GHz
PA
VDD_IO
Voltage
Regulator
VCHOKE
27
1,23
4
TX_N
7
Radio Controller
timing and packet
handling
APPLICATION NOTE
www.onsemi.com

AND9902/D
www.onsemi.com
2
Table of Contents
Overview 1...............................................................................................
FIFO Operation 7.........................................................................................
Programming the Chip 12..................................................................................
Register Overview 21......................................................................................
Register Details 33........................................................................................
References 82............................................................................................

AND9902/D
www.onsemi.com
3
Connecting the AX5045 to an AX8052F100 or other
Microcontroller
The AX5045 can easily be connected to an AX8052F100
or any other microcontroller. The microcontroller
communicates with the AX5045 via a register file that is
implemented in the AX5045 and that can be accessed
serially via an industry standard Serial Peripheral Interface
(SPI) protocol.
Reset is performed by the integrated power-on-reset
(POR) block and can be performed manually via the register
file.
The AX5045 sends and receives data via the SPI port in
frames. This standard operation mode is called frame mode.
In frame mode, the internal communication controller
performs frame delimiting, and data is received and
transmitted via a 256 Byte FIFO, accessible via the register
file. The FIFO is shared between receive and transmit.
Figure 2 shows the corresponding diagram. Connecting the
interrupt line is highly recommended, though not strictly
required. It is also recommended to connect the SYSCLK
line, which can be programmed to provide a copy of the
precise crystal clock of the AX5045. Once set up, the
Microcontroller can directly run on that clock or use it to
calibrate its internal oscillators.
AX5045
SEL
AX8052F100
or
other mC
28 27 26 25 24 23 22
1
2
3
4
5
6
7
21
20
19
18
17
16
15
8 9 10 11 12 13 14
RESET_N
PB7/DBG_CLK
DBG_EN
PB6/DBG_DATA
PB5/U0RX/T1OUT
PB4/U0TX/T1CLK
PB3/OC0/T2CLK/EXTIRQ1/DSWAKE
RIRQ/PR5
VDD_CORE
RMOSI/PR4
RMISO/PR3
RCLK/PR2
RSEL/PR0
RSYSCLK/PR1
OMPO0/U0RX/SMISO/PC3
U 0 T X /SM O S I/P C 2
OMPO1/T0CLK/SSCK/PC1
XTIRQ0/T0OUT/SSEL/PC0
EXTIRQ0/IC1/U1TX/PB0
OC1/U1RX/PB1
T2OUT/IC0/PB2
PA5/ADC5/IC0/U1TX/COMPI10 PA4/ADC4/T1CLK/COMPO0/LPXTA PA3/ADC3/T1OUT/LPXTALP PA 2 /AD C 2 /O C 0 /U 1 R X/C O M P I0 0 PA1/ADC1/T0CLK/OC1/XTALP PA 0 /AD C 0 /T 0 O U T /IC 1 /X TA L N VDD_IO
IRQ
MOSI
MISO
CLK
SYSCLK
Figure 2. Connecting AX5045 to AX8052F100 or other mC
VDD_IO
VCHOKE
TX_P
TX_N
RX_P
RX_N
VDD_ANA
ANTSEL
PWRAMP
IRQ
NC
MOSI
MISO
CLK
FILT
NC NC
DATA
SYSCLK
CLKP CLKN NC VDD_IO
DCLK
28 27 26 25 24 23 22
810111213149
1
2
3
4
5
6
7
21
20
19
18
17
16
15
SEL
GPADC2 GPADC1
NC
GND
center pad

AND9902/D
www.onsemi.com
4
Pin Function Descriptions
Table 1. PIN FUNCTION DESCRIPTION
Symbol
Pin(s)
Type
Description
VDD_IO
1
P
Power supply 3.0 V – 3.6 V
VCHOKE
2
P
Regulator Output to External PA choke inductors
TX_P
3
A
Differential TX antenna output
TX_N
4
A
Differential TX antenna output
RX_P
5
A
Differential RX antenna input
RX_N
6
P
Differential RX antenna input
VDD_ANA
7
P
Analog power output, decoupling
FILT
8
A
Optional synthesizer filter
NC
9
A
Not used
NC
10
A
Not used
DATA
11
I/O
In wire mode: Data input/output
Can be programmed to be used as a general purpose I/O pin Selectable
internal 65 kWpull−up resistor
DCLK
12
I/O
In wire mode: Clock output
Can be programmed to be used as a general purpose I/O pin Selectable
internal 65 kWpull−up resistor
SYSCLK
13
I/O
Default functionality: Crystal oscillator (or divided) clock output Can be pro-
grammed to be used as a general purpose I/O pin Selectable internal 65 kW
pull−up resistor
SEL
14
I
Serial peripheral interface select
CLK
15
I
Serial peripheral interface clock
MISO
16
O
Serial peripheral interface data output
MOSI
17
I
Serial peripheral interface data input
NC
18
N
Must be left unconnected
IRQ
19
I/O
Default functionality: Transmit and receive interrupt
Can be programmed to be used as a general purpose I/O pin Selectable
internal 65 kWpull−up resistor
PWRAMP
20
I/O
Default functionality: Power amplifier control output
Can be programmed to be used as a general purpose I/O pin Selectable
internal 65 kWpull−up resistor
ANTSEL
21
I/O
Default functionality: Diversity antenna selection output
Can be programmed to be used as a general purpose I/O pin Selectable
internal 65 kWpull−up resistor
NC
22
N
Must be left unconnected
VDD_IO
23
P
Power supply 3.0 V – 3.6 V
NC
24
N
Must be left unconnected
GPADC1
25
A
GPADC input, must be connected to GND if not used
GPADC2
26
A
GPADC input, must be connected to GND if not used
CLKN
27
A
Crystal oscillator input/output. Leave unconnected when using TCXO
CLKP
28
A
Crystal oscillator input/output. TCXO input.
GND
Center pad
P
Ground on center pad of QFN, must be connected
NOTE: All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible and 5 V tolerant.
A = analog input
I = digital input signal
O = digital output signal
I/O = digital input/output signal
N = not to be connected
P = power or ground

AND9902/D
www.onsemi.com
5
SPI Register Access
Registers are accessed via a synchronous Serial Peripheral
Interface (SPI). Most Registers are 8 bits wide and accessed
using the waveforms as detailed in Figure 3. These
waveforms are compatible to most hardware SPI master
controllers, and can easily be generated in software. MISO
changes on the falling edge of CLK, while MOSI is latched
on the rising edge of CLK.
R/W A7
S7
A6 A5 A4 A3 A2 A1
S6 S5 S4 S3 S2 S1
A0
S0
A11 A10 A9
S14 S13 S12 S11 S9
A8
S8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0S10
SS
SCK
MOSI
MISO
111
Figure 3. SPI 8bit Long Address Read/Write Access
The most important registers are at the beginning of the
address space, i.e. at addresses less than 0x70. These registers can be accessed more efficiently using the short address form, which is detailed in Figure 4.
Figure 4. SPI 8bit Read/Write Access
Some registers are longer than 8 bits. These registers can
be accessed more quickly than by reading and writing
individual 8 bit parts. This is illustrated in Figure 5. Accesses
are not limited by 16 bits either, reading and writing data
bytes can be continued as long as desired. After each byte,
the address counter is incremented by one. Also, this access
form also works with long addresses.
R/W A6 A5 A4 A3 A2 A1 A0
S14 S13 S12 S11 S10 S9 S8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SS
SCK
MOSI
MISO
A A+1
Figure 5. SPI 16bit Read/Write Access
During the address phase of the access, the chip outputs
the most important status bits. This feature is designed to
speed up software decision on what to do in an interrupt
handler. The table below shows which register bit is
transmitted during the status timeslots.
Table 2. SPI STATUS BITS
SPI Bit Cell
Status
Register Bit
0
−
1 (when transitioning out of deep sleep, this bit transitions from 0
→
1 when the power becomes ready)
1
S14
PLL LOCK
2
S13
FIFO OVER
3
S12
FIFO UNDER
4
S11
THRESHOLD FREE ( FIFO Free
>
FIFO threshold)
5
S10
THRESHOLD COUNT (FIFO count
>
FIFO threshold)
6
S9
FIFO FULL
7
S8
FIFO EMPTY
8
S7
PWRGOOD (not BROWNOUT)
9
S6
PWR INTERRUPT PENDING
10
S5
RADIO EVENT PENDING
11
S4
XTAL OSCILLATOR RUNNING

AND9902/D
www.onsemi.com
6
Table 2. SPI STATUS BITS (continued)
SPI Bit Cell Register BitStatus
12
S3
WAKEUP INTERRUPT PENDING
13
S2
LPOSC INTERRUPT PENDING
14
S1
GPADC INTERRUPT PENDING
15
S0
undefined
Note that bit cells 8−15 (S7…S0) are only available in two
address byte SPI access formats.
Deep Sleep
The chip can be programmed into deep sleep mode. In
deep sleep mode, the chip is completely switched off, which
results in very low leakage power. All registers loose their
programming.
To enter deep sleep mode, write the deep sleep encoding
into bits 3:0 of PWRMODE. At the rising edge of the SEL
line, the chip will enter deep sleep mode.
To exit deep sleep mode, lower the SEL line. This will
initiate startup and reset of the chip. Then poll the MISO
line. The MISO line will be held low during initialization,
and will rise to high at the end of the initialization, when the
chip becomes ready for further operation.
Address Space
The address space has been allocated as follows.
Addresses from 0x000 to 0x06F are reserved for “dynamic
registers”, i.e. registers that are expected to be frequently
accessed during normal operation, as they can be efficiently
accessed using single address byte SPI accesses. Addresses
from 0x070 to 0x0FF have been left unused (they could only
be accessed using the two address byte SPI format).
Addresses from 0x100 to 0x1FF have been reserved for
physical layer parameter registers, for example receiver,
transmitter, PLL, crystal oscillator. Addresses from 0x200 to
0x2FF have been reserved for medium access parameters,
such as framing, packet handling. Addresses from 0x300 to
0x3FF have been reserved for special functions, such as
GPADC.

AND9902/D
www.onsemi.com
7
FIFO OPERATION
The AX5045 features a 256 Byte FIFO. The same FIFO
is used for both reception and transmission. During transmit,
only the write port is accessible by the microcontroller.
During receive, only the read port is accessible by the
microcontroller. Otherwise, both ports are accessible
through the register file.
In order to prevent transmitting premature data, the FIFO
contains three pointers. Data is read at the read pointer, up
to the write pointer. Data is written to the write ahead pointer.
The write pointer is not updated when data is written,
therefore, new data is not immediately visible to the
consumer. Writing the COMMIT command to the
FIFOSTAT register copies the write ahead pointer to the
write pointer, thus making the written data visible to the
receiver. Writing the ROLLBACK command to the
FIFOSTAT register sets the write ahead pointer to the write
pointer, thus discarding data written to the FIFO. During
transmit, this means that the transmitter will only consider
data written to the FIFO after the commit command. During
receive, this feature is used by the receiver to store packet
data before it is known whether the CRC check passes.
FIFOCOUNT reports the number of bytes that can be read
without causing an underflow. FIFOFREE reports the
number of bytes that can be written without causing an
overflow. FIFOCOUNT and FIFOFREE do not add up to
256 Bytes whenever there are uncommitted bytes in the
FIFO. Figure 6 illustrates this.
Figure 6. FIFO Pointer
Write ahead pointer
Write pointer
FIFOCOUNT
256−FIFOFREE
Read pointer
FIFO Chunk Encoding
In order to distinguish meta-data (such as RSSI) from
receive or transmit data, FIFO contents are organized as
chunks. Chunks consist of a header that encodes the chunk
length as well as the payload data format.
Each chunk starts with a single byte header. The header
encodes the length of a chunk, and indicates the data it
contains. The top 3 bits encode the length (or optionally refer
to an additional length byte after the header byte), and the
bottom 5 bits indicate what payload data the chunk contains.
The following table lists the encoding of the length bits (top
3 bits of the first chunk header byte). Figure 7 shows the
chunk header byte encoding.
76543210
Chunk
payload
size
Chunk
payload
data format
Figure 7. FIFO Header byte Format
The following table lists the chunk payload size encoding:
Table 3. CHUNK PAYLOAD SIZE ENCODING
Top Bits
Chunk Payload Size
000
No payload
001
Single byte payload
010
Two byte payload
011
Three byte payload

AND9902/D
www.onsemi.com
8
Table 3. CHUNK PAYLOAD SIZE ENCODING (continued)
Top Bits Chunk Payload Size
100
Invalid
101
Invalid
110
Invalid
111
Variable length payload; payload size is encoded in the following length byte the length byte is part of
the header (and not included in length), everything after the length byte is included in the length
The following table lists the chunk types and their
encodings. The Hdr Byte column lists the complete FIFO
Chunk Header Byte, consisting of the length and data format
encodings.
Table 4. CHUNK TYPES AND THEIR ENCODINGS
Name Dir
Hdr. Byte
Description
7−0
No Payload Commands
NOP
T
00000000
No Operation
FIFOIRQ
T
00000011
Trigger a Radiocontrol
interrupt
One Byte Payload Commands
RSSI
R
00110001
RSSI
TXCTRL
T
00111100
Transmit Control
(Antenna, Power Amp)
Two Byte Payload Commands
FREQOFFS
R
01010010
Frequency Offset
ANTRSSI2
R
01010101
Background Noise
Calculation RSSI
Three Byte Payload Commands
REPEATDATA
T
01100010
Repeat Data
TIMER
TR
01110000
Timer
RFFREQOFFS
R
01110011
RF Frequency Offset
DATARATE
R
01110100
Datarate
ANTRSSI3
R
01110101
Antenna Selection RSSI
Variable Length Payload Commands
DATA
TR
11100001
Data
TXPWR
T
11111101
Transmit Power
Direction: T = Transmit, R = Receive
NOP Command
Table 5. NOP COMMAND
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
The NOP command will be discarded without effect by
the transmitter. The receiver will not generate NOP
commands.
FIFOIRQ Command
Table 6. FIFOIRQ COMMAND
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
The FIFOIRQ command triggers an interrupt if bit
IRQMRADIOCTRL is set in register IRQMASK0 and bit
REVMFIFOIRQCMDDET is set in register
RADIOEVENTMASK. This feature allows to track TX
events as for example completion of preamble transmission.
To clear the interrupt, register RADIOEVENTREQ0 has
to be read.
RSSI Command
Table 7. RSSI COMMAND
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
1
RSSI
The RSSI command will only be generated by the receiver
at the end of a packet if bit ST RSSI is set in register
PKTSTOREFLAGS. The encoding is the same as that of the
RSSI register.
TXCTRL Command
Table 8. TXCTRL COMMAND
7
6
5
4
3
2
1
0
0
0
1
1
1
1
0
0
0
SETTX TXSE TXDIFF SETANT ANTSTATE SETPA PASTATE
The TXCTRL command allows certain aspects of the
transmitter to be changed on the fly. If SETTX is set, TXSE
and TXDIFF are copied into the register MODCFGA. If
SETANT is set, ANTSTATE is copied into register
DIVERSITY. If SETPA is set, PASTATE is copied into
register PWRAMP.

AND9902/D
www.onsemi.com
9
FREQOFFS Command
Table 9. FREQOFFS COMMAND
7
6
5
4
3
2
1
0
0
1
0
1
0
0
1
0
FREQOFFS1
FREQOFFS0
The FREQOFFS command will only be generated by the
receiver at the end of a packet if bit ST FOFFS is set in
register PKTSTOREFLAGS. The encoding is the same as
that of the TRKFREQ register.
ANTRSSI2 Command
Table 10. ANTRSSI2 COMMAND
7
6
5
4
3
2
1
0
0
1
0
1
0
1
0
1
RSSI
BGNDNOISE
The ANTRSSI2 command will be generated by the
receiver when it is idle if bit ST ANT RSSI is set in register
PKTSTOREFLAGS. If DIVENA is set in register
DIVERSITY, the ANTRSSI3 command is generated
instead. The encoding of the RSSI field is the same as that
of the RSSI register. The BGNDNOISE field contains an
estimate of the background noise.
REPEATDATA Command
Table 11. REPEATDATA COMMAND
7
6
5
4
3
2
1
0
0
1
1
0
0
0
1
0
0
DIBITSYNC
UNENC
RAW
NOCRC
RESIDUE
PKTEND
PKTSTART
REPEATCNT
DATA
The REPEATDATA command allows the efficient
transmission of repetitive data bytes. The DATA byte given
in the payload is repeated REPEATCNT times. See DATA
command for a description of the flag byte. This command
is especially handy for constructing preambles.
TIMER Command
Table 12. TIMER COMMAND
7
6
5
4
3
2
1
0
0
1
1
1
0
0
0
0
TIMER2
TIMER1
TIMER0
This command enables exact packet timing, e.g. for
frequency hopping systems.
In TX mode, upon detection of a TIMER command, the
transmitter pauses until the internal timer (accessible via
TIMER register) reaches the value given by the payload. A
detailed documentation of this function can be found under
the description of register RCTRLTIMESTAMP.
In RX mode, the TIMER command will be generated by
the receiver at the start/end of a packet if bit ST TIMER
and/or ST TIMER PKTEND is set in register
PKTSTOREFLAGS. The payload is a copy of the internal
timer (i.e. the current value of the TIMER register).
RFFREQOFFS Command
Table 13. RFFREQOFFS COMMAND
7
6
5
4
3
2
1
0
0
1
1
1
0
0
1
1
RFFREQOFFS2
RFFREQOFFS1
RFFREQOFFS0
The RFFREQOFFS command will only be generated by
the receiver at the end of a packet if bit ST RFOFFS is set in
register PKTSTOREFLAGS. The encoding is the same as
that of the TRKRFFREQ register.
DATARATE Command
Table 14. DATARATE COMMAND
7
6
5
4
3
2
1
0
0
1
1
1
0
1
0
0
DATARATE2
DATARATE1
DATARATE0
The DATARATE command will only be generated by the
receiver at the end of a packet if bit ST DR is set in register
PKTSTOREFLAGS. The encoding is the same as that of the
TRKDATARATE register.

AND9902/D
www.onsemi.com
10
ANTRSSI3 Command
Table 15. ANTRSSI3 COMMAND
7
6
5
4
3
2
1
0
0
1
1
1
0
1
0
1
ANTORSSI2
ANTORSSI1
ANTORSSI0
The ANTRSSI3 command will be generated by the
receiver when it is idle if bit ST ANT RSSI is set in register
PKTSTOREFLAGS. If DIVENA is not set in register
DIVERSITY, the ANTRSSI2 command is generated
instead. The encoding of the ANT0RSSI and ANT1RSSI
fields are the same as that of the RSSI register.
The BGNDNOISE field contains an estimate of the
background noise.
DATA Command
The DATA command transports actual transmit and
receive data. While the basic format is the same for transmit
and receive, the semantics of the flag byte differs.
Table 16. TRANSMIT DATA FORMAT
7
6
5
4
3
2
1
0
1
1
1
0
0
0
0
1
LENGTH
0
DIBITSYNC
UNENC
RAW
NOCRC
RESIDUE
PKTEND
PKTSTART
DATA
LENGTH includes the flags byte as well as all DATA
bytes.
Setting RAW to one causes the DATA to bypass the
framing mode, but still pass through the encoder.
Setting UNENC to one causes the DATA to bypass the
framing mode, as well as the encoder, except for inversion.
UNENC has priority over RAW.
Setting NOCRC suppresses the generation of the CRC
bytes.
Setting RESIDUE allows the transmission of a number of
data bits that is not a multiple of eight. All but the last data
byte are transmitted as if RESIDUE was not set. The last
byte however contains only 7 bits or less. The transmitter
looks for the highest bit set. This is considered the stop bit.
Only bits below the stop bit are transmitted. If the
MSBFIRST in register PKTADDRCFG is set, the algorithm
is reversed, i.e. the lowest bit set is considered the stop bit
and bits above the stop bit are transmitted.
PKTSTART and PKTEND bits enable the transmission of
packets that are larger than the FIFO size. If PKTSTART is
set, the radio packet starts at the beginning of the DATA
command payload. If PKTEND is set, the radio packet ends
at the end of the DATA command payload. If PKTSTART is
not set, this command is the continuation of a previous
DATA command. If PKTEND is not set, the packet is
continued with the next DATA command.
Setting DIBITSYNC causes the DATA bytes to be aligned
to DiBit boundaries in 4−FSK mode.
For example, to transmit 20 bits of an alternating 0−1
pattern as a preamble, the following bytes should be written
to the FIFO (MSBFIRST = 0 in register PKTADDRCFG is
assumed):
Table 17. FIFO COMMAND
0xE1
FIFO Command
0x04
Length Byte
0x24
Flag Byte: Unencoded, to ensure 0−1 remains 0−1, and Residue set, because the number of bits
transmitted is not a multiple of 8
0xAA
Alternating 0−1 bits
0xAA
Alternating 0−1 bits
0x1A
Alternating 0−1 bits; Bit 4 is the “Stop” bit
Table 18. RECEIVE DATA FORMAT
7
6
5
4
3
2
1
0
1
1
1
0
0
0
0
1
LENGTH
SYNCWD
ABORT
SIZEFAIL
ADDRFAIL
CRCFAIL
RESIDUE
PKTEND
PKTSTART
DATA