Emulex SC03/B1 User manual

SC03/Bl
RM03/RM05/RM80 COMPATIBLE
DISK CONTROLLER
TECHNICAL MANUAL
EMULEX
3545 Harbor Boulevard
Costa Mesa, California 92626
[phone] TWX 910-595-2521
SC0351001-00 Rev E
November, 1987

Copyright (C) 1982 Emulex Corporation
The information in this manual is for information purposes and is
subject to change without notice.
Emulex Corporation assumes no responsibility for any errors which
may appear in the manual.
Printed in U.S.A.

Section 1
Section 2
1.1
1.1.1
1.2
1. 2 .1
1.3
1. 3 .1
1. 3. 2
1. 3. 3
1. 3 .4
1. 3. 5
1. 3. 6
1. 3. 7
1. 3. 8
1.4
1.4.1
1.4. 2
1.4. 3
1.4.4
2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2
2.2.3
2.2.4
2.2.5
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.2
2.3.2.1
2.3.2.2
2.3.2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.4.1
TABLE OF CONTENTS
INTRODUCTION
SCOPE
Register Addresses in this Manual
OVERVIEW
General Description
FEATURES
Microprocessor Design
Packaging
Self-Test
Buffering
Error Correction
Dual Port Mode
Dual Access Mode
Option and Configuration Switches
FUNCTIONAL COMPATIBILITY
Media Compatibility
Disk Mapping
Diagnostics
Operating Systems
GENERAL DESCRIPTION
CONTROLLER ORGANIZATION
PHYSICAL DESCRIPTION
Connectors
A Cable Connector
B Cable Connector
Test Connectors
Switches
LED Indicator
Firmware PROMs
Bootstrap PROMs
INTERFACES
Disk Interface
A Cable
B Cable
Q-Bus Interface
Interrupt Priority Level
Register Address
DCOK and INIT Signals
DISK FORMAT
Disk Pack Organization
Mapping
Sector Organization
Header
Header Description
iii
1-1
1-1
1-1
1-1
1-1
1-1
1-1
1-2
1-2
1-2
1-2
1-2
1-2
1-3
1-3
1-3
1-3
1-3
2-1
2-1
2-4
2-4
2-4
2-4
2-4
2-4
2-5
2-5
2-5
2-5
2-5
2-7
2-7
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-11
2-11

Section 3
2.4.4.2
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.4.1
3.4.4.2
3.4.4.3
3.4.4.4
3.5
3.5.1
3.5.2
3.6
3.6.l
3.6.2
3.6.3
3.7
3.7.1
3.7.2
Header Field Handling
GENERAL PROGRAMMING INFORMATION
Clearing the Controller
Interrupt Conditions
Termination of Data Transfers
Ready Bits
22-Bit Memory Addressing
Line Time Clock (LTC)
Bootstrap Routines
DUAL CONTROLLER OPERATION
Dual Port Drives
Unseized State
Seized State
Returning to the Unseized State
DEC Compatibility
Dual Port Drives in a Single Port
Mode
Dual Access Mode
Dual Port Drives Busy Signal
INSTALLATION
INSPECTION
DISK DRIVE PREPARATION
Drive Placement
Local/Remote
Sectoring
Index and Sector Pulse Selection
Unit Addressing
Lark Drive Configuration
SYSTEM PREPARATION
Powering Down the System
CONTROLLER SETUP
Controller Address Selection
Interrupt Vector Address
Drive Configuration Selection
Options
Q-Bus Terminator Option
Bootstrap PROM Option
22-Bit Memory Addressing
Line Time Clock Option
PHYSICAL INSTALLATION
Slot Selection
Mounting
CABLING
A Cable
B Cable
Grounding
TESTING
Self-Test
Register Examination
iv
2-11
2-11
2-11
2-12
2-12
2-13
2-13
2-14
2-14
2-14
2-15
2-15
2-15
2-15
2-16
2-16
2-17
2-17
3-1
3-1
3-1
3-1
3-2
3-2
3-2
3-2
3-2
3-2
3-2
3-4
3-4
3-4
3-4
3-5
3-5
3-6
3-6
3-6
3-6
3-7
3-7
3-7
3-8
3-8
3-8
3-8
3-9

Section 4
Section 5
3.7.3
3.7.4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
5.1
5 .1.1
5 .1. 2
5 .1. 3
5 .1.4
5 .1. 5
5 .1. 6
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.4
5.4.1
5.4.2
Hardware Formatting the Disk
Diagnostics
CONTROLLER REGISTERS
CONTROL/ STATUS REGISTER 1 (RMCSl)
WORD COUNT REGISTER (RMWC)
Q-BUS ADDRESS REGISTER (RMBA)
DISK ADDRESS REGISTER (RMDA)
CONTROL/STATUS REGISTER 2 (RMCS2)
DRIVE STATUS REGISTER (RMDS)
ERROR REGISTER 1 (RMERl)
ATTENTION SUMMARY REGISTER (RMAS)
LOOK-AHEAD REGISTER (RMLA)
DATA BUFFER (RMDB)
MAINTENANCE REGISTER 1 (RMMRl)
DRIVE TYPE REGISTER (RMDT)
SERIAL NUMBER REGISTER (RMSN)
OFFSET REGISTER (RMOF)
DESIRED CYLINDER REGISTER (RMDC)
HOLDING REGISTER (RMHR)
MAINTENANCE REGISTER 2 (RMMR2)
ERROR REGISTER 2 (RMER2)
ECC POSITION REGISTER (RMECl)
ECC PATTERN REGISTER (RMEC2)
BUS ADDRESS EXTENSION (RMBAE)
CONTROL/STATUS REGISTER 3 (RMCS3)
COMMANDS
DATA TRANSFER COMMANDS
Write Check Data (51)
Write Check Header and Data (53)
Write Data (61)
Write Header and Data (Format
Operation) (63)
Read Data (71)
Read Header and Data (73)
POSITIONING COMMANDS
Seek Command (5)
Recalibrate (7)
Offset Command (15)
Return-To-Centerline Command (17)
Search Command (31)
HOUSEKEEPING COMMANDS
No Op (1)
Drive Clear (11)
Release Command (13)
Read-In Preset (21)
Pack Acknowledge
OPTIONAL COMMANDS
Format (77)
DMA Bandwidth Set (25)
v
3-9
3-9
4-1
4-3
4-3
4-3
4-4
4-6
4-8
4-10
4-10
4-11
4-11
4-12
4-13
4-13
4-14
4-14
4-14
4-15
4-16
4-16
4-17
4-17
5-1
5-1
5-2
5-2
5-2
5-2
5-2
5-3
5-3
5-3
5-3
5-4
5-4
5-4
5-4
5-4
5-4
5-4
5-4
5-5
5-5
5-5

Section 6
6.1
6.2
6.2.1
6.3
6.3.1
6.3.2
6.4
Appendix A
A.l
A.2
A.2.1
A.2.2
A.3
Appendix B
B.l
B.1.1
B.1.2
B.1.3
B.2
B.2.1
B.2.2
B.2.3
B.3
B.3.1
B.3.2
B.4
B.4.1
B.4.2
B.5
B.5.1
B.5.2
B.6
B.6.1
B.6.2
B.7
B.7.1
B.8
BOOTSTRAP PROM OPTION
OVERVIEW
ODT BOOTSTRAP
Operation
AUTO BOOTSTRAP
Operation
Alternate Bootstrap Devices
PROGRAM MESSAGES
6-1
6-2
6-3
6-4
6-5
6-5
6-7
SC03/Bl Configuration and Option Selection
INTRODUCTION
CONTROLLER CONFIGURATION
Physical vs Logical Disk Numbering
Drive Configuration Selection
USER SELECTABLE OPTIONS
Modification for DEC Diagnostics
A-1
A-1
A-1
A-1
A-4
ZRMA-CO FORMATTER B-1
Modifications to Correct Programming B-1
Errors
Modifications For Number of Cylinders B-1
and Tracks
Formatter Operation
ZRMB-BO PERFORMANCE EXERCISER
Modifications to Correct Programming
Errors
B-2
B-3
B-3
Modifications For Number of Cylinders B-4
and Tracks
Performance Exerciser Operation B-5
ZRMC-BO FUNCTIONAL TEST - PART 1 B-6
Modifications For Correct Operation B-6
Modifications For Number of Cylinders B-6
and Tracks
ZRMD-BO FUNCTIONAL TEST - PART 2 B-7
Modifications For Correct Operation B-7
Modifications For Number of Cylinders B-8
and Tracks
ZRME-BO FUNCTIONAL TEST - PART 3 B-9
Modifications For Correct Operation B-9
Modifications For Number of Cylinders B-9
and Tracks
ZRMF-BO EXTENDED DRIVE TEST B-10
Modifications For Correct Operation B-10
Modifications For Number of Cylinders B-10
and Tracks
ZRMI-BO DRIVE COMPATIBILITY TEST
Modifications For Correct Operation
EMULEX DIAGNOSTICS
vi
B-11
B-11
B-11

Table No.
Table 1-1
Table 2-1
Table 2-2
Table 2-3
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 6-5
Table A-1
Table A-2
Table A-3
Table A-4
Table A-5
Table A-6
Figure No.
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 3-1
Figure 3-2
LIST OF TABLES
Title
General Specifications
Disk Drive Connections
Q-Bus Connections
Register Access on Dual Controller
Operation
Bootstrap Option Kit PROMS
ODT Boot Devices
Auto Bootstrap Device Priority List
Alternate Boot Device Address
Boot Option Messages
Drives Supported
Drive Configurations
SC03 Factory Switch Settings
Option Switch SWl Settings
Option Switch SW2 Settings
Option Switch SW3 Settings
LIST OF FIGURES
Title
SC03 Block Diagram
SC03 Controller Board
Sector Format
Header Format
SC03 Controller Assembly
Cabling Schematic
vii
1-4
2-6
2-8
2-18
6-1
6-2
6-4
6-6
6-7
A-2
A-3
A-4
A-5
A-5
A-6
2-2
2-3
2-10
2-10
3-3
3-7

BLANK

1.1 SCOPE
Section 1
INTRODUCTION
This manual provides information related to the capabilities,
design, installation, and use of the SC03/Bl Disk Controller.
In addition, this manual provides diagnostic and application
information.
1.1.1 Register Addresses in this Manual
The register addresses given in this manual are standard Q-Bus
addresses for an RM disk subsystem. All addresses are given for an
18-bi t Q-Bus. For 22-bi t addressing add 17000000 to obtain the
desired register address.
1. 2 OVERVIEW
1.2.1 General Description
The SC03/Bl Disk Controller is a one board, imbedded controller for
LSI-11 computers manufactured by Digital Equipment Corporation.
This controller can be used to interface any large disk having a
Storage Module Drive (SMD) interface. The SC03/Bl controller
emulates the RHll and RH70 disk controllers manufactured by Digital
Equipment Corporation for use with RM02, RM03, RMOS, and RM80 disk
drives.
1.3 FEATURES
1.3.1 Microprocessor Design
The SC03/Bl design incorporates a unique 16-bit bipolar
microprocessor to perform all controller functions. The
microprocessor approach provides for a reduced component count,
high reliability, easy maintainability, and most importantly, the
ability to adapt a single set of hardware to a wide range of
emulation capabilities through the use of microprogramming. The
Emulex controllers achieve functional capability beyond that of the
DEC controllers which they emulate, by providing enhancement
features such as built-in self-test during power-up, built-in disk
formatting and the ability to work with disk drives of various
sizes.
1.3.2 Packaging
The SC03/Bl is constructed on a single, quad-size, Multi-layer PC
board which plugs directly into the LSI-11 chassis. No cabling is
1-1

required between the computer and the disk controller. The
controller obtains its power from the chassis in which it is
mounted.
1.3.3 Self-Test
The controller incorporates an internal self-test routine which is
executed upon power-up. This test exercises all parts of the
microprocessor, buffer and disk data logic. Although this test
does not completely test all controller circuitry, successful
execution indicates a very high probability that the controller is
operational. If the controller fails the self-test, it leaves the
LED ON and the controller cannot be addressed from the CPU.
1.3.4 Buffering
The controller contains a 4K x 16 high-speed RAM buffer. It is
used to store the device registers of the controller plus a 14
sector data buffer. The large buffer eliminates the possibility of
a data late condition and permits the controller to be operated at
low bus priorities.
1.3.5 Error Correction
The controller incorporates a 32-bit error correcting code (ECC)
capable of correcting a single error bit in bursts of up to 11 bits
in length and detecting multiple error bits in bursts of any
length. The controller determines the pattern and location of the
error so that the software may correct the data after it is
transferred to memory. A 16-bit CRC is employed with the header of
every sector.
1.3.6 Dual Port Mode
In order to provide compatibility with dual port drivers when
configured for dual port, the dual port mode is provided. This
mode should be selected only when the disk drive has dual ports and
is configured for dual port operation.
1.3.7 Dual Access Mode
In order to provide compatibility with dual access drivers when
configured for dual access, the dual access mode is provided. When
in this mode, the controller sets Dual Port Mode (Drive Type
Register) and Programmable (Drive Status Register) to imitate the
DEC neutral state.
Setting the Dual Port Option switch overrides the Dual Access
Option except except for the one-second power-up timer disable.
1.3.8 Option and Configuration Switches
Sockets provide for insertion of optional 512 word bootstrap PROMS,
22-bit addressing and Q-Bus termination resistor packs. Provisions
1-2