Emulex SC03/B1 User manual

SC03/Bl
RM03/RM05/RM80 COMPATIBLE
DISK CONTROLLER
TECHNICAL MANUAL
EMULEX
3545 Harbor Boulevard
Costa Mesa, California 92626
[phone] TWX 910-595-2521
SC0351001-00 Rev E
November, 1987

Copyright (C) 1982 Emulex Corporation
The information in this manual is for information purposes and is
subject to change without notice.
Emulex Corporation assumes no responsibility for any errors which
may appear in the manual.
Printed in U.S.A.

Section 1
Section 2
1.1
1.1.1
1.2
1. 2 .1
1.3
1. 3 .1
1. 3. 2
1. 3. 3
1. 3 .4
1. 3. 5
1. 3. 6
1. 3. 7
1. 3. 8
1.4
1.4.1
1.4. 2
1.4. 3
1.4.4
2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2
2.2.3
2.2.4
2.2.5
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.2
2.3.2.1
2.3.2.2
2.3.2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.4.1
TABLE OF CONTENTS
INTRODUCTION
SCOPE
Register Addresses in this Manual
OVERVIEW
General Description
FEATURES
Microprocessor Design
Packaging
Self-Test
Buffering
Error Correction
Dual Port Mode
Dual Access Mode
Option and Configuration Switches
FUNCTIONAL COMPATIBILITY
Media Compatibility
Disk Mapping
Diagnostics
Operating Systems
GENERAL DESCRIPTION
CONTROLLER ORGANIZATION
PHYSICAL DESCRIPTION
Connectors
A Cable Connector
B Cable Connector
Test Connectors
Switches
LED Indicator
Firmware PROMs
Bootstrap PROMs
INTERFACES
Disk Interface
A Cable
B Cable
Q-Bus Interface
Interrupt Priority Level
Register Address
DCOK and INIT Signals
DISK FORMAT
Disk Pack Organization
Mapping
Sector Organization
Header
Header Description
iii
1-1
1-1
1-1
1-1
1-1
1-1
1-1
1-2
1-2
1-2
1-2
1-2
1-2
1-3
1-3
1-3
1-3
1-3
2-1
2-1
2-4
2-4
2-4
2-4
2-4
2-4
2-5
2-5
2-5
2-5
2-5
2-7
2-7
2-9
2-9
2-9
2-9
2-9
2-9
2-9
2-11
2-11

Section 3
2.4.4.2
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.4.1
3.4.4.2
3.4.4.3
3.4.4.4
3.5
3.5.1
3.5.2
3.6
3.6.l
3.6.2
3.6.3
3.7
3.7.1
3.7.2
Header Field Handling
GENERAL PROGRAMMING INFORMATION
Clearing the Controller
Interrupt Conditions
Termination of Data Transfers
Ready Bits
22-Bit Memory Addressing
Line Time Clock (LTC)
Bootstrap Routines
DUAL CONTROLLER OPERATION
Dual Port Drives
Unseized State
Seized State
Returning to the Unseized State
DEC Compatibility
Dual Port Drives in a Single Port
Mode
Dual Access Mode
Dual Port Drives Busy Signal
INSTALLATION
INSPECTION
DISK DRIVE PREPARATION
Drive Placement
Local/Remote
Sectoring
Index and Sector Pulse Selection
Unit Addressing
Lark Drive Configuration
SYSTEM PREPARATION
Powering Down the System
CONTROLLER SETUP
Controller Address Selection
Interrupt Vector Address
Drive Configuration Selection
Options
Q-Bus Terminator Option
Bootstrap PROM Option
22-Bit Memory Addressing
Line Time Clock Option
PHYSICAL INSTALLATION
Slot Selection
Mounting
CABLING
A Cable
B Cable
Grounding
TESTING
Self-Test
Register Examination
iv
2-11
2-11
2-11
2-12
2-12
2-13
2-13
2-14
2-14
2-14
2-15
2-15
2-15
2-15
2-16
2-16
2-17
2-17
3-1
3-1
3-1
3-1
3-2
3-2
3-2
3-2
3-2
3-2
3-2
3-4
3-4
3-4
3-4
3-5
3-5
3-6
3-6
3-6
3-6
3-7
3-7
3-7
3-8
3-8
3-8
3-8
3-9

Section 4
Section 5
3.7.3
3.7.4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
5.1
5 .1.1
5 .1. 2
5 .1. 3
5 .1.4
5 .1. 5
5 .1. 6
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.4
5.4.1
5.4.2
Hardware Formatting the Disk
Diagnostics
CONTROLLER REGISTERS
CONTROL/ STATUS REGISTER 1 (RMCSl)
WORD COUNT REGISTER (RMWC)
Q-BUS ADDRESS REGISTER (RMBA)
DISK ADDRESS REGISTER (RMDA)
CONTROL/STATUS REGISTER 2 (RMCS2)
DRIVE STATUS REGISTER (RMDS)
ERROR REGISTER 1 (RMERl)
ATTENTION SUMMARY REGISTER (RMAS)
LOOK-AHEAD REGISTER (RMLA)
DATA BUFFER (RMDB)
MAINTENANCE REGISTER 1 (RMMRl)
DRIVE TYPE REGISTER (RMDT)
SERIAL NUMBER REGISTER (RMSN)
OFFSET REGISTER (RMOF)
DESIRED CYLINDER REGISTER (RMDC)
HOLDING REGISTER (RMHR)
MAINTENANCE REGISTER 2 (RMMR2)
ERROR REGISTER 2 (RMER2)
ECC POSITION REGISTER (RMECl)
ECC PATTERN REGISTER (RMEC2)
BUS ADDRESS EXTENSION (RMBAE)
CONTROL/STATUS REGISTER 3 (RMCS3)
COMMANDS
DATA TRANSFER COMMANDS
Write Check Data (51)
Write Check Header and Data (53)
Write Data (61)
Write Header and Data (Format
Operation) (63)
Read Data (71)
Read Header and Data (73)
POSITIONING COMMANDS
Seek Command (5)
Recalibrate (7)
Offset Command (15)
Return-To-Centerline Command (17)
Search Command (31)
HOUSEKEEPING COMMANDS
No Op (1)
Drive Clear (11)
Release Command (13)
Read-In Preset (21)
Pack Acknowledge
OPTIONAL COMMANDS
Format (77)
DMA Bandwidth Set (25)
v
3-9
3-9
4-1
4-3
4-3
4-3
4-4
4-6
4-8
4-10
4-10
4-11
4-11
4-12
4-13
4-13
4-14
4-14
4-14
4-15
4-16
4-16
4-17
4-17
5-1
5-1
5-2
5-2
5-2
5-2
5-2
5-3
5-3
5-3
5-3
5-4
5-4
5-4
5-4
5-4
5-4
5-4
5-4
5-5
5-5
5-5

Section 6
6.1
6.2
6.2.1
6.3
6.3.1
6.3.2
6.4
Appendix A
A.l
A.2
A.2.1
A.2.2
A.3
Appendix B
B.l
B.1.1
B.1.2
B.1.3
B.2
B.2.1
B.2.2
B.2.3
B.3
B.3.1
B.3.2
B.4
B.4.1
B.4.2
B.5
B.5.1
B.5.2
B.6
B.6.1
B.6.2
B.7
B.7.1
B.8
BOOTSTRAP PROM OPTION
OVERVIEW
ODT BOOTSTRAP
Operation
AUTO BOOTSTRAP
Operation
Alternate Bootstrap Devices
PROGRAM MESSAGES
6-1
6-2
6-3
6-4
6-5
6-5
6-7
SC03/Bl Configuration and Option Selection
INTRODUCTION
CONTROLLER CONFIGURATION
Physical vs Logical Disk Numbering
Drive Configuration Selection
USER SELECTABLE OPTIONS
Modification for DEC Diagnostics
A-1
A-1
A-1
A-1
A-4
ZRMA-CO FORMATTER B-1
Modifications to Correct Programming B-1
Errors
Modifications For Number of Cylinders B-1
and Tracks
Formatter Operation
ZRMB-BO PERFORMANCE EXERCISER
Modifications to Correct Programming
Errors
B-2
B-3
B-3
Modifications For Number of Cylinders B-4
and Tracks
Performance Exerciser Operation B-5
ZRMC-BO FUNCTIONAL TEST - PART 1 B-6
Modifications For Correct Operation B-6
Modifications For Number of Cylinders B-6
and Tracks
ZRMD-BO FUNCTIONAL TEST - PART 2 B-7
Modifications For Correct Operation B-7
Modifications For Number of Cylinders B-8
and Tracks
ZRME-BO FUNCTIONAL TEST - PART 3 B-9
Modifications For Correct Operation B-9
Modifications For Number of Cylinders B-9
and Tracks
ZRMF-BO EXTENDED DRIVE TEST B-10
Modifications For Correct Operation B-10
Modifications For Number of Cylinders B-10
and Tracks
ZRMI-BO DRIVE COMPATIBILITY TEST
Modifications For Correct Operation
EMULEX DIAGNOSTICS
vi
B-11
B-11
B-11

Table No.
Table 1-1
Table 2-1
Table 2-2
Table 2-3
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 6-5
Table A-1
Table A-2
Table A-3
Table A-4
Table A-5
Table A-6
Figure No.
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 3-1
Figure 3-2
LIST OF TABLES
Title
General Specifications
Disk Drive Connections
Q-Bus Connections
Register Access on Dual Controller
Operation
Bootstrap Option Kit PROMS
ODT Boot Devices
Auto Bootstrap Device Priority List
Alternate Boot Device Address
Boot Option Messages
Drives Supported
Drive Configurations
SC03 Factory Switch Settings
Option Switch SWl Settings
Option Switch SW2 Settings
Option Switch SW3 Settings
LIST OF FIGURES
Title
SC03 Block Diagram
SC03 Controller Board
Sector Format
Header Format
SC03 Controller Assembly
Cabling Schematic
vii
1-4
2-6
2-8
2-18
6-1
6-2
6-4
6-6
6-7
A-2
A-3
A-4
A-5
A-5
A-6
2-2
2-3
2-10
2-10
3-3
3-7

BLANK

1.1 SCOPE
Section 1
INTRODUCTION
This manual provides information related to the capabilities,
design, installation, and use of the SC03/Bl Disk Controller.
In addition, this manual provides diagnostic and application
information.
1.1.1 Register Addresses in this Manual
The register addresses given in this manual are standard Q-Bus
addresses for an RM disk subsystem. All addresses are given for an
18-bi t Q-Bus. For 22-bi t addressing add 17000000 to obtain the
desired register address.
1. 2 OVERVIEW
1.2.1 General Description
The SC03/Bl Disk Controller is a one board, imbedded controller for
LSI-11 computers manufactured by Digital Equipment Corporation.
This controller can be used to interface any large disk having a
Storage Module Drive (SMD) interface. The SC03/Bl controller
emulates the RHll and RH70 disk controllers manufactured by Digital
Equipment Corporation for use with RM02, RM03, RMOS, and RM80 disk
drives.
1.3 FEATURES
1.3.1 Microprocessor Design
The SC03/Bl design incorporates a unique 16-bit bipolar
microprocessor to perform all controller functions. The
microprocessor approach provides for a reduced component count,
high reliability, easy maintainability, and most importantly, the
ability to adapt a single set of hardware to a wide range of
emulation capabilities through the use of microprogramming. The
Emulex controllers achieve functional capability beyond that of the
DEC controllers which they emulate, by providing enhancement
features such as built-in self-test during power-up, built-in disk
formatting and the ability to work with disk drives of various
sizes.
1.3.2 Packaging
The SC03/Bl is constructed on a single, quad-size, Multi-layer PC
board which plugs directly into the LSI-11 chassis. No cabling is
1-1

required between the computer and the disk controller. The
controller obtains its power from the chassis in which it is
mounted.
1.3.3 Self-Test
The controller incorporates an internal self-test routine which is
executed upon power-up. This test exercises all parts of the
microprocessor, buffer and disk data logic. Although this test
does not completely test all controller circuitry, successful
execution indicates a very high probability that the controller is
operational. If the controller fails the self-test, it leaves the
LED ON and the controller cannot be addressed from the CPU.
1.3.4 Buffering
The controller contains a 4K x 16 high-speed RAM buffer. It is
used to store the device registers of the controller plus a 14
sector data buffer. The large buffer eliminates the possibility of
a data late condition and permits the controller to be operated at
low bus priorities.
1.3.5 Error Correction
The controller incorporates a 32-bit error correcting code (ECC)
capable of correcting a single error bit in bursts of up to 11 bits
in length and detecting multiple error bits in bursts of any
length. The controller determines the pattern and location of the
error so that the software may correct the data after it is
transferred to memory. A 16-bit CRC is employed with the header of
every sector.
1.3.6 Dual Port Mode
In order to provide compatibility with dual port drivers when
configured for dual port, the dual port mode is provided. This
mode should be selected only when the disk drive has dual ports and
is configured for dual port operation.
1.3.7 Dual Access Mode
In order to provide compatibility with dual access drivers when
configured for dual access, the dual access mode is provided. When
in this mode, the controller sets Dual Port Mode (Drive Type
Register) and Programmable (Drive Status Register) to imitate the
DEC neutral state.
Setting the Dual Port Option switch overrides the Dual Access
Option except except for the one-second power-up timer disable.
1.3.8 Option and Configuration Switches
Sockets provide for insertion of optional 512 word bootstrap PROMS,
22-bit addressing and Q-Bus termination resistor packs. Provisions
1-2

are also made to enable an optional software-controlled line time
clock (LTC) which is BDVll compatible.
DIP switches are used to configure the cont!oller for various disk
sizes, Q-Bus addresses and options. It is possible to select one
of several possible combinations of disk characteristics for the
two drives which can be handled by the controller, including
mixtures of disk sizes and drive type codes.
1.4 FUNCTIONAL COMPATIBILITY
1.4.1 Media Compatibility
In all cases, the headers written on the drives are standard RM02 1
RM03, RM05 and RM80 headers. Packs may be formatted by utilizing
the hardware formatting capability of the extended command set.
Disk packs formatted with an SC03/Bl controller are media
compatible with other Ernulex controllers and with the equivalent
DEC packs when appropriate disk drives are used.
1.4.2 Disk Mapping
Depending upon the type and size of the disk drive, one or two
logical units may be mapped on it. Various mapping organizations
are used~ some of which do not leave direct 1:1 correlation between
the logical and physical addresses.
1.4.3 Diagnostics
The SC03/Bl will run the following DEC diagnostics on LSI-11
computers.
•
ZRMA
•
ZRMB
•
ZRMC
•
ZRMD
•
ZRME
•
ZRMF
•
ZRMI
Formatter
Performance Exerciser
Functional Controller, Part I*
Functional Controller, Part II*
Functional Controller, Part III*
Extended Drive Test
Drive Compatibility Test
The diagnostics marked with an asterisk require certain patches to
bypass unsupported maintenance functions. All diagnostics require
patches to run with drive sizes other than that of a standarJ
RM02/RM03. See Appendix B for diagnostic patches.
Ernulex provides self-sizing diagnostics for the SC03.
listed at the end of Appendix B.
They are
The SC03/Bl is compatible with all DEC operating systems running on
LSI-11 computers that support the appropriate DEC disk subsystems.
No operating system modifications are required when running
standard sized disk drives.
1-3

FUNCTIONAL
Emulation
Media Compatibility
Drive Interface
Drive Ports
Error Control
Sector Size
Sectors/Track
Tracks/Cylinder
Cylinders/Drive
Drive Type Code
Computer Interface
Q-Bus Address
Standard
Alternate
Vector Address
Standard
Alternates
Priority Level
Data Bufferring
Data Transfer
Table 1-1
General Specifications
DEC RM02, RM03, RM05 and RM80
DEC RM02, RM03 and RM05 when using
appropriate disk drives.
SMD
2
32-bit ECC for data and 16-bit CRC for
headers. Correction of single data error
burst of up to 11 bits.
256 words (512 bytes)
Selectable for each drive.
Selectable for each drive.
Selectable for each drive.
Selectable for each drive.
Q-Bus
776700-776752
776300-776352
254
50, 150, 270, 274, 354, 370, 374
BR4
14 full sectors
High speed NPR operation.
Maximum Disk Data Rate
16 MHz (2 MBytes/second)
1-4

Self-Test
Indicators
DESIGN
PHYSICAL
Packaging
Mounting
Connectors
Electrical
Q-Bus Interface
Drive Interfaces
Power
Table 1-1 (cont~d)
Extensive internal self-test on powering
up.
Activity/Fault LED
High-speed bipolar microprocessor using
2901 bit slice components.
One DEC quad-size board.
Any slot in CPU or expansion box.
One 60-pin A cable flat connector and two
26-pin B cable connectors. (Flat cable
type.)
DEC approved line drivers and receivers.
Differential line drivers and receivers.
A cable accumulative length to 35 feet.
B cable length to 25 feet.
+5 v, 8 Amp. max.
1-5

BLANK

2.1 CONTROLLER ORGANIZATION
Section 2
GENERAL DESCRIPTION
A block diagram showing the major functional elements of the
SC03/Bl controller is shown in Figure 2-1. The controller is
organized around a 16-bit high-speed bipolar microprocessor. The
ALU and register file portion of the microprocessor are implemented
with four 2901 bit slice components. The microinstruction is 48
bits in length and the control memory of 2K words is implemented
with six 2K x 8 PROMS.
The controller incorporates a 4K x 16 high-speed RAM buffer which
is used to store the controller~s device registers and 14 sectors
of data buffering.
The A Cable Register (ACR) latches all A cable signals going to or
from the disk drives. The inputs from the selected drive are
testable by the microprocessor.
The Shift Register converts parallel write data from the data bus
to serial data for the disk drives. The register also converts
serial read data from the drives back into parallel data. Serial
read and write data is provided to the ECC logic via the Shift
Register.
Serial data from the drive is converted into eight-bit parallel
data and transferred to the buffer via the microprocessor.
Likewise, the data access from the buffer by the microprocessor is
serialized and sent to the drive under the control of the servo
clock received from the drive. A 32-bit ECC Shift Register is used
to generate and check the ECC for the data field. The same
register is also used in a 16-bit CRC mode for the headers. The
actual ECC polynomial operation is done independently of the
microprocessor, but the determination of the error position and
error pattern is done under the control of the microprocessor.
The Q-Bus interface consists of 42 bidirectional lines (which
include lines Al8 to A21) and two unidirectional signal lines. The
Q-Bus interface is used for programmed I/O, CPU interrupts, and
data transfers. The microprocessor responds to all programmed I/O
and carries out the I/O functions required for the addressed
controller register. The microprocessor also controls all DMA
operations and transfers data between the Q-Bus data lines and the
buffer.
2.2 PHYSICAL DESCRIPTION
The SC03/Bl controller consists of a single quad-size board which
plugs directly into an LSI-11 chassis. The controller PCBA is
shown in Figure 2-2.
2-1

Data Bus
16-Bit
1K x 16
ALU and
A Cable
Control
Register
RAM
Register
Buffer
A Cable
File
Status
0-Bus
Write
Shift
Data
0-Bus
Address
Register
B Cable
and Data
and
~Read
N
(UAR)
Buffer
I
Data
N I
Address
Se-
Switches
ECC
Decode
quencer
Logic
Test Mux
SC0301 0079
Figure 2-1 SC03 Block Diagram

2.2.1 Connectors
2.2.1.1 A Cable Connector
The 60-pin flat cable connector labeled J3 at the top edge of the
board is for the A cable which daisy-chains to all the drives for
control and status. Pin 1 is located on the right side of the
connector.
2.2.1.2 B Cable Connector
The two 26-pin flat cable connectors labeled Jl and J2 are for the
radial B cables to each of two physical drives which may be
attached to the controller. Pin 1 is identified by an arrowhead on
the connector. The two B cable ports are identical and either
drive may be plugged into either connector.
2.2.1.3 Test Connectors
Connectors J4 and JS are used with the Emulex test panel during
manufacturing test and factory repair. They have no use in normal
operation.
2.2.2 Switches
There are three sets of switches labled SW1-SW3. SWl is a four
pole DIP "piano-type" switch accessible from the PC board edge.
SWl is located such that it is accessible to the operator while the
controller is imbedded in an LSI type chassis, making the selection
of common options simpler to perform.
The other two sets of switches SW2 and SW3 provide controller
address decoding selection, option selection and drive
configuration selection. (See Section 3 for a complete description
of the switch functions.)
2.2.3 LED Indicator
There is an LED indicator mounted between the B Cable connectors at
the top of the board. The controller executes an extensive
self-test when powering up. The microprogrammed organization of
the controller permits most logic other than the interface
circuitry to the disk to be validated before the controller becomes
ready. The LED lamp is turned ON as the controller starts its
self-test and is turned OFF only when the controller successfully
completes the test. If a malfunction is detected by the built-in
diagnostics, the LED remains ON and the controller will not respond
to program I/O. The LED blinks at approximately a one second rate
if the self-test is successful but no drive is seen on-line. The
LED also functions as an activity indicator during read and write
operations.
2-4

2.2.4 Firmware PROMS
There are six PROM sockets, used for the control memory, located
along the left edge of the board. The sockets are labeled PROM 0
through PROM 5 in a discontinuous physical order. The numbers on
the top of the PROM ICs are Emulex part numbers, which identify the
unique pattern of the PROM. When inserting PROMs in the board, the
ID numbers are placed in the same sequence as the PROM numbers on
the board beside each socket.
2.2.5 Bootstrap PROMS
There are two sockets provided for the installation of optional
bootstrap PROMs. They are at location U71 and location 092. PROM
number B02 or B04 goes in location U92, and PROM number B03 or BOS
goes in location U71. The Emulex part number of the option kit is
SC0313001. See paragraph 3.4.4.2 for installation instructions,
and section 6 for operating instructions.
2.3 INTERFACES
2.3.1 Disk Interface
The controllers's disk interface conforms to the Flat Cable
Interface Specification for the SMD, MMD, and CMD (CDC Document No.
64712400}. The controller has been tested with most drives using
the SMD, MMD and CMD interfaces and is compatible with these drives
electrically and in timing.
The following defines the electrical interface and the recommended
cables.
2.3.1.1 A Cable
The 60-conductor A cable is daisy-chained to all drives and
terminated at the last drive. The signals in this cable are listed
in Table 2-1 along with their function when the control tag (Tag 3}
is asserted. The A cable should be a 30-twisted-pair flat cable
with an impedance of 100 ohms and a cumulative length of no
greater than 35 feet.
Spectra-Strip P/N 455-248-60 flat cable or its equivalent is
recommended. It is possible to order A-Cable assemblies from
Emulex that are made up in one of four lengths:
EMULEX P/N
SU1111201
SU1111203
SU1111205
SU1111207
2-5
LENGTH (FT.}
8.0
15.0
25.0
35.0

Table 2-1
Disk Drive Connections
Pins Lo/Hi
Signal
(Tag 3 Function)
From/To
A Cable:
22?52 Unit Select Tag
To
23,53 Unit
Select bit 0
To
24,54
Unit Select bit 1
To
26,56
Unit
Select bit 2
To
27,57
Unit Select bit 3
To
1,31
Tag
1
To
2,32
Tag 2
To
3,33 Tag
3
To
4,34
Bit
0
(Write Gate)
To
5,35
Bit 1
(Read Gate)
To
6,36 Bit
2 (Servo Off set Plus)
To
7,37
B. +-
1 ...
3 (Servo Off set Minus)
To
8,38 Bit 4
(Fault Clear)
To
9,39
Bit 5 (AM Enable)
To
10,40
Bit
6 (Return to Zero)
To
11,41
Bit 7 (Data Strobe Early)
To
12,42 Bit
8
(Data Strobe Late)
To
13,43
Bit
9 (Release)
To
30,60
Bit 10
To
14,44
Open Cable
Detect
To
15,45
Fault
From
16,46
Seek Error
From
17,47
On Cylinder
From
18,48
Index
From
19,49
Unit Ready
From
20,50
Not Used
From
21,51
Busy
(dual port only)
From
25,55
Sector From
28,58
Write Protected
From
29
Power
Sequence Hold To
59 Power
Sequence Pick To
B
Cable:
8,20
Write
Data
To
6,19
Write Clock
To
2,14
Servo Clock
From
3,16
Read Data
From
.5, 17
Read Clock
From
10,23
Not Used
From
22,9
Unit Selected From
12,24
Not Used From
13,26
Not Used
From
--~--~----------------------------------------------------------
2-6