Explore EP9134 User manual

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User Guide — EP9134_UG V0.2
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4 Ports HDMI 1.3 Splitter
EP9134
User Guide
V0.2
Original Release Date: Aug. 27, 2007
Explore
Revised: Mar. 14, 2008
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Revision History
Version
Number
Revision
Date Author Description of Changes
0.0 Aug/27/2007 Jerry Chen Initial Version
0.1 Jan/11/2008 Ether Lai Revised Version
0.2 Mar/14/2008 Ether Lai Revise Register Description; Change package type;
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Section 1 Introduction
1.1 Overview
The EP9134 is a 4-Port DVI/HDMI splitter with integrated HDCP decryption/encryption engines and is
compliant with HDMI Rev 1.3b and HDCP Rev 1.2 specifications. The EP9134 receives DVI/HDMI
inputs, process HDCP decryption and encryption and transmits the data to 4 DVI/HDMI ports. The chip
uses an external EE to store the encrypted HDCP receiver/transmitter keys.
1.2 Features
• DVI Specification 1.0 Compliant
• HDMI Specification 1.3b Compliant
• Integrated HDCP decryption/encryption engines which are compliant with HDCP Rev 1.1
specification
• Encrypted HDCP keys store in external serial EE
• Wide Frequency Range: 25MHz - 225MHz
• Support 12-bit Deep Color up to 1080p
• Supports 1 DVI/HDMI input port and 4 DVI/HDMI output ports
• Supports conversion of HDMI signaling to DVI signaling
• Supports HDCP Repeater
• Cascadable to make more than 4 output ports
• 128-Pin HQFP (Pb-Free)
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Section 2 Overview
2.1 Block Diagram
Figure 2-1 Block Diagram
SDA1
SCL1
EXT_RSTb
IIC Slave
Registers
&
Logics
DVI/HDMI
Receiver
EXT_SWING
HDCP Keys
RX0+/- RX1+/- RX2+/- RXC+/-
DVI/HDMI
Transmitter
SDA3
SCL3 IIC Slave
SDA2
SCL2 IIC Master
HDCP Keys DVI/HDMI
Transmitter
HDCP Keys
TX00+/- TX10+/- TX20+/- TXC0+/-
TX01+/- TX11+/- TX21+/- TXC1+/-
HDCP Keys
DVI/HDMI
Transmitter HDCP Keys DVI/HDMI
Transmitter
TX02+/- TX12+/- TX22+/- TXC0+/-
TX03+/- TX13+/- TX23+/- TXC1+/-
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2.2 Pin Diagram
Figure 2-2
reserved 32
VSSE 31
VDDE 30
SDA2 29
SCL2 28
SDA1 27
SCL1 26
VSS 25
VDD18 24
EXT_RSTb 23
A2 22
A1 21
A0 20
VSS 19
VSS 18
VDD18 17
VDD18 16
AVSS 15
AVSS 14
TX22+ 13
TX22- 12
AVDD 11
TX12+ 10
TX12- 9
AVSS 8
AVSS 7
TX02+ 6
TX02- 5
AVDD 4
TXC2+ 3
2TXC2-
1
AVSS
EXT_SWING01
64
PVDD
63
PVSS
62
AVSS
61
AVSS
60
TX21+
59
TX21-
58
AVDD
57
TX11+
56
TX11-
55
AVSS
54
AVSS
53
TX01+
52
TX01-
51
AVDD
50
TXC1+
49
TXC1-
48
AVSS
47
AVSS
46
VSS
45
VSS
44
VDD18
43
VDD18
42
HTPLG3
41
AVDD
71
72
73
TX10+74
75
AVSS
76
AVSS
77
PVSS
78
PVDD
79
EXT_RES
80
AVDD
81
RXC-
82
RXC+
83
AVSS
84
RX0-
85
86
RX0+
87
AVSS
88
89
AVDD90
AVSS91
RX1-92
RX1+93
AVDD94
RX2-95
RX2+96
AVSS97
_AVSS98
_AVSS99
_AVSS100
_AVSS101
_AVSS102
103 104 105 106 107 108 109 110 111 112 113 114
TX03+
115
AVSS
116
AVSS
117
TX13-
118
TX13+
119
AVDD
120
AVDD
121
TX23-
122
TX23+
123
AVSS
124
AVSS
125
PVSS
126
127 128
PVSS
PVDD
PVDD
EXT_SWING23
AVSS
HTPLG2
40
TX10-
AVSS
AVSS
TX20+
TX20-
39
AVSS
_AVSS
_AVSS
AVSS
AVSS
TXC3-
TXC3+
AVDD
AVDD
TX03-
reserved 33
SCL3 34
SDA3 35
V_OUT 36
HTPLG0 37
HTPLG1 38
70 TX00+
69 TX00-
68 AVDD
67 TXC0+
66 TXC0-
65 AVSS
Pin Diagram
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2.3 Pin Description
Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.
Table 2-1 IIC Pins
NAME IN /
OUT DESCRIPTION
SCL1 IN IIC SCL signal for receiver port DDC
SDA1 IO IIC SDA signal for receiver port DDC (open drain)
SCL2 OUT IIC SCL signal for EE interface (open drain)
SDA2 IO IIC SDA signal for EE interface (open drain)
SCL3 IN IIC SCL signal for internal registers access
SDA3 IO IIC SDA signal for internal registers access (open drain)
A2, A1, A0 IN Determine the lowest 3-bit of the IIC addrress for IIC Port 3 (SCL3/SDA3)
Table 2-2 Misc. Pins
NAME IN /
OUT DESCRIPTION
EXT_RSTb IN External Reset (Active LOW). A HIGH level indicates normal operation and a
LOW level causes all the logic on the chip to be reset.
V_OUT OUT Polarity corrected vertical sync pulse (active high) derived from receiver
input
reserved IN Must be tied LOW for normal operation.
Table 2-3 Receiver Pins
NAME IN /
OUT DESCRIPTION
RX0-
RX0+
RX1-
RX1+
RX2-
RX2+
Analog
Differential Data Input Pairs for receiver port
RXC-
RXC+ Differential Clock Input Pairs for receiver port
EXT_RES Analog DVI/HDMI External Termination Resistor
Table 2-4 Transmitter Pins
NAME IN /
OUT DESCRIPTION
TX00-
TX00+
TX10-
TX10+
TX20-
TX20+
Analog
Differential Data Output Pairs for transmitter port 0
TXC0-
TXC0+ Differential Clock Output Pairs for transmitter port 0
HTPLG0 IN
Hot Plug Input
This pin is used to monitor the "HOT PLUG" signal for tansmitter port 0. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
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TX01-
TX01+
TX11-
TX11+
TX21-
TX21+
Analog
Differential Data Output Pairs for transmitter port 1
TXC1-
TXC1+ Differential Clock Output Pairs for transmitter port 1
HTPLG1 IN
Hot Plug Input
This pin is used to monitor the "HOT PLUG" signal for tansmitter port 1. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
EXT_SWING01 Analog
Voltage Swing Adjust for Port 0/1. A resistor should tie this pin to AVCC. This
resistance determines the amplitude of the voltage swing. 560:is
recommended.
TX02-
TX02+
TX12-
TX12+
TX22-
TX22+
Analog
Differential Data Output Pairs for transmitter port 2
TXC2-
TXC2+ Differential Clock Output Pairs for transmitter port 2
HTPLG2 IN
Hot Plug Input
This pin is used to monitor the "HOT PLUG" signal for tansmitter port 2. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
TX03-
TX03+
TX13-
TX13+
TX23-
TX23+
Analog
Differential Data Output Pairs for transmitter port 3
TXC3-
TXC3+ Differential Clock Output Pairs for transmitter port 3
HTPLG3 IN
Hot Plug Input
This pin is used to monitor the "HOT PLUG" signal for tansmitter port 3. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
EXT_SWING23 Analog
Voltage Swing Adjust for Port 2/3. A resistor should tie this pin to AVCC. This
resistance determines the amplitude of the voltage swing. 560:is
recommended.
Table 2-5 Power and Ground Pins
NAME IN /
OUT DESCRIPTION
VDDE PWR Digital Power, 3.3V
VSSE GND Digital Ground
VDD18 PWR Core Power, 1.8V
VSS GND Core Ground
AVDD PWR Analog Power, 3.3V
AVSS GND Analog Ground
PVDD PWR Analog Power for PLL, 3.3V
Table 2-4 Transmitter Pins
NAME IN /
OUT DESCRIPTION
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PVSS GND Analog Ground for PLL
_AVSS GND Analog Ground
Table 2-5 Power and Ground Pins
NAME IN /
OUT DESCRIPTION
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2.4 Electrical Characteristics
Absolute Maximum Conditions
Symbol Parameter Min Typ Max Units
Vcc33 3.3V Supply Voltage -0.3 4.0 V
Vcc18 1.8V Supply Voltage -0.3 2.5 V
VIInput Voltage -0.3 Vcc + 0.3 V
VOOutput Voltage -0.3 Vcc + 0.3 V
TAAmbient Temperature (with power applied) -25 75 qC
TSTG Storage Temperature -40 125 qC
TJA Thermal Resistance (Junction to Ambient) 29.1 qC/W
PPD Package Power Dissipation 2.4 W
1 Permanent device damage may occur if absolute maximum conditions are exceeded.
2 Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Normal Operating Conditions
Symbol Parameter Min Typ Max Units
Vcc33 3.3V Supply Voltage 3.14 3.3 3.6 V
Vcc18 1.8V Supply Voltage 1.71 1.8 1.98 V
VCCN Supply Voltage Noise1-0.3 100 mVp-p
TAAmbient Temperature (with power applied) 0 25 70 qC
1 Guaranteed by design.
DC Digital I/O Specifications (under normal operating conditions unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units
VIH High-level Input Voltage 2.0 V
VIL Low-level Input Voltage 0.8 V
VOH High-level Output Voltage 2.4 V
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DC Analogue Specifications (under normal operating conditions unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units
VOD
Differential Voltage
Single ended peak to peak amplitude
RLOAD = 50 ohm
REXT_SWING = 430 ohm 510 550 590 mV
VDOH Differential High-level Output Voltage1AVCC mV
IDOS Differential Output Short Circuit Current VOUT = 0V 5 V
IPD Power-Down Current225qC Ambient
3V3 2 mA
1V8 1 mA
ICCD
Supply Current
(25qC Ambient,
REXT_SWING = 430 ohm,
TX0/TX1/TX2/TX3 are Active)
1080p Resolution (8-bit)
3V3 440 mA
1V8 110 mA
UXGA Resolution (8-bit)
3V3 449 mA
1V8 110 mA
1080p Resolution (12-bit)
3V3 484 mA
1V8 164 mA
1 Guaranteed by design.
2 Assumes all HDMI/DVI I/O ports are not connected and all digital inputs are scilent.
Receiver AC Specifications (under normal operating conditions unless otherwise specified)
Symbol Parameter Conditions Min Typ Max Units
TDPS Intra-Pair (+ to -) Differential Input Skew10.4 Tbit
TCCS Channel to Channel Differential Input Skew11.0 Tpixel
TIJIT Differential Input Clock Jitter Tolerance2,3 0.3 Tbit
TPDL
Delay from OUT_EN Low to High Impedance
outputs 10 ns
THSC Link Disabled (Tx power down) to LINK_ON Low4250 ms
TFSC Link Enabled (DE Active) to LINK_ON High125 40 DE
edges
VOL Low-level Output Voltage 0.4 V
IOL Output Leakage Current High Impedance -10 10 uA
VID
Differential Input Voltage, Single
Ended Amplitude 150 1000 mV
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