Fairchild FEBFAN9611 S01U300A User manual

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© 2012 Fairchild Semiconductor Corporation 1 FEBFAN9611_S01U300A • Rev. 0.0.1
User Guide for
FEBFAN9611_S01U300A
Evaluation Board
FAN9611 300W Interleaved Dual-BCM,
Low-Profile, PFC Evaluation Board
Featured Fairchild Product:
FAN9611
Direct questions or comments
about this evaluation board to:
“Worldwide Direct Support”
Fairchild Semiconductor.com

© 2012 Fairchild Semiconductor Corporation 2 FEBFAN9611_S01U300A • Rev. 0.0.1
Table of Contents

1.Overview of the Evaluation Board............................................................................................. 3
2.Key Features............................................................................................................................... 5
3.Specifications ............................................................................................................................. 6
4.Test Procedure............................................................................................................................ 7
4.1.Safety Precautions.............................................................................................................7
5.Schematic ................................................................................................................................... 9
6.Boost Inductor Specification .................................................................................................... 10
7.Four-Layer PCB and Assembly Images................................................................................... 11
8.Bill of Materials (BOM)........................................................................................................... 14
9.Inrush Current Limiting............................................................................................................ 16
10.Test Results............................................................................................................................. 18
10.1.Startup.............................................................................................................................18
10.2.Steady State Operation....................................................................................................20
10.3.Line Transient .................................................................................................................24
10.4.Load Transient ................................................................................................................25
10.5.Brownout Protection .......................................................................................................27
10.6.Phase Management .........................................................................................................28
10.7.Efficiency........................................................................................................................30
10.8.Harmonic Distortion and Power Factor ..........................................................................32
10.9.EMI .................................................................................................................................33
11.References............................................................................................................................... 34
12.Ordering Information .............................................................................................................. 34
13.Revision History ..................................................................................................................... 34

© 2012 Fairchild Semiconductor Corporation 3 FEBFAN9611_S01U300A • Rev. 0.0.1
The following user guide supports the FAN9611 300W evaluation board for interleaved
boundary-conduction-mode power-factor-corrected supply. It should be used in
conjunction with the FAN9611 datasheet, Fairchild application note AN-6086 —Design
Considerations for Interleaved Boundary-Conduction Mode PFC Using FAN9611 /
FAN9612 and FAN9611/12 PFC Excel®-based Design Tool.
1. Overview of the Evaluation Board
The FAN9611 interleaved, dual Boundary-Conduction-Mode (BCM), Power-Factor-
Correction (PFC) controllers operate two parallel-connected boost power trains 180º out
of phase. Interleaving extends the maximum practical power level of the control
technique from about 300W to greater than 800W. Unlike the Continuous Conduction
Mode (CCM) technique often used at higher power levels, BCM offers inherent zero-
current switching of the boost diodes (no reverse-recovery losses), which permits the use
of less expensive diodes without sacrificing efficiency. Furthermore, the input and output
filters can be smaller due to ripple current cancellation between the power trains and
doubling of effective switching frequency.
The advanced line feed-forward with peak detection circuit minimizes the output voltage
variation during line transients. To guarantee stable operation with less switching loss at
light load, the maximum switching frequency is clamped at 525kHz. Synchronization is
maintained under all operating conditions.
Protection functions include output over-voltage, over-current, open-feedback, under-
voltage lockout, brownout, and redundant latching over-voltage protection. FAN9611 is
available in a lead-free, 16-lead, Small-Outline Integrated-Circuit (SOIC) package.
This FAN9611 evaluation board uses a four-layer Printed Circuit Board (PCB) designed
for 300W (400V/0.75A) rated power. The maximum rated power is 350W and the
Maximum On-Time (MOT) power limit is set to 360W. The FEBFAN9611_S01U300A
is optimized to demonstrate all the FAN9611 efficiency and protection features in a low-
profile height form factor less than 18mm.

© 2012 Fairchild Semiconductor Corporation 4 FEBFAN9611_S01U300A • Rev. 0.0.1
Figure 1. FEBFAN9611_S01U300A, Top View, 152mm x 105mm
Figure 2. FEBFAN9611_S01U300A, Side View (Low Profile), Cross Section=18mm
Figure 3. FEBFAN9611_S01U300A, Bottom View, 152mm x 105mm

© 2012 Fairchild Semiconductor Corporation 5 FEBFAN9611_S01U300A • Rev. 0.0.1
2. Key Features
180° Out-of-Phase Synchronization
Automatic Phase Disable at Light Load
1.8A Sink, 1.0A Source, High-Current Gate Drivers
Transconductance (gM) Error Amplifier for Reduced Overshoot
Voltage-Mode Control with (VIN)2Feed-Forward
Closed-Loop Soft-Start with Programmable Soft-Start Time for Reduced Overshoot
Minimum Restart Timer Frequency to Avoid Audible Noise
Maximum Switching Frequency Clamp
Brownout Protection with Soft Recovery
Non-Latching OVP on FB Pin and Second-Level Latching Protection on OVP Pin
Open-Feedback Protection
Over-Current and Power-Limit Protection for Each Phase
Low Startup Current: 80µA Typical
Works with DC input or 50Hz to 400Hz AC Input
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ZCD1
ZCD2
5VB
MOT
AGND
COMP
FB
SS
OVP
CS1
CS2
PGND
DRV2
DRV1
VDD
VIN
0.2V
5V
gm
3VREF
Q
Q
R
S
Q
Q
R
S
UVLO
5V
BIAS
5V VDD
VDD
5µA
0.195V
0.195V
1.25V
IMOT
A
B
AB
5V
A
5V
B
PROTECTION LOGIC
(Open FB, Brownout Protection,
OVP, Latched OVP)
INPUT VOLTAGE SENSE
(Input Voltage Squarer,
Input UVLO, Brownout)
K1 VIN IMOT
2
K1 VIN IMOT
2
Phase
Management
CHANNEL 1
VALLEY DETECTOR
CHANNEL 2
VALLEY DETECTOR
SYNCHRONIZATION
RESTART TIMERS
FREQUENCY CLAMPS
2µA
Figure 4. Block Diagram

© 2012 Fairchild Semiconductor Corporation 6 FEBFAN9611_S01U300A • Rev. 0.0.1
3. Specifications
This evaluation board has been designed and optimized for the conditions in Table 1.
Table 1. Electrical and Mechanical Requirements
Min. Typ. Max.
VIN_AC 80V 120V 265V
VIN_AC(ON) 90V
VIN_AC(OFF) 80V
fVIN_AC 50Hz 60Hz 65Hz
VOUT_PFC 395V 400V 405V
VOUT_PFC_RIPPLE 10V 11V
POUT_PFC 300W 350W
POUT_PFC(MOT LIMIT) 360W
fSW_PFC 18kHz 300kHz
tHOLD_UP 20ms
tSOFT_START 250ms 300ms
tON_OVERSHOOT 10V
_PFC_120V
POUT>30%POUT(TYP) 96% 96.5%
_PFC_230V
POUT>30%POUT(TYP) 95% 98%
PF_120V 0.991
PF_230V 0.980
Mechanical and Thermal
Height 18mm
JC
60⁰C
The trip points for the built-in protections are set as below in the evaluation board.
The line UVLO (brownout protection) trip point is set at 80VAC (10VAC hysteresis).
The pulse-by-pulse current limit for each MOSFET is set at 6A.
The current-limit function can be observed by measuring the individual inductor current
waveforms while operating at 85VAC and increasing the load to 360W. The maximum
power limit is set at ~120% of the rated output power. The power-limit function can be
observed while operating at >115VAC and increasing the load beyond 360W. When
operating in power limit, the output voltage drops and the COMP voltage is saturated, but
the AC line current remains sinusoidal. The phase-management function permits phase
shedding / adding ~18% of the nominal output power for high line (230VAC). This level
can be increased by modifying the MOT resistor (R6) as described in Fairchild
Application Note AN-6086 —Design Considerations for Interleaved Boundary-
Conduction Mode PFC Using FAN9611 / FAN9612.

© 2012 Fairchild Semiconductor Corporation 7 FEBFAN9611_S01U300A • Rev. 0.0.1
4. Test Procedure
Before applying power to the FEBFAN9611_S01U300A evaluation board; the DC bias
supply for VDD, AC voltage supply for line input, and DC electronic load for output
should be connected to the board as shown in Figure 5.
Table 2. Specification Excerpt from FAN9611 Datasheet
Symbol Parameter Conditions Min. Typ. Max. Unit
Supply
ISTARTUP Startup Supply Current VDD = VON – 0.2V 80 110 µA
IDD Operating Current Output Not Switching 3.7 5.2 mA
IDD_DYM Dynamic Operating Current fSW = 50kHz; CLOAD = 2nF 4 6 mA
VON UVLO Start Threshold VDD Increasing 9.5 10.0 10.5 V
VOFF UVLO Stop Threshold Voltage VDD Decreasing 7.0 7.5 8.0 V
VHYS UVLO Hysteresis VON – VOFF 2.5 V
4.1. Safety Precautions
The FEBFAN9611_S01U300A evaluation module produces lethal voltages and the bulk
output capacitors store significant charge. Please be extra careful when probing and
handling the module and observe a few precautions:
Start with a clean working surface, clear of any conductive material.
Be careful while turning on the power switch to the AC source.
Never probe or move a probe on the DUT while the AC line voltage is present.
Ensure the output capacitors are discharged before disconnecting the test leads. One
way to do this is to remove the AC power with the DC output load still switched on.
The load then discharges the output capacitors and the module is safe to disconnect.
Power-On Procedure
1. Supply VDD for the control chip first. It should be higher than 10.5V (refer to the
specification for VDD turn-on threshold voltage in Table 2).
2. Connect the AC voltage (90~265VAC) to start the FAN9611 evaluation board. Since
FAN9611 has brownout protection, any input voltage less than the designed
minimum AC line voltage triggers brownout protection. FEBFAN9611_S01U300A
does not start until the AC input voltage is greater than 90VAC.
3. Change load current (0~0.75A) and check the operation
4. Verify the output voltage is regulating between 395VDC<VOUT<405VDC

© 2012 Fairchild Semiconductor Corporation 8 FEBFAN9611_S01U300A • Rev. 0.0.1
Figure 5. Recommended Test Set-Up
All efficiency data shown in this document was taken using the test set up shown in
Figure 5 with the output voltage being measured directly at the output bulk capacitors
(not through the output connector (J2)).
Power-Off Procedure
1. Make sure the electronic load is set to draw at least 100mA of constant DC current.
2. Disconnect (shut down) AC line voltage source.
3. Disconnect (shut down) 12V DC bias power supply.
4. Disconnect (shut down) DC electronic load last to ensure that the output capacitors
are fully discharged before handling the evaluation module.
AC Source
PF, THD, PIN
0-265VAC
DVM
Current
DC Bias Supply
0-12V
DVM
Current
Electronic Load
400V, 0-1A
DVM
Voltage

© 2012 Fairchild Semiconductor Corporation 9 FEBFAN9611_S01U300A • Rev. 0.0.1
5. Schematic
Figure 6. FEBFAN9611_S01U300A 300W Evaluation Board Schematic

© 2012 Fairchild Semiconductor Corporation 10 FEBFAN9611_S01U300A • Rev. 0.0.1
6. Boost Inductor Specification
750340834 from Wurth Electronics (www.we-online.com)
Core: EFD30 (Ae=69mm2)
Bobbin: EFD30
Inductance : 270H
Figure 7. Boost Inductor (L1, L2) in the Evaluation Board
Figure 8. Wurth 750340834 Mechanical Drawing
Table 3. Inductor Turns Specifications
Pin Turns Wire
NBOOST 1 6 69 (3 Layers) 30xAWG#38 Litz
Insulation Tape
NAUX 10 9 7 AWG#28
Insulation Tape

© 2012 Fairchild Semiconductor Corporation 11 FEBFAN9611_S01U300A • Rev. 0.0.1
7. Four-Layer PCB and Assembly Images
Figure 9. Layer 1 – Top Layer
Figure 10. Layer 2 – Internal Layer

© 2012 Fairchild Semiconductor Corporation 12 FEBFAN9611_S01U300A • Rev. 0.0.1
Figure 11. Layer 3 – Internal Layer
Figure 12. Layer 4 – Bottom Layer

© 2012 Fairchild Semiconductor Corporation 13 FEBFAN9611_S01U300A • Rev. 0.0.1
Figure 13. Top Assembly
Figure 14. Bottom Assembly

© 2012 Fairchild Semiconductor Corporation 14 FEBFAN9611_S01U300A • Rev. 0.0.1
8. Bill of Materials (BOM)
Item Qty. Reference Part Number Value Description Manufacturer Package
1 2 C1, C6 0.22µF CAP, SMD, Ceramic, 25V,
X7R STD 1206
2 1 C2 390nF CAP, SMD, Ceramic, 25V,
X7R STD 805
3 2 C3, C13 15nF CAP, SMD, Ceramic, 25V,
X7R STD 805
4 2 C4, C9 ECW-F2W154JAQ 150nF Cap, 450V, 5%, Polypropylene Panasonic Thru-Hole
5 1 C5 470nF CAP, SMD, Ceramic, 25V,
X7R STD 805
6 2 C7, C11 B32914A3474 470nF Cap, 330VAC, 10%,
Polypropylene EPCOS Thru-Hole
7 2 C8, C26 B43041A5157M 150µF Cap, Alum, Elect. EPCOS Thru-Hole
8 2 C10, C14 2.2µF CAP, SMD, Ceramic, 25V,
X7R STD 1206
9 1 C12 B32914A3105K 1µF Cap, 330VAC, 10%,
Polypropylene Epcos Thru-Hole
10 1 C15 PHE840MB6100MB05R17 0.1µF Cap, X Type, 10%,
Polypropylene KEMET Thru-Hole
11 2 C16, C18 CS85-B2GA471KYNS 470pF
Cap, Ceramic, 250VAC, 10%,
Y5P, TDK Corporation Thru-Hole
12 1 C17 2.7nF CAP, SMD, Ceramic, 25V,
X7R STD 805
13 1 C19 0.1µF CAP, SMD, Ceramic, 25V,
X7R STD 805
14 1 C20 1µF CAP, SMD, Ceramic,50V, X5R STD 805
15 1 C37 1nF CAP, SMD, Ceramic, 25V,
X7R STD 805
16 3 D1-3 ES3J
Diode, 600V, 3A, Ultra-Fast
Recovery
Fairchild
Semiconductor SMC
17 2 D4, D6 S1J
Diode, General Purpose, 1A,
600V
Fairchild
Semiconductor SMA
18 1 D5 GBU6J Diode, Bridge, 6A, 1000V Fairchild
Semiconductor Thru-Hole
19 3 D7-8, D10 MBR0540 Diode, Schottky,40V, 500mA Fairchild
Semiconductor SOD-123
20 1 D9 MMBZ5231B 5.1V Diode, Zener, 5V, 350mW Fairchild
Semiconductor SOT-23
21 1 F1 37421000410 10A Fuse, 374 Series, 5.08mm
Spacing Littlefuse Radial
22 1 H1 7-345-2PP-BA Heatsink, Low Profile, T0-247 CTS Thru-Hole
23 1 J1 1-1318301-3 Header, 3 Pin, 0.312 Spacing TE Connectivity Thru-Hole
24 1 J2 1-1123724-2 Header, 2 Pin, 0.312 Spacing TYCO Thru-Hole
25 5 J3-7 3103-2-00-21-00-00-08-0 Test pin, Gold, 40mil, Mill-Max Thru-Hole
26 1 K1 G5CA-1A DC12
RELAY PWR SPST-NO 10A
12VDC PCB
Omeron
Electronics, Inc. Thru-Hole
27 2 L1-2 750340834/NP1138-01 280µH Inductor, Coupled Wurth Thru-Hole
28 2 L3-4 750311795 9mH Common Mode Choke, 9mH Wurth Thru-Hole
29 2 Q1, Q3 FDP22N50N
MOSFET, NCH, UniFET,
500V, 11.5A, 0.18
Fairchild
Semiconductor TO-220
Continued on the following page…

© 2012 Fairchild Semiconductor Corporation 15 FEBFAN9611_S01U300A • Rev. 0.0.1
Item Qty. Reference Part Number Value Description Manufacturer Package
30 2 Q2, Q4 ZXTP25020DFL Transistor, PNP, 20V, 1.5A Zetex SOT-23
31 1 Q6 2N7002 MOSFET, NCH, 60V, 300mA Philips SOT-23
32 2 R1-2 46.4kRES, SMD, 1/8W STD 805
33 6
R3, R18,
R23-24 R33-
34 665kRES, SMD, 1/8W STD 805
34 3 R4, R7-8 340kRES, SMD, 1/8W STD 805
35 1 R5 68.1kRES, SMD, 1/8W STD 805
36 1 R6 60.4kRES, SMD, 1/8W STD 805
37 1 R9 422kRES, SMD, 1/8W STD 805
38 2 R10, R20 47.5RES, SMD, 1/8W STD 805
39 2 R11-12 12RES, SMD, 1/8W STD 805
40 2 R13-14 0.033RES, SMD, 1W STD 2512
41 1 R15 B57237S0330M000 33Thermistor Epcos Inc. Thru-Hole
42 3 R16, R26,
R40 0RES, SMD, 1/2W STD 2010
43 1 R17 45.3kRES, SMD, 1/8W STD 805
44 1 R19 15.4kRES, SMD, 1/8W STD 805
45 2 R21-22 10kRES, SMD, 1/8W STD 805
46 1 R25 24.9kRES, SMD, 1/4W STD 1206
47 2 R27-28 1.24MRES, SMD, 1/8W STD 805
48 3 R29, R35-36 1.2kRES, SMD, 1/8W STD 805
49 1 R30 23.7kRES, SMD, 1/4W STD 1206
50 1 R31 7.68kRES, SMD, 1/8W STD 805
51 1 R32 150kRES, SMD, 1/4W STD 1206
52 1 R37 1kRES, SMD, 1/8W STD 805
53 1 R38 0RES, SMD, 1/4W STD 1206
54 1 R39 0RES, SMD, 1/8W STD 805
55 2 R65-66 DNP RES, SMD, 1/10W STD 603
56 1 U1 FAN9611
Interleaved, Dual, BMC, PFC
Controller
Fairchild
Semiconductor SOIC-16
57 1 U2 LM393M Dual, Differential Comparator Fairchild
Semiconductor SOIC-8
58 2 SC1, SC2 PMSSS 440 0050 PH
SCREW MACHINE PHIL 4-
40X1/2 SS STD Hardware
59 2 W1, W2 INT LWZ 004
WASHER LOCK INT TOOTH
#4 ZINC STD Hardware
60 2 N1, N2 HNZ440 NUT HEX 4-40 ZINC PLATED STD Hardware
61 1 PWB
4 Layer, FR4, FAN9611 LOW-
PROFILE PWB - REV. 1.0
Fairchild
Semiconductor PCB
Notes:
1. DNP = Do Not Populate
2. STD = Standard Components

© 2012 Fairchild Semiconductor Corporation 16 FEBFAN9611_S01U300A • Rev. 0.0.1
9. Inrush Current Limiting
The evaluation board includes an inrush current limiting circuit comprised of the highlighted
components shown in Figure 15.
Figure 15. Inrush Current Limiting Circuit
Since the inrush current limiting circuit has a negative impact on light-load efficiency and may not
be required by all offline applications, the evaluation board is configured with the inrush circuit
fully populated, but disabled, as shown in Figure 15. R18 and R39 are installed on the PCB;
purposely electrically open. To enable and test the inrush current limiting circuit, rotate R18 and
R39 to complete the proper series connection shown in the schematic. Remove R38 to allow the
33ΩNTC thermistor (R15) to limit the inrush current during startup. Input current measurements
can be made by removing the R16, 0Ωjumper and installing a loop of wire connected to the holes
provided within the R16 PCB pad locations. A current probe can then be connected to the wire
loop. The effectiveness of the inrush current limiting function is shown below in Figure 16.

© 2012 Fairchild Semiconductor Corporation 17 FEBFAN9611_S01U300A • Rev. 0.0.1
M2: AC Line Current (5A/div), CH3: AC Line Current (5A/div), Time (50ms/div)
Figure 16. Full-Load Startup at 115VAC
Table 4. Inrush Current Limiting Circuit Effectiveness Comparison
Input Line
Voltage Output Power Peak Line Current (Inrush Circuit Disabled) Peak Line Current (Inrush Circuit Enabled)
% Inrush
Current
Reduction
VIN=115VAC 300W 22.50APK 8.45APK 62.40%
VIN=230VAC 300W 26.9APK 11.5APK 57.3%
AC Input Current
(Inrush Enabled)
AC Input Current
(Inrush Disabled)
AC Input Peak
Current (Zoom)
(Inrush Disabled)
33NTC

© 2012 Fairchild Semiconductor Corporation 18 FEBFAN9611_S01U300A • Rev. 0.0.1
10. Test Results
10.1. Startup
Figure 17 and Figure 18 show the startup operation at 115VAC line voltage for no-load
and full-load condition, respectively. Due to the closed-loop soft-start, almost no
overshoot is observed for no-load startup and full-load startup.
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (100ms/div)
Figure 17. No-Load Startup at 115VAC
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (200ms/div)
Figure 18. Full-Load Startup at 115VAC
DRV1
VOUT
Line
Current
DRV1
VOUT
Line
Current
COMP
COMP

© 2012 Fairchild Semiconductor Corporation 19 FEBFAN9611_S01U300A • Rev. 0.0.1
Figure 19 and Figure 20 show the startup operation at 230VAC line voltage for no-load
and full-load conditions, respectively. Due to the closed-loop soft-start, almost no
overshoot is observed for no-load startup and full-load startup.
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (10A/div), Time (100ms/div)
Figure 19. No-Load Startup at 230VAC
CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div),
CH3: Output Voltage (200V/div), CH4: Line Current (10A/div), Time (100ms/div)
Figure 20. Full-Load Startup at 230VAC
DRV1
VOUT
Line
Current
DRV1
VOUT
Line
Current
COMP
COMP