Fastrax IT430 Parts list manual

REV 1.5
TECHNICAL DESCRIPTION
Fastrax IT430 OEM GPS Receiver
This document describes the electrical connectivity and main
functionality of the Fastrax IT430 OEM GPS Receiver.
June 30, 2010
Fastrax Ltd.

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TRADEMARKS
Fastrax is a registered trademark of Fastrax Ltd.
All other trademarks are trademarks or registered trademarks of their respective holders.
COPYRIGHT
© 2010 Fastrax Ltd.
DISCLAIMER
This document is compiled and kept up-to-date as conscientiously as possible. Fastrax Ltd.
cannot, however, guarantee that the data are free of errors, accurate or complete and,
therefore, assumes no liability for loss or damage of any kind incurred directly or indirectly
through the use of this document. The information in this document is subject to change
without notice and describes only generally the product defined in the introduction of this
documentation. Fastrax products are not authorized for use in life-support or safety-critical
applications. Use in such applications is done at the sole discretion of the customer. Fastrax
will not warrant the use of its devices in such applications.

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CHANGE LOG
Rev. Notes Date
1.0 Initial documentation 2010-02-18
1.1 Added notes on power up and power removal; relaxed
operation temperature range between -40ºC and -30ºC;
increased module height to 1.85 mm, updated table 3
(added I/O type vs. operating mode); added note and
spec on ESD sensitivity and avoid ultrasonic exposure
2010-04-19
1.2 Updated power consumption and added notes on
internal regulator mode; added note on ESD sensitivity
of the antenna input; added out-of-band RF_IN power
spec to abs. max
2010-05-11
1.3 Added chapter on reset state. Clarified low power
operation modes (added APM; notes on PTF &
SiRFAware);
2010-06-04
1.4 Added two module variants, corrected volatile data RAM
clearing at reset; added Tape&Reel spec; added chapter
on Jammer Remover; clarified operating temperature
range down to -40… -30C with relaxed performance
2010-06-28
1.5 Corrected external pull up resistors requirement to
DR_I2C bus
2010-06-30

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CONTENTS
_______________________________________________________________________
1 GENERAL DESCRIPTION...............................................................................7
1.1 Block diagram.......................................................................................8
1.2 Frequency plan .....................................................................................8
2 SPECIFICATIONS ...........................................................................................9
2.1 General..................................................................................................9
2.2 Absolute Maximum Ratings ...............................................................10
3 OPERATION.................................................................................................. 11
3.1 Operating modes ................................................................................11
3.2 Full on mode ....................................................................................... 11
3.2.1 Host port configuration .............................................................11
3.2.2 Power management system modes.......................................... 11
3.3 Hibernate state ...................................................................................12
3.4 Reset state ..........................................................................................13
4 CONNECTIVITY ............................................................................................14
4.1 Signal assignments ............................................................................ 14
4.2 Power supply ......................................................................................16
4.3 Host Port Configuration: RTS_N and CTS_N .................................... 18
4.3.1 Host Port UART .......................................................................18
4.3.2 Host Port SPI ........................................................................... 18
4.3.3 Host Port I
2
C ............................................................................19
4.4 ON_OFF control input ........................................................................19
4.5 Reset input..........................................................................................20
4.6 Antenna input .....................................................................................20
4.6.1 Active GPS antenna ................................................................. 21
4.6.2 Jamming Remover ...................................................................21
4.7 Dead Reckoning I
2
C bus .................................................................... 21
4.8 Time Mark TM .....................................................................................22
4.9 WAKEUP ............................................................................................. 22
4.10 Interrupt inputs EIT and EIT2............................................................. 22
4.10.1 EIT ...........................................................................................22
4.10.2 EIT2 .........................................................................................23
4.11 ELCK ...................................................................................................23
4.12 TSYNC ................................................................................................. 23

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4.13 Mechanical dimensions and contact numbering .............................. 23
4.14 Test points ..........................................................................................25
4.15 Suggested pad layout ........................................................................26
5 MANUFACTURING ....................................................................................... 27
5.1 Assembly and soldering .................................................................... 27
5.2 Moisture sensitivity ............................................................................ 27
5.3 Marking ............................................................................................... 27
5.3.1 Module variants........................................................................ 28
5.4 Tape and reel ......................................................................................29
6 REFERENCE DESIGN................................................................................... 30
6.1 Reference circuit diagram..................................................................30
6.2 PCB layout issues ..............................................................................31
7 IT430 APPLICATION BOARD ....................................................................... 33
7.1 Card Terminal I/O-connector ............................................................. 33
7.2 Bill of materials .................................................................................. 35
7.3 Circuit drawing ...................................................................................38
7.4 Assembly drawing, Top side.............................................................. 39
7.5 Artwork, layer 1 (Top).........................................................................39
7.6 Artwork, layer 2 ..................................................................................40
7.7 Artwork, layer 3 ..................................................................................40
7.8 Artwork, layer 4 (Bottom)...................................................................41

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COMPLEMENTARY READING
The following reference documents are complementary reading for this document:
Ref. # File name Document name
I SiRFstarIV Brochure.pdf SiRFstar IV Brochure
II CS-129435-MA-N.pdf NMEA Protocol Reference
Manual
III CS-129291-DC-2.pdf One Socket Protocol (OSP)
Interface Control Document
IV Reflow_soldering_ profile.pdf Soldering Profile

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1 GENERAL DESCRIPTION
The Fastrax IT430 is an OEM GPS receiver module, which provides the SiRFstar IV receiver (ref
I) functionality using the state of the art SiRF GSD4e chip (ROM variant). The module has ultra
small form factor 9.6x9.6 mm, height is 1.85 mm nominal (2.15 mm max). The Fastrax IT430
receiver provides low power and very fast TTFF together with weak signal acquisition and
tracking capability to meet even the most stringent performance expectations.
The module provides complete signal processing from antenna input to host port in either NMEA
messages (ref II) or in SiRF OSP binary protocol (ref III). The module requires a single power
supply VDD +1.8V. The host port is configurable to UART, SPI or I
2
C during power up. Host data
and I/O signal levels are 1.8V CMOS compatible, inputs are 3.6V tolerable.
The SiRFstar IV provides a new feature called SiRFAware (also referenced as Micro Power
Management mode), which enables fast TTFF for Snap start mode while consuming only 500 uA
average current (typ.) in autonomous Hibernate state. The receiver does wakeup autonomously
to calibrate internal GPS time and to collect ephemeris data while maintaining 1 sec Snap fix
capability. The module supports also connectivity to optional external sensors for Dead
Reckoning like 3D-accelerometer on dedicated DR_I
2
C bus.
The receiver is also optionally self-assisted since the Client Generated Extended Ephemeris
(CGEE) calculation is embedded in the software without any resources required from the host.
The CGEE data is stored on external serial EEPROM memory on the dedicated DR_I
2
C bus (can
be optionally transferred to/from host).
The SiRFstar IV contains also a CW Jammer Remover, which will track and remove up to 8 CW
(Carrier Wave) type signals up to 80dBHz (equals to -90 dBm typ.) signal level.
The antenna input supports passive and active antennas and provides also an input for externally
generated antenna bias supply.
This document describes the electrical connectivity and main functionality of the Fastrax
IT430 OEM GPS Receiver module.

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1.1 Block diagram
Figure 1 Block diagram
1.2 Frequency plan
Clock frequencies generated internally at the Fastrax IT430 receiver:
•32768 Hz real time clock (RTC)
•8 MHz switched mode regulator (when enabled by command)
•16.369 MHz master clock (TCXO or crystal)
•3142.96 MHz local oscillator of the RF down-converter

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2 SPECIFICATIONS
2.1 General
Table 1 General Specifications
Receiver GPS L1 C/A-code, SPS
Chip set & Tracking sensitivity SiRF IV, GSD4e, -163 dBm
Channels 48
Update rate (default) 1 Hz max (fix rate configurable)
Supply voltage, VDD +1.71… +1.89 V
Supply voltage ripple, VDD 54 mV(RMS) max @ f = 0… 3MHz
15 mV(RMS) max @ f > 3 MHz
Power consumption (note 1) 56 mW (Switcher mode) or 68 mW (LDO
mode) typ. @ VDD=1.8 V
Power consumption (Hibernate
state)
36 uW typical @ 1.8 V
Antenna net gain range 0…+25 dB
Antenna bias voltage VDD_ANT +/- 5.5 V (externally generated)
Antenna bias current VDD_ANT 70 mA rated max
Storage temperature -40ºC…+85ºC
Operating temperature -40ºC…+85ºC (note 2)
Host port configuration SPI (default), UART or I
2
C
Serial port protocol (UART) NMEA (configurable to SiRF binary OSP)
Serial data format (UART) 8 bits, no parity, 1 stop bit
Serial data speed (UART) 4800 baud (configurable)
I/O signal levels CMOS compatible: low state 0… +0.4 V max;
high state 0.75…1.0xVDD. Inputs are 3.6 V
tolerable
I/O output sink/source capability +/- 2 mA max
I/O input leakage +/- 10 uA max
TM output (1PPS) 200ms high pulse, rising edge +/-1 us
accuracy
Note 1: Module boots for internal 1.2V LDO regulator mode. Internal Switcher mode
regulator reduces power consumption and requires a binary command from host to enable
Switcher mode, see chapter 4.2.
Note 2: Operation in the temperature range –40°C… –30°C is allowed but Time-to-First-Fix
performance and tracking sensitivity may be degraded.

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2.2 Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings
Item Min Max unit
Operating and storage temperature -40 +85 ºC
Power dissipation - 200 mW
Supply voltage, VDD -0.3 +2.2 V
Supply voltage, VDD_ANT -5.5 +5.5 V
Supply current, VDD_ANT (must be
externally limited)
- +150 mA
Input voltage on any input connection -0.3 +3.6 V
ESD voltage (RF_IN, Machine Model) - +50 V
RF_IN input power (in band) - +10 dBm
RF_IN input power (out of band <1460
MHz or >1710 MHz)
- +15 dBm
Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage.
These are stress ratings only. Operation beyond the Recommended Operating Conditions, Table
1, is not recommended and extended exposure beyond the Recommended Operating Conditions
can affect device reliability.
Note that module is Electrostatic Sensitive Device (ESD).

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3 OPERATION
3.1 Operating modes
After power up the IT430 module boots from the internal ROM to Hibernate state. The module
operation requires ON_OFF interrupt to wakeup for Normal (Navigation, Full on) mode. Modes of
operation:
•Full on (Navigation, Full Power)
oPower management system modes
•Hibernate state
•Reset state
3.2 Full on mode
The module will enter Hibernate state after first power up. The Navigation mode will start after
waking up from Hibernate state in cold start mode by sending ON_OFF signal interrupt pulse
from host. Power consumption will vary depending on the amount of satellite acquisitions and
number of satellites in track. This mode is also referenced as Full on, Full Power or Navigation
mode.
Navigation is available and any configuration settings are valid as long as the VDD power supply
is active. When the VDD is powered off, settings are reset to factory configuration and receiver
performs a cold start on next power up.
VDD supply is intended to be kept active all the time and navigation activity is suggested to be
controlled to low quiescent Hibernate state via ON_OFF control input. See also chapter 3.3 and
4.2.
3.2.1 Host port configuration
User can select the host port configuration between UART, SPI (slave) and I
2
C (master/slave)
during power up boot. The port selection is not intended to be changed dynamically but only set
once at power up. Default host port is SPI and other host port configurations requires external
pull down or pull up resistor at CTS_N and RTS_N signals, see chapter 4 for details.
3.2.2 Power management system modes
The IT430 module supports also SiRF operating modes for reduced average power consumption
(ref III) like Adaptive TricklePower
TM
, Advanced Power Management, Push-to-Fix
TM
and
SiRFAware
TM
modes:
1. Adaptive TricklePower (ATP): In this mode the receiver stays at Full on power state for
200… 900ms and provides a valid fix. Between fixes with 1… 10 sec interval the receiver
stays in Hibernate state. ATP mode is configurable with SiRF binary protocol message
ID151 (ref III). The receiver stays once in while in Full on power mode automatically (typ.

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every 1800 sec) to receive new ephemeris data from rising satellites or if received signal
levels drop below certain level.
2. Advanced Power Management (APM): APM allows power savings while ensuring that the
quality of the solution is maintained when signal levels drop. APM does not engage until
all necessary information is received. Host can configure e.g. number of APM cycles
(continuous or up to 255), time between fixes (10… 180 sec), Power duty cycle (5…
100%) and max position error. Rest of the time the receiver stays in Hibernate state. This
mode is configurable with SiRF binary protocol message ID53 (ref III).
3. Push-to-Fix (PTF): In this mode the receiver is configured to wake up periodically, typically
every 1800 sec (configurable range 10… 7200 sec), for position update and to collect
new ephemeris data from rising satellites. Rest of the time the receiver stays in
Hibernate state. When position update is needed, the host can wake up the receiver by
ON_OFF control input interrupt (pulse low-high-low >90us after which the receiver
performs either Snap or Hot start and a valid fix is available within 1… 8 seconds typ.
This mode is configurable with SiRF binary protocol message ID151 & 167 (ref III).
4. SiRFAware (aka Micro Power Management mode, MPM): In this mode the receiver is
configured to wake up periodically for 18 sec, typically every 1800 sec, to collect new
ephemeris data from rising satellites, and also every 60 seconds for 250 ms to calibrate
internal navigation state and GPS time estimate. Rest of the time the receiver stays in
Hibernate state and module achieves 0.5 mA typ. average current drain. The host wakes
up the receiver by ON_OFF control input interrupt (pulse low-high-low >90us) to Full on
power mode after which the receiver performs Snap start and a valid fix is available
within 1 second typ. After valid fix, operation can return back to Micro Power
Management mode by re-sending the configuration binary message from host. This
mode is configurable with SiRF OSP (One Socket Protocol) binary protocol message
MID218 (ref III).
These power management modes are also configurable with SiRF OSP binary protocol message
MID 218, Power Mode Request (ref III). Note that position accuracy is somewhat degraded in
power management modes when compared to full power operation.
3.3 Hibernate state
Hibernate state means a low quiescent (20uA typ.) power state where only the internal I/O Keep
Alive, non-volatile RTC and backup RAM block is powered on. Other internal blocks like digital
baseband, data RAM and RF are internally powered off. The main supply input VDD shall be
kept active all the time, even during Hibernate state. Waking up from and entering in to Hibernate
state is controlled by host interrupt at ON_OFF control input (rising edge toggle low-high-low
>90us).
During Hibernate state the I/O Keep Alive is still active, thus I/O signals keep respective states
except TX and RX signals, which are configured to high input impedance state.
The receiver wakes up from Hibernate state on the next ON_OFF interrupt (at rising edge) using
all internal aiding like GPS time, Ephemeris, Last Position etc. resulting to a fastest possible
TTFF in either Hot or Warm start modes.
If Client Generated Extended Ephemeris (CGEE) operation is required to improve TTFF over
long Hibernate periods up to 3 days, the CGEE data must be stored either on external EEPROM
(128kB) connected at DR_I
2
C bus or transferred to host memory via host port prior entering to

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Hibernate state. The host must send the CGEE data back to the module after wake up from
Hibernate state.
3.4 Reset state
Reset state is entered internally after power up until the internal RTC clock wakes up after which
internal reset state is relaxed. Host can override reset state via RESET_N (pin 12) input, low
state active. Normally external reset override is not required but if power shall be removed
abruptly see chapter 4.2 for reset suggestion.
Note that reset clears data RAM content, e.g. downloaded ROM patch code. Backup RAM
content is not cleared and thus fast TTFF is possible after reset.

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4 CONNECTIVITY
4.1 Signal assignments
The I/O signals are available as soldering (castellated) pads on the bottom side of the module.
These pads are also used to attach the module on the motherboard. All I/O signal levels are 1.8V
CMOS compatible and inputs are 3.6V tolerable. All unconnected I/O signals can be left
unconnected when not used, unless instructed to use external pull up/down resistor.
Table 3 Connections
Con
tact
Signal
name
I/O type
Full on
I/O type
Hibernate
I/O type
Reset
Signal description
1 VDD P,I P,I P,I Power supply input +1.8V nom.
De-couple externally with e.g.
4.7uF low ESR ceramic capacitor.
2 DR_I2C_D
IO
S,C,B S,C,B HZ - GPIO0
- Dead reckoning I
2
C host bus data
(SDA). Use external pull up
resistor when bus is used. Can be
left unconnected when not used.
3 VDD_ANT P,I P,I P,I Antenna bias power supply input
up to +/-5.5V. De-couple signal
further externally, see Application
Circuit Diagram.
4 GND G G G Ground
5 GND G G G Ground
6 RF_IN A,I,O A,I,O A,I,O Analog Antenna input (50 ohm),
Antenna bias voltage output
(filtered from VDD_ANT)
7 GND G G G Ground
8 GND G G G Ground
9 GND G G G Ground
10 GND G G G Ground
11 CTS_N S,C,B,
PD(a)
S,C,B, PD HZ - GPIO6
- SPI_CLK slave SPI clock input
(CLK)
- UART_CTS_N UART clear to
send (CTS), active low
- Host port boot strap, see 4.3
Pull up externally for UART.
12 RESET_N C,I,PU C,I,PU C,I,PU External reset input, active low.
Can be left unconnected when not

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used.
13 RTS_N S,C,B,
PU(a)
S,C,B, PU HZ - GPIO7
- SPI_SS_N slave SPI chip select
(CS#), active low
- UART_RTS_N UART ready to
send (RTS), active low
- Host port boot strap, see 4.3
Can be left unconnected when not
used.
14 GND G G G Ground
15 TX S,C,B HZ HZ - SPI_DO slave SPI data output
(MISO)
- UART_TX UART data transmit
(TX)
- I2C_CLK I²C bus clock (SCL)
16 RX S,C,B HZ HZ - SPI_DI slave SPI data input
(MOSI)
- UART_RX UART data receive
(RX). Must be driven by host or
use external pull up resistor (UART
RX).
- I2C_DIO I²C bus data (SDA)
17 ON_OFF S,C,B S,C,B S,C,B Power control input used to
command the module On
(Navigation) or Off (Hibernate).
Must be driven by the host.
18 GND G G G Ground
19 GND G G G Ground
20 TM S,C,B S,C,B HZ - GPIO5
- Time mark output signal (default
1PPS)
- Optionally GPS_ON, power
control output signal for e.g.
external LNA bias control.
- Optionally RTC_CLK, buffered
RTC clock output. Can be left
unconnected when not used.
21 WAKEUP C,O C,O C,O Wakeup output for control of
external regulator, e.g. battery to
1.8V for the VDD supply input
when full power mode is entered.
Can be used also externally for
active antenna bias control, active
high = high current/bias on. Can
be left unconnected when not
used.

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22 EIT S,C,B S,C,B HZ - GPIO4
- External interrupt input signal.
Provides an interrupt on either
high or low logic level. Can be left
unconnected when not used.
23 EIT2 S,C,B S,C,B HZ - GPIO8
- EIT2 external interrupt input #2.
Provides an interrupt on either
high or low logic level or edge-
sensitive interrupt. Can be left
unconnected when not used.
24 GND G G G Ground
25 ECLK S,C,B S,C,B HZ - GPIO3
- Reserved for ECLK clock input
for frequency aiding applications.
Can be left unconnected when not
used.
26 TSYNC S,C,B S,C,B HZ - GPIO2
- Reserved for TSYNC that is the
time transfer strobe input used in
A-GPS precise time aiding. Can be
left unconnected when not used.
27 DR_I2C_C
LK
S,C,B S,C,B HZ - GPIO1
- Dead reckoning I²C host bus
clock (SCL). Use external pull up
resistor when bus is used. Can be
left unconnected when not used.
28 GND G G G Ground
Con
tact
Signal
name
I/O type
Full on
I/O type
Hibernate
I/O type
Reset
Signal description
Notes: (a) Pull Up/down resistor present only shortly after power up.
Legend: A=Analogue, B=Bidirectional, C=CMOS, G=Ground, HZ=High Impedance, I=Input,
O=Output, P=Power, PU=Internal Pullup 86 kohm typ., PD=Internal Pulldown 91 kohm typ.,
S=Schmitt Trigger (when Input). Note that with Birectional I/O the firmware has control for input
vs. output I/O type depending on the firmware function.
4.2 Power supply
The IT430 module requires only one power supply VDD. Keep the supply active all the time in
order to keep the non-volatile RTC & RAM active for fastest possible TTFF.
VDD supply intended to be kept alive all the time. First power up may take 300ms typ. due to
internal RTC startup time (may increase up to 5 seconds at cold temperature) after which the
module will enter to Hibernate state. The host may try wakeup the module via successive

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ON_OFF interrupts sent every second until the host port messages are outputted and/or
WAKEUP output is at high state.
When power supply is intended to be removed, it is suggested that prior power removal a serial
message in binary (MID 205) or NMEA format ($PSRF117,16*0B<CR><LF>) is sent to module to
shut down firmware operations orderly. Otherwise e.g. external EEPROM may get corrupted if
power down happens in the middle of EEPROM writing, which may increase in TTFF. If external
EEPROM is also used for ROM patch code, the abrupt power removal may cause patch code
corruption that may end to system failure.
Second option for orderly shutdown is to send ON_OFF interrupt prior VDD removal. Operations
shutdown may take anything between 10 to 900 ms depending upon operation in progress and
messages pending and hence is dependent upon serial interface speed and host port type.
If it is likely that VDD supply will be removed abruptly, suggestion is to add external voltage
monitor to detect under voltage condition below 5% nominal supply voltage and to drive
RESET_N signal to reset condition (low state). This important especially when external EEPROM
or data storage at host is used. VDD supply off-time is suggested to be over 10 seconds to next
power up in order to clear all internal backup RAM content and to minimize risk for wrong backup
data.
Main power supply VDD current varies according to the processor load and satellite acquisition.
Typical VDD peak current is 56 mA (typ.) during waking for Full on power up. Typical VDD
current in low power Hibernate state is 20uA. The external power supply can be using dual
low/high current modes, which can be controlled via the WAKEUP output signal (high current =
WAKEUP high) as indication when full power is required by the module. The external power
supply should be able to provide full current to VDD within 9 ms after WAKEUP low-to-high
transition.
The internal 1.2V regulator is powered from VDD supply and it boots for LDO mode. The internal
1.2V power supply includes also Switcher mode regulator (f = 8 MHz). The host may reduce
power drain by enabling the Switcher mode via sending a binary message from the host
(Message ID 178 TrackerIC, Sub ID 2 TrackerConfig; contact Fastrax support for details).
By-pass the VDD supply input by a low ESR ceramic de-coupling capacitor (e.g. 4.7 uF) placed
nearby VDD pin to ensure low ripple voltage at VDD. Ensure that the VDD supply ripple voltage
is low enough: 54 mV(RMS) max @ f = 0… 3MHz and 15 mV(RMS) max @ f > 3 MHz.
NOTE
VDD supply is intended to be active all the time. Abrupt
removals of VDD supply are not suggested and if required,
use an external voltage detector to force reset at VDD under
voltage conditions.
De-couple the VDD input externally with e.g. 4.7uF low ESR
ceramic capacitor connected to GND. The module has also
internal a low ESR (~0.01 ohm) by-pass capacitor at VDD
supply input. Ensure that the external regulator providing
VDD supply is suitable for loads with low ESR ceramic
capacitors.

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VDD supply ripple voltage: 54 mV(RMS) max @ f = 0… 3MHz
and 15 mV(RMS) max @ f > 3 MHz.
4.3 Host Port Configuration: RTS_N and CTS_N
User can select the host port configuration between UART, SPI (slave) and I
2
C (master/slave)
during power up boot. At system reset, the host port pins are disabled, so there will be no port
conflict occurring. Depending on the host port type, the software enables the correct port drivers,
sets up the port hardware, configures the pins according to the port type and begins operations.
The port selection is not intended to be changed dynamically but only set once at power up.
Default host port is SPI (selected by internal pull up/down resistors that are present during power
up) and other host port configurations requires connection of external pull down (to 0V) or pull up
(to 1.8V) resistor at CTS_N and RTS_N pins, see table below.
Table 4 Host port boot strap
Host port RTS_N CTS_N
UART - Pull up 10 kohm
SPI (default) - -
I
2
C Pull down 10 kohm -
4.3.1 Host Port UART
UART is normally used for GPS data reports and receiver control. Serial data rates are selectable
from 1200 baud to 1.8432 Mbaud. Default baud rate is 4800 baud; default protocol is NMEA
(switchable to SiRF OSP binary). RX signal must be driven by host or pulled up externally.
4.3.2 Host Port SPI
The host interface SPI is a slave mode SPI:
■Supports both SPI and Microwire formats
■An interrupt is provided when the transmit FIFO and output serial register (SR) are both empty
■The transmitter and receiver each have independent 1024B FIFO buffers
■The transmitter and receiver have individual software-defined 2-byte idle patterns
■SPI detects synchronization errors and is reset by software
■Supports a maximum clock of 6.8MHz.
■A timer is provided to generate an interrupt when:

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■The receiver FIFO is not empty
■The receiver FIFO fill level does not exceed the alarm level
■There are no received FIFO input for a programmable number of SPI source clock ticks
4.3.3 Host Port I
2
C
The I²C host port interface supports:
■Operation up to 400kbps
■Individual transmit and receive FIFO lengths of 64B
■640µS interrupt intervals when the FIFO fill point is programmed for 32B
■Interrupts are available when the FIFO is empty / full or when there are error conditions
■2 primary I²C modes exist:
■Master transmit where module is master
■Slave receive where module is slave
The operation of the I²C with a master transmit and slave receive mimics a UART operation,
where both module and host can independently freely transmit. It is possible to enable the master
transmit and slave receive at the same time,
4.4 ON_OFF control input
The ON_OFF control input must be used by the host to wakeup the module after first power
up and to control the receiver activity between Normal and Hibernate states and also to
generate interrupt in Push-to-Fix and SiRFAware modes of operation.
The module will boot to Hibernate state after power up. First ON_OFF interrupt wakes up
the module for Normal (Navigation) operation. Consequent ON_OFF interrupts switch the
operation mode between Hibernate and Normal modes.
The ON_OFF interrupt is generated by rising edge of a low-high-low toggle, which should be
longer than 90us and less than 1s (suggestion is abt. 100ms pulse length). Do not generate
ON_OFF interrupts less than 1 sec intervals. Especially take care that any multiple switch
bounce pulses are filtered out.
During Hibernate state the I/O Keep Alive is still active, thus I/O signals keep respective states
except TX and RX signals, which are configured to high input impedance state.

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IT430_Tech_doc.doc
Figure 2 Suggested ON_OFF Hibernate control timing diagram.
NOTE
Do not generate multiple ON_OFF interrupts less than 1 sec
intervals. Especially filter out multiple pulses generated by a
mechanical switch bounce.
4.5 Reset input
The RESET_N (active low) signal provides external override of the internally generated power
up/down reset. Normally external control of RESET_N is not necessary. When power supply
VDD may be abruptly removed, suggestion is to use externally generated reset by means of
external VDD voltage monitor.
When RESET_N signal is used, it will force volatile RAM data loss (e.g. ROM patch code). Non-
Volatile Backup RAM content is not cleared and thus fast TTFF is possible after reset. The input
has internal pull up resistor 86 kohm typ. and leave it not connected (floating) if not used.
4.6 Antenna input
The module supports passive and active antennas. The antenna input RF_IN impedance is 50
ohms and it provides also a bias supply low-pass filtered form VDD_ANT supply. Note that
antenna input is ESD sensitive. With passive antennas the ESD performance can be improved
by connecting VDD_ANT supply input to GND.
NOTE
With Passive antennas leave VDD_ANT not connected or
connect to GND.