First International Computer VY050 User manual

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First International Computer,Inc
Portable Computer Group HW Department
Board name : MotherBoard Schematic
Version : 0.3
Manager Sign by: AVERY
Total confirm by: AVERY
Drawing by : Spruce
VY050
Initial Date : Nov/ 18/ 2008
Confidential
Project :
Title
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
C
149Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.

8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Penryn
P10~15
P17~22
CORE
Processor
CPU
Intel
P47
P7,8
Cantiga
P9
Thermal
Sensor
DMI
FSB
Mem_A Bus
3. Block Diagram :
P46
VCCP
CPU
Lid Switch
USB 2.0
P28
USB 0,1,2
Intel NB
(G)MCH
Intel SB
ICH9M
LCD
P24
P16
DDRII SODIMM0 (A)
DDRII SODIMM1 (B)
P17
Mem_B Bus
PCIE_3
Azalia
LPC BUS
P23
Flash ROM
BIOS
P32
LED
P26
RTS5158E
ALCORCardReader
3 in 1
P32
USB 3,4
MAIN SW CNN/DIP SW
DDR2 800/667 MHz
DDR2 800/667 MHz
(667/800/1066 MHz)
(x4)
PCIE_2
SPI
P35
Speaker
P29
Mini Card (Robson)
P29
Mini Card (WLAN)
LAN 10/100/1000M
P33,34
RTL 8102E
RJ-45
PCIE_6
P35
P28P42
CCD
Glide PadInt. KB
P30
PMX
MB90F372
P30
P37
P31
Express Card
PCIE_1
USB 2.0
MDC
P28
RJ-11
CRT
P25
Reset Circuit
P23
CLKGEN
RTM875N-606-VD-GR
P18
RTC Bat
P20
P27
HDD
P27
SATA BUS
CDROM
SATA BUS
Mic In HP/SPDIF
P36
P36
Line In
P36
ALC269
P35
AzaliaCodec
Charger
P42
P43
P44
1.5VDDM
1.8/1.05/0.9VDD
VDD CORE
P46
CPU CORE
P45
P47
ACIN/ DCIN
P41
3VDD/5VDD
P42
BT
Block Diagram
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2) 8751-8751
C
2 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
FirstInternational Computer, Inc.

8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Voltage Rails
DCIN
VCC_CORE
Primary DC system power supply
Core Voltage for CPU
3.3V switched power rail by SUSTAT_B#
PMU3V 3.3V always on power rail by LATCH or ACIN
PMU5V 5.0V always on power rail by LATCH or ACIN
5VDDA 5.0V power rail by PSUSC#
3VDDM 5.0V switched power rail by SUSTAT_B#5VDDM
F
R
Inductor
Resistor
Q
Connector
C
Fuse
=
CN
Crystal and Osc
RP
D
UResistor Pack Arbitrary Logic Device
Diode
Part Naming Conventions
Transistor
L
Y
Capacitor
=
=
=
=
=
=
=
=
=
Active Low signal
Net Name Suffix
# =
1.05VDDM 1.8V power rail for DDRII by PSUSC#
0.9V DDRII Termination Voltage by SUSTAT_B#
1.8VDDS
0.9VDDT_DDRII
3VDDA
4. Nat name Description:
1.5VDDM
1.05V power rail for AGTL+ termination/Core for GMCH by SUSTAT_B#
1.5V power rail for CPU PLL/DMI;PCIE;DDRII DLLs for GMCH/Core;PCIE
for ICH7m by SUSTAT_B#
Differential Impedance for Microstrip
55 ohm +/- 15%
100 ohm +/- 15%
PCIE Bus
Single End Impedance
85 ohm +/- 20%
95 ohm +/- 15%
70 ohm +/- 20%
100 ohm +/- 15%
SDVO
70 ohm +/- 20%
95 ohm +/- 15% DMI Bus
55 ohm +/- 15%
100 ohm +/- 15%
Host Bus
55 ohm +/- 15%
55 ohm +/- 15%
95 ohm +/- 15%
DDR2 Bus
55 ohm +/- 15%
95 ohm +/- 15%
90 ohm +/- 15%
DDR2 CLK
100 ohm +/- 15%
90 ohm +/- 15%
DDR2 Strobe
95 ohm +/- 15%
100 ohm +/- 15%
110 ohm +/- 15%
Lan
SRC Clock
95 ohm +/- 15%
110 ohm +/- 15% IEEE1394
55 ohm +/- 15%
100 ohm +/- 15%
Host Clock
100 ohm +/- 15%
50 ohm +/- 15%
USB
Differential Impedance for Stripline
55 ohm +/- 15%
55 ohm +/- 15%
LVDS
42 ohm +/- 15%
100 ohm +/- 15%
SATA
5. BoardStackup Description
PCB Layers
Layer 3
Solder Side,Microstrip signal Layer
Layer 5
Layer 6
Component Side, Microstrip signal Layer
Power Plane
Layer 1
Layer 4
Ground Plane
Stripline Layer(High Speed)
Layer 2 Stripline Layer(High Speed)
3.3V power rail by PSUSC#
5. Timing Diagram
14. Candiga GM45 Power(5/6)
2. Block Diagram
6. Schematic Modify
13. Candiga GM45 Power(4/6)
1. Title
10. Candiga GM45 Host(1/6)
18. DDRII SDRAMSO-DIMM1
11.Candiga GM45 DMI/Graphic(2/6)
15. Candiga GM45 GND(6/6)
17. DDRII SDRAMSO-DIMM0
16. Clock Generator
9. CPU Thermal
12. Candiga GM45 DDRII(3/6)
7. Penryn Processor(1/2)
3. ANNOTATIONS
33. LAN RTL 8111C
27. HDD CNN / ODD CNN
30. INT KB / GP / SW CNN
34. TRANSFORMER
25. CRT CNN
38. ScrewHole
26. DIP SW / LED / LID SW
22. ICH9MPower/GND(4/4)
19. ICH9MPCI/PCIE/DMI(1/4)
23. Reset Circuit / SPI
21. ICH9MGPIO(3/4)
31. Express Card / CCD / BT
24. LCD CNN
32. Card-Reader RTS5158E
28. USB CNN / MDC CNN
20. ICH9MCPU/IDE/SATA(2/4)
42. Charger
47. CPU CORE
35. Azalia ALC269 Codec
37. PMX
36. HP / MIC / Int. MIC
49. SW Board
48. Audio Board
46. VDD CORE
43. 3/5VDDA/M, PMU3/5V
44. 1.5VDDM
45. 1.8VDDS / 0.9VDDS / 1.05VDDM
39. block
41. ADPIN, BATIN, ADPOUT1
29. Mini-WLAN / Robson
40. Power Block
8. Penryn Processor(2/2)
4. DDRII Layout Guideline
Annotations
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2) 8751-8751
C
349Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Crestline DDRII Layout Guidelines
DDRII SignalGroups
Data
Group Signal Name
Control-to-Clock
Signal Group Minimum Length Maximum Length
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe
Clock - 1.0"
Clock - 1.0"
Clock - 0.5"
Clock - 0.0"
Clock + 1.0"
Strobe - 220mils
8. Layout Guideline :
SA_DQ[63..0]/SB_DQ[63..0]
SA_DM[7..0]/SB_DM[7..0]
SA_DQS[7..0]/SA_DQS#[7..0]
SB_DQS[7..0]/SB_DQS#[7..0]
SA_RAS#/SB_RAS#
SA_BS[2..0]/SB_BS[2..0]
SA_MA[13..0]/SB_MA[13..0]Address
SA_CAS#/SB_CAS#
SA_WE#/SB_WE#
SM_CS#[3..0]Control SM_CKE[3..0]
SM_ODT[3..0]
Clock SM_CK[3..0]
SM_CK#[3..0]
SA_RCVENOUT#/SB_RCVENOUT#FeedBack SA_RCVENIN#/SB_RCVENIN#
Length Matching and Length Formulas
Clock + 1.0"
Strobe - 180mils
CLK group: SM_CK[3..0],SM_CK#[3..0]
GMCH
P1
P1
L0
L0
L1
L1
L2
L2
S1
S1
SO-DIMM
Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Differential Pair Point-to-Point
Ground
42 +/- 15%
70 +/- 20%
Nominal Trace Width Inner Layer : 7 mils
Outer Layer : 8 mils
Outer Layer : 5 mils
Nominal CKto CK# Spacing
(edge to edge) Inner Layer : 4 mils
Minimum Serpentine Spacing Inner Layer : 12 mils
Outer Layer : 15 mils
Minimum Spacing to Other DDR2 Inner Layer : 16 mils
Outer Layer : 20 mils
Minimum Isolation Spacing to non-DDR2 25 mils
PackageLength Range- P1 1000 mils +/- 250 mils
Trace Length Limit - L0 Max =50 mils (Escape)
Trace Length Limit - L1 Max =500 mils (Breakout)
Stub Length S1-Stub from via to SO-DIMM Max =200 mils (Breakin)
MB Length Limits - L0 +L1 +L2 +S1 Min = 500 mils
Max = 4500 milsTotal Length - P1 +L0 +L1 +L2 +S1 Max = 4000 mils
Total Length for Channel A: X0
TotalLength for Channel B : X1
Maximim Via Count 2 (Per side)
SCK to SCK# Length Matching Match total length to within 5mils
Clock to Clock Length Match
(Total Length) Match Channel A clocks to X0 +/- 20mils
Match Channel A clocks to X1 +/- 20mils
Breakout Exceptions (Reduce geometries
for GMCHbreak-out region) Inner Layer : 4/12 mils to other DDR2
Outer Layer : 5/15 mils to other DDR2
Max. breakout length is 500 m ils
Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region) CK to CK# spacing rule waived at connector spacing of 15 mils to
other DDR2
Max. breakin length is 2 00 mils
Escape Breakout Breakin
4/4/12 7/4/16 8/5/15
Outer Layer : 5 mils
Inner Layer : 4mils spacing allowe d
L1
Inner Layer : 12 mils
55 +/- 15%
Max =500 mils (Breakout)
Max =50 mils (Escape)
Outer Layer : 10 mils
Point-to-Point with parallel termination
GMCH
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 +L1 +L2 +S1 -
From GMCH ball to SO-DIMM pad
Trace Length Limit - L1
Package Length P1
Outer Layer : 15 mils
S1
Nominal Trace Width
Max =200 mils (Breakin)
8/5/15
Breakout
3
Total Length - P1 +L0 +L1 +L2 +S1 -
From GMCH die to SO-DIMM pad
Inner Layer : 4 mils
Maximim Via Count
Minimum CTRL Trace Spacing
7/4/16
Max. breakout length is 500 m ils
Min = 500 mils
25 mils
Topology
4/4/12
Max = 4500 mils
Inner Layer : 8 mils
Minimum Spacing to Other DDR2
L2
Reference Plane
Escape
(CLK-1.0") </= CTRL </= (CLK-0.0")
Max = 5000 mils
Ground
P1
750 mils +/- 200 mils
Minimum Isolation Spacing to non-DDR2
SO-DIMM
L0
Control group: SM_CKE[3..0],SM_CS#[3..0],SM_ODT[3..0]
Characteristic Trace Impedance
L3
CTRL to SCK/SCK # Length Matching
(Total Length including package)
Breakout Exceptions (Reduce geometries
for GMCHbreak-out region)
Trace Length Limit - L0
Vtt
Max = 1500 milsTrace Length L3
Parallel Termination Resistor 56 +/- 5%
Outer Layer : 5mils spacing allowed
P1
Max = 5000 mils
Minimum CMD Bus Trace Spacing
750 mils +/- 350 mils
Ground
Package Length P1
L3
Maximim Via Count
Total Length - P1 +L0 +L1 +L2 +S1 -
From GMCH die to SO-DIMM pad
Outer Layer : 10 mils
Min = 500 mils
CTRL to SCK/SCK # Length Matching
(Total Length including package)
Nominal Trace Width
4/4
L1
Max = 1500 mils
3
Max = 4500 mils
Trace Length L3
Breakout
Inner Layer : 6 mils
4/6,5/10
Max =200 mils (Breakin)
55 +/- 15%
Minimum Isolation Spacing to non-DDR2
Parallel Termination Resistor
Vtt
25 mils
Trace Length Limit - L0
Characteristic Trace Impedance
Topology
Outer Layer : 5 mils
SO-DIMM
GMCH
Reference Plane
L2
Trace Length Limit - L1
Point-to-Point with parallel termination
Escape
Inner Layer : 4 mils
Max =500 mils (Breakout)
(CLK-1.0") </= CM D </= (CLK+1.0")
Inner Layer : 12 mils
Max =50 mils (Escape)
Outer Layer : 15 mils
Stub Length S1-Stub from via to SO-DIMM
56 +/- 5%
S1
Minimum Spacing to Other DDR2
L0
Max. breakout length is 500 m ils
Outer Layer : 5mils spacing allowed
MB Length Limits - L0 +L1 +L2 +S1 -
From GMCH ball to SO-DIMM pad
Inner Layer : 4mils spacing allowe dBreakout Exceptions (R educe geometries
for GMCHbreak-out region)
Commandgroup:
SA_MA[13..0],SB_MA[13..0],SA_BS[2..0],SB_BS[2..0],SA_RAS#,
SB_RAS#,SA_CAS#,SB_CAS#,SA_WE#,SB_WE#
4/6,5/10
GMCH
Data group: SA_DQ[63..0],SB_DQ[63..0],SA_DM[7..0],SB_DM[7..0]
Reference Plane
Outer Layer : 5mils spacing allowed
L1
Minimum DQ Bus Trace Spacing
L2
Inner Layer : 6 mils
Max = 5000 mils
Min = 500 mils
Package Length P1
Breakout Exceptions (R educe geometries
for GMCHbreak-out region)
Minimum Isolation Spacing to non-DDR2
DQ/DM to DQS Length Matching
(Total Length including
package)
Max = 4500 mils
750 mils +/- 350 mils
4/4
Escape
25 mils
S1
Trace Length Limit - L0
Stub Length S1-Stubfrom via to SO-DIMM
Ground
P1 L0
MB Length Limits - L0 +L1 +L2 +S1 -
From GMCH ball to SO-DIMM pad
2
Outer Layer : 5 mils
SO-DIMM
Topology
Maximim Via Count
Breakout
Minimum Spacing to Other DDR2
Nominal Trace Width
Outer Layer : 8 mils
Trace Length L3
Max =500 mils (Breakout)
Outer Layer : 15 mils
Max =200 mils (Breakin)
Inner Layer : 12 mils
4/6
Total Length - P1 +L0 +L1 +L2 +S1 -
From GMCH die to SO-DIMM pad Max = 1500 mils
Point-to-Point
Max. breakout length is 500 mi ls
Max =50 mils (Escape)
Match DQ/DM to [SDQS - 200mils]
+/- 20mils, per byte lane
55 +/- 15%
Inner Layer : 4 mils
Trace Length Limit - L1
Characteristic Trace Impedance
Inner Layer : 4mils spacing allowed
Minimum Serpentine Spacing Same as DQ-to-DQ r outing
S1
Breakout Exceptions (R educe geometries
for GMCHbreak-out region)
Minimum Spacing to Other DDR2
P1
Match total length to within 5mils
Max =50 mils (Escape)
Differential Pair Point-to-Point
Max = 5000 mils
Max. breakin length is 2 00 mils
DQS to DQS# Length Matching
Trace Length Limit - L0
L2
Clock to Clock Length Match
(Total Length include package)
2 (Per side)
Ground
Min = 500 mils
DQS to DQS# spacing rule
waived at connector spacing of
10 mils to other DDR2
Outer Layer : 10 mils
SingleEnded Trace Impedance
Breakout
Max =200 mils (Breakin)
55 +/- 15%
Outer Layer : 5 mils
25 mils
Breakin
P1
Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region)
750 mils +/- 350 mils
5/5/10
Data Strobe group: SA_DQS[7..0],SA_DQS[7..0]#,SB_DQS[7..0],SB_DQS[7..0]#
Escape
Stub Length S1-Stubfrom via to SO-DIMM
Differential Mode Impedance
L2
Max = 4500 mils
Inner Layer : 4 mils
SO-DIMM
Inner Layer : 8 mils
85 +/- 20%
Minimum Isolation Spacing to non-DDR2
GMCH
PackageLength Range- P1
4/4/12
Reference Plane
L1
S1
Inner Layer : 4 mils
Outer Layer : 15 mils
Max =500 mils (Breakout)
Nominal Trace Width
Nominal DQS to DQS# Spacing
(edge to edge)
Topology
Max. breakout length is 500 mi ls
Minimum Serpentine Spacing
L1
4/4/8
Inner Layer : 8mils to other DDR2
Inner Layer : 12 mils
L0
Trace Length Limit - L1
Maximim Via Count
Outer Layer : 5 mils
L0
Outer Layer : 10 mils to other DDR2
Outer Layer : 15 mils
Inner Layer : 12 milsMinimum DQS to DQ Spacin g
MB Length Limits - L0 +L1 +L2 +S1 -
From GMCH ball to SO-DIMM pad
Total Length - P1 +L0 +L1 +L2 +S1 -
From GMCH die to SO-DIMM pad
(CLK-0.5") </= D QS </= (CLK+1.0")
Feedback group:
SA_RCVENIN#],SA_RCVENOUT#,SB_RCVENIN#],SB_RCVENOUT#
These signals are routed internally on the GMCH package and don't require an y
routing on the MB. As a result, can be leftas NC.
SL SL MS
MS SLSL MS
SL/MSMS SL MS
SL/MS
SL/MS
SL MS MS SL/MS
SLMS SL MS
4/4
DDRII Layout Guideline
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2) 8751-8751
C
449Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Tsft_star_vcc(3ms max)
GMCHPWRGD
Tcpu_up
Tboot
Vccgmch
Vid
Vcc-core
Tvccp_up
VID
Vccp
CLK_ENABLE#
Tgmch_pwrgd
Vccp_UP
IMVP6 Power On Sequencing Timing Diagram
Tboot-vid-tr(100uS max)
Tcpu_pwrgd(3~20mS)
IMVP4_PWRGD
CPU_UP
Vboot
VR_ON
PSUSC0
VDDM,VDDS
To ODEM and ICH4
PM_PWROK
From ODEM to CPU
AGTL+_CPURST0
PMU5V/PMU3V
BATTERY ONLY POWER ON TIMING
DCON
To ICH4
VDDA
CPU_PWRGD
To clock generator
VCCP/1.2VDDM
To ICH4
VR_ON
VCORE_CPU
From ICH4
PM_SLP_S30/S40/S50
SYS_PWROK
CK408_PWRGD0
From ICH4 to CPU
To ODEM/other PCI device
SUSTAT_B0
PCI_RST0
VCORE_ON
From ASIC_B0
From ASIC_B0
PM_RSTRST0
MAINSW0_ICH
POWSW0
PM_VGATE
VRON_VCCP
H
From ASIC_B0
CPU_PWRGOOD
VR_ON
CK408_PWRGD0
PM_VGATE
DCON
H
S3 SUSPEND AND RESUME TIMING
H
VCCP,1.2VDDM
SYS_PWROK
From ASIC_B0
H
To ICH4_M
H
From ICH4_M
1.5VDDS AND
H
PM_PWROK
SUSTAT_B0
VCORE_CPU
Generator
VDDM
PMU5V/PMU3V
PM_SLP_S40/S50
VRON_VCCP
PM_RSMRST0
H
DDR_PWRGD
To ODEM/other
PCI device
PCI_RST0
VDDA
From ODEM to CPU
To clock
VDDS
PSUSC0
ToICH4 and ODEM
From ICH4_M
VCORE_ON
PM_SLP_S30
POWSW0
From ICH4 to CPU
AGTL+_CPURST0
7. power on& off & S3 Sequence :
Tboot:10-100uS
-12%
t
CPU_UP
-12%
Vccp_UP
t
t
BOOT
BOOT-VID-TR
t
-12%
t
MCH-PWRGD
t
CPU_PWRGD
PSI#
VID
VR_ON
V
CC-CORE
CCP
CC_MCH
CPU_UP
V
Vccp_UP
V
MCH_PWRGD
CLK_ENABLE#
IMVP6_PWRGD
20060117A - DATA FROM NO.16809
Power On Sequencing Timing Diag ram
SFT_START_VCC
t
t
SFT_START_VCC
Max = 3 ms
t
BOOT
Min = 10 us , Max = 100 us
BOOT-VID-TR
t
Max = 100 us
t
CPU_PWRGD
Min = 3 ms , Max = 20 ms
MCH-PWRGD
t
t
Vccp_UP
CPU_UP
t
Min = 10 us , Max = 30 us
Min = 10 us , Max = 30 us
Min = 10 us , Max = 30 us
Timing Diagram
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2) 8751-8751
C
549Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
6.Schematic modify Item and History :
Schematic Modify
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2) 8751-8751
C
649Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Transmission LineType Total TraceLength Normal Impedance Spacing (mils)
ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# ,HITM# ,LOCK# ,
RS[2..0]# , TRDY# ,RESET#.
Strip-line(Int. Layer)
Micro-strip(Ext. Layer) 1.0 ~ 6.5 inch 55+/-15% 5 & 10 mils
FSB Common Clock Signal Layout Guide :
Normal Impedance
0.5 ~ 5.5 inch
Width & Spacing (mils)
55+/-15%
4 & 8 mils
DATA#[63..0]
FSB Source Synchronous Data Signal Routing Topology#1 :
Signal Name
Strip-line
Total TraceLength
Signals Name
DSTBP0#,DSTBN0#
Strobes associated with thegroup Strobe-to-StrobeComplement Matching
DATA#[15..0] , DINV0#
Signals Matching
+/- 25 mils+/- 100 mils
DATA#[31..16] , DINV1# +/- 100 mils
+/- 100 mils
+/- 100 mils
+/- 25 mils
+/- 25 mils
+/- 25 mils
DATA#[47..32] , DINV2#
DATA#[63..48] , DINV3#
DSTBP1#,DSTBN1#
DSTBP2#,DSTBN2#
DSTBP3#,DSTBN3#
Strobes associated with thegroup
A#[16..3] , REQ#[4..0]
+/- 200 mils
ADSTB0#+/- 200 mils
Strobe to Assoc. Address Signal Matching
ADSTB1#A#[31..17]
+/- 200 mils
ADSTB#[1..0]
Signals MatchingSignals Name
Topology : PWRGOOD
CPU
L1 0.5" - 12" Strip-line
L1
Micro-strip
Transmission Line
0.5" - 12"
Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# ,STPCLK#
A#[32-39], APM#[0-1]:Leave escape routing on for future functionality
Zo=55ohm, 0.5" max for GTLREF, Space any other switch
signals away from GTLREF with a minimum of 25mils.
Should be connect to ICH8M and Crestline without T-ing(no stub)
Rout to TP via and place gnd via w/in 100mils
Comp0,2 connect with Zo=27.4ohm, make trace
length shorter than 0.5" and width is 18mils.
Comp1,3 connect with Zo=55ohm, make trace
length shorter than 0.5" and width is 5mils
XDP P/U & P/D
DINV#[3..0]
DSTBN#[3..0]
DSTBP#[3..0]
Transmission LineType
Strip-line
Strip-line
Strip-line
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
0.5 ~ 5.5 inch
55+/-15%
55+/-15%
55+/-15%
Data-to-Data,Strobe-to-strobe Strobe-to-Data
4 & 8 mils
4 & 8 mils
4 & 12 mils
4 & 12 mils
4 & 12 mils
4 & 12 mils
N/A
N/A
FSB Source Synchronous Data Length Variation and Strobe Matching Requirements :
FSB Source Synchronous Address Length Variation and Strobe Matching Requirements :
+/- 200 mils
*** No length matching requirements exist between ADSTB0# and ADSTB1#
55+/-15%Strip-line
55+/-15%
4 & 8 mils
FSB Source Synchronous Address Signal Routing :
Transmission LineType
4 & 8 mils
Signal Name
Strip-line
Total TraceLength Normal Impedance
0.5 ~ 6.5 inch
Width & Spacing (mils)
55+/-15%
Strip-line
Address#[31..3]
REQ#[4..0]
4 & 8 mils
0.5 ~ 6.5 inch
0.5 ~ 6.5 inch
0" - 3.0" Microstrip0.5" - 12"
L2
56 +/-5%
Rtt
Topology : FERR#
Stripline
VCCP L1
0.5" - 12"L1
ICH8MCPU Rtt Transmission Line
0" - 3.0"
56 +/-5%
L2
ICH8M
Strip-line
L1 0.5" - 12"
Transmission Line
0.5" - 12" Micro-strip
L1CPU ICH8M
L4
VCCP
Rtt CPU IMVP6
VCCP
Rtt
L2+L1 L3 Strip-line
Rtt Transmission LineL2L1
Micro-strip75 +/-5%0.5" - 6.5"
75 +/-5%0.5" - 6.5"
0.5" - 6.5"
0.5" - 6.5"
0" - 3.0"
0" - 3.0"
0" - 3.0"
0" - 3.0"
L3 L4
Rtt
VCCP
Topology : THERMTRIP#
GMCH
L2
CPU ICH7m
RttL1 L4
L3
Rtt
56 +/-5%
L1 L2
1" - 6" 0" - 3.0"
Strip-line0" - 3.0"
0" - 3.0"
Transmission LineL4
Micro-strip
L3
0" - 3.0"
1" - 12"
1" - 12" 1" - 6"
L1+L3
1" - 12"
1" - 12"
Rss
24 +/-5%
24 +/-5% 56 +/-5%
Micro-strip
Strip-line
L1
Strip-line
Transmission LineCPU
Topology : CPUSLP#
0.5" - 12"
1" - 6"
Transmission Line
0.5" - 12"
Topology : RESET#
Micro-strip
L1CPU
L1
L1
GMCH
GMCH
1" - 6"
Don't allow the GTLREF routing to create splits or
discontinuities in the reference planes of the FSB
signals
H_PWRGD rise time :
Max : 15ns
Processor ITP Signal Default Strapping When ITP-XDP &
ITP700FLEX Dedbug Port Not Used.
TDI
TMS
TRST#
TCK
TDO
54.9 OHM +/-5%
OPEN
VCCP
VCCP
GND
GND
NC
Within 2.0" of theCPU
Within 2.0" of theCPU
Within 2.0" of theCPU
Within 2.0" of theCPU
N/A
Signal Resistor Value Connect To Resistor Placement
54.9 OHM +/-5%
649 OHM +/-5%
54.9 OHM +/-5%
Place C181 close tothe CPU_TEST4 pin.
Make sure CPU_TEST4 routing is reference toGND
and away from other nossy signale.
VCCP=1.05VDDM
0'' ~ 3''
Confidential
For D.C 2K
For Q.C 1.74K
Don't allow the GTLREF routing to create splits or
discontinuities in the reference planes of the FSB
signals
Zo=55ohm, 0.5" max for GTLREF, Space any other switch
signals away from GTLREF with a minimum of 25mils.
For Q.C CPU
For Q.C CPU
For D.C 56
For Q.C 50
R26,AA1 For D.C 27.4 For Q.C 25.9
U26,Y1 For D.C 54.9 For Q.C 50
For Q.C 51
EMI
EMI
MeromProcessor (1/2)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
C
749Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.
H_A#[35..3]
XDP_TRST#
XDP_DBRESET#
H_D#32
H_D#33
H_D#34
H_D#36
H_D#35
H_D#38
H_D#40
H_D#39
H_D#37
H_D#46
H_D#42
H_D#44
H_D#47
H_D#43
H_D#45
H_D#41
H_D#57
H_D#53
H_D#49
H_D#56
H_D#51
H_D#63
H_D#54
H_D#50
H_D#52
H_D#61
H_D#62
H_D#58
H_D#55
H_D#59
H_D#48
H_D#60
H_D#23
H_D#31
H_D#1
H_D#10
H_D#13
H_D#21
H_D#22
H_D#[63..0]
H_D#18
H_D#30
H_D#4
H_D#19
H_D#26
H_D#27
H_D#0
H_D#5
H_D#[63..0]
H_D#7
H_D#11
H_D#14
H_D#15
H_D#17
H_D#8
H_D#25
H_D#2
H_D#24
H_D#28
H_D#6
H_D#9
H_D#12
H_D#20
H_D#[63..0]
H_D#3
H_D#16
H_D#29
H_D#[63..0]
COMP2
XDP_TCK
XDP_TDI
XDP_TMS
XDP_BPM#5
H_GTLREF COMP1
COMP3
1.05VDDM
TEST3
TEST5
COMP0
H_REQ#3
H_A#9
H_A#5
H_A#25
XDP_TMS
XDP_DBRESET#
H_A#8
H_A#6
H_A#19
H_A#14
H_A#12
H_A#11
H_A#35
H_REQ#2
H_A#20
H_A#4
H_A#30
H_A#27
H_A#18
H_A#13
H_A#10
H_A#34
H_REQ#4
H_REQ#1
XDP_BPM#5
H_A#17
H_A#16
XDP_TRST#
XDP_TDIH_A#26 XDP_TCK
H_REQ#0
H_A#33
H_A#32
H_A#7
H_A#31
H_A#3
H_A#24
H_A#23
H_A#22
H_IERR#
H_A#28
H_A#21
H_A#[35..3]
H_A#29
H_A#15
H_REQ#[4..0]
3VDDM
H_QCBPM2
H_QCBPM0
H_QCBPM1
H_BPM1
H_BPM3
H_BPM2
H_BPM0
H_GTLREF2
TDO_M
TDI_M
3VDDM(9,11,14,16,17,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,43,45,46,47)
1.05VDDM(8,10,11,13,14,18,20,22,45)
H_A#[35..3](10)
H_A#[35..3](10)
H_ADSTB#0(10)
H_ADSTB#1(10)
H_REQ#[4..0](10)
H_D#[63..0](10)
H_D#[63..0](10)
H_DSTBN#0(10) H_DSTBP#0(10) H_DINV#0(10)
H_DSTBN#1(10)
H_DINV#1(10) H_DSTBP#1(10)
H_D#[63..0] (10)
H_D#[63..0] (10)
H_DSTBN#2 (10)
H_DINV#2 (10)
H_DSTBP#2 (10)
H_DSTBN#3 (10)
H_DINV#3 (10)
H_DSTBP#3 (10)
H_BNR# (10)
H_DBSY# (10)
H_LOCK# (10)
H_DRDY# (10)
H_HITM# (10)
H_HIT# (10)
H_ADS# (10)
H_BREQ# (10)
H_PROCHOT# (47)
H_A20M#(20)
H_IGNNE#(20)
H_STPCLK#(20) H_INTR(20) H_NMI(20) H_SMI#(20)
H_CPUSLP# (10) H_PWRGD (20)
H_DPWR# (10)
H_DPRSTP# (11,20,47)
H_DPSLP# (20)
H_CPURST# (10)
H_RS#2 (10)
H_RS#1 (10)
H_INIT# (20)
H_RS#0 (10)
H_BPRI# (10)
H_TRDY# (10)
H_DEFER# (10)
CLK_CPU_BCLK (18)
CLK_CPU_BCLK# (18)
H_THERMDA (9)
H_FERR#(20)
CPU_BSEL0(18) CPU_BSEL1(18) PSI# (47)CPU_BSEL2(18)
PM_THRMTRIP# (11,20)
H_THERMDC (9) HOT_DOWN# (9,37)
H_QCTHERMDA(9) H_QCTHERMDC(9)
1.05VDDM
1.05VDDM
1.05VDDM
1.05VDDM
3VDDM
1.05VDDM
1.05VDDM
1.05VDDM
1.05VDDM
C167
1000pF 25V+80-20%SMT0603 Y5V LR(NU)
R228 54.9 1%1/16W SMT0402 LR Sn
R290 1K 1%1/16W SMT0402 LR
R278
1.74K 1%1/10W SMT0603 LR(NU)
R213 51 5%1/16W SMT0402 LR(NU)
R286 0 5%1/16W SMT0402 LR(NU)
R218 54.9 1%1/16W SMT0402 LR Sn
C172
1000pF 25V+80-20%SMT0603 Y5V LR(NU)
R214 51 5%1/16W SMT0402 LR(NU)
R287
68 5%1/16W SMT0402 TIN LR
R566
100 1%1/16W SMT0402 LR(NU)
R24151 5%1/16W SMT0402 LR(NU)
R285 54.9 1%1/16W SMT0402 LR Sn
R234
51 5%1/16W SMT0402 LR(NU)
R294 1K 5%1/16W SMT0402 LR(NU)
R217 54.9 1%1/16W SMT0402 LR Sn
R215 51 5%1/16W SMT0402 LR(NU)
R24551 5%1/16W SMT0402 LR(NU)
R289 1K 5%1/16W SMT0402 LR(NU)
R275 1K 5%1/16W SMT0402 LR(NU)
R291 27.4 1%SMT0402 LR
R280 1K 1%1/16W SMT0402 LR(NU)
R222 54.9 1%1/16W SMT0402 LR Sn
R219 54.9 1%1/16W SMT0402 LR Sn
R22751 5%1/16W SMT0402 LR(NU)
R233 54.9 1%1/16W SMT0402 LR Sn
RP17
05%SMT1010 1/16W 4P2R LR(NU)
1 24
3
ADDR GROUP 0ADDR GROUP
1
CONTROL
XDP/ITP SIGNALS
H CLK
THERMAL
RESERVED
ICH
U30A
Penryn Ball-out Rev 1a
N3
P5
P2
L2
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
J4
U2
V4
M4
N5
T2
V3
B2
C3
D2
D22
L5
L4
K5
M3
N2
J1
A6
H1
M1
V1
D3
A22
A21
E2
AD4
AD3
AD1
AC4
G5
F1
C20
E1
H5
F21
A5
G6
E4
D20
C4
B3
C6
B4
H4
AC2
AC1
D21
K3
H2
K2
J3
L1
C1
F3
F4
G3
A3
D5
AC5
AA6
AB3
C7
A24
B25
AB5
G2
AB6
W3
AA4
AB2
AA3
F6
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[3]#
A[30]#
A[31]#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A20M#
ADS#
ADSTB[0]#
ADSTB[1]#
RSVD[09]
BCLK[0]
BCLK[1]
BNR#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
BPRI#
BR0#
DBR#
DBSY#
DEFER#
DRDY#
FERR#
HIT#
HITM#
IERR#
IGNNE#
INIT#
LINT0
LINT1
LOCK#
PRDY#
PREQ#
PROCHOT#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
RESET#
RS[0]#
RS[1]#
RS[2]#
SMI#
STPCLK#
TCK
TDI
TDO
THERMTRIP#
THERMDA
THERMDC
TMS
TRDY#
TRST#
A[32]#
A[33]#
A[34]#
A[35]#
RSVD[10]
C242
0.1uF 10V10%0402 X5R LR(NU)
R221 27.4 1%SMT0402 LR
R288 56 5%1/16W SMT0402 LR
R284
2K 1%1/16W SMT0402 LR
12
DATA GRP 0 DATA GRP 1
DATA GRP 2DATA GRP 3
MISC
U30B
Penryn Ball-out Rev 1a
R26
U26
AA1
Y1
E22
F24
J24
J23
H22
F26
K22
H23
N22
K25
P26
R23
E26
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
G22
T25
N25
Y22
AB24
V24
V26
V23
T22
U25
U23
F23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
AE24
AD24
G25
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
E25
AC22
AD23
AF22
AC23
E23
K24
G24
AF1
H25
N24
U22
AC20
E5
B5
D24
J26
L26
Y26
AE25
H26
M26
AA26
AF24
AD26
AE6
D6
D7
C24
B22
B23
C21
D25
AF26
A26
C23 COMP[0]
COMP[1]
COMP[2]
COMP[3]
D[0]#
D[1]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
D[16]#
D[17]#
D[18]#
D[19]#
D[2]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[3]#
D[30]#
D[31]#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[4]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[5]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[6]#
D[60]#
D[61]#
D[62]#
D[63]#
D[7]#
D[8]#
D[9]#
TEST5
DINV[0]#
DINV[1]#
DINV[2]#
DINV[3]#
DPRSTP#
DPSLP#
DPWR#
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
DSTBP[0]#
DSTBP[1]#
DSTBP[2]#
DSTBP[3]#
GTLREF
PSI#
PWRGOOD
SLP#
TEST3
BSEL[0]
BSEL[1]
BSEL[2]
TEST2
TEST4
TEST6
TEST1
R216 51 5%1/16W SMT0402 LR(NU)

A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Place theseinside socket cavity on L8
(North side secondary)
Place C?
Close To pin
B26
Route VCCSENSE and VSSSENSE traces
at 27.4 ohms with 50milspacing.
Place PU and PD within 1 inch of CPU
ICCA=130mA, 20mils
HFM
ICC=41A
ICCP=4.5A,180mils
TDK
Place theseinside socket cavity on L1
(South sidePrimary)
Place theseinside socket cavity on L8
(North side secondary)
Place theseinside socket cavity on L1
(North side Primary)
Place these inside socket cavity on
L8 (South side secondary)
South side secondary
North side secondary
Confidential
For Q.C NU
For D.C ON
For D.C
For D.C 0
For Q.C 1.21K
For Q.C ON
Merom Processor (2/2)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
C
8 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
FirstInternational Computer, Inc.
1.5VDDM
VCORE_CPU
1.05VDDM
GTREF_CONT
H_QCBPM3
BR1#
1.05VDDM(7,10,11,13,14,18,20,22,45)
1.5VDDM(13,14,19,20,22,29,31,44)
VCORE_CPU(47)
H_VID0 (47)
H_VID1 (47)
H_VID3 (47)
H_VID2 (47)
H_VID5 (47)
H_VID4 (47)
H_VID6 (47)
VCCSENSE (47)
VSSSENSE (47)
1.05VDDM
1.5VDDM
VCORE_CPU
VCORE_CPU
1.5VDDM
R251
05% 1/16WSMT0402 LR
C221 0.1uF 16V ±10% SMD0603 X7R LR
R244
05% 1/16WSMT0402 LR
C519 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
R262
51 5% 1/16WSMT0402 LR(NU)
C213 0.1uF 16V ±10% SMD0603 X7R LR
C189 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C227 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR C198 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
R260
05% 1/16WSMT0402 LR
C252 0.1uF 16V ±10% SMD0603 X7R LR
C525 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
R242
05% 1/16WSMT0402 LR
C520 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C513 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU) C498 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C224 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
U30D
Penryn Ball-out Rev 1a
P6
AE11
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3 A25
AF21
AF19
AF16
AF13
AF11
AF8
AF6
A2
AE26
AE23
AE19
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
Y6
A4
AE14
AE16
AE8
AF25
VSS[082]
VSS[148]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081] VSS[162]
VSS[161]
VSS[160]
VSS[159]
VSS[158]
VSS[157]
VSS[156]
VSS[155]
VSS[154]
VSS[153]
VSS[152]
VSS[151]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[106]
VSS[001]
VSS[149]
VSS[150]
VSS[147]
VSS[163]
C514 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR C180 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
R253
05% 1/16WSMT0402 LR
C225 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C511 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
R255
05% 1/16WSMT0402 LR
U30C
Penryn Ball-out Rev 1a
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
B26
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
AF7
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AE7
C26
G21
V6
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCA[01]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCSENSE
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VSSSENSE
VCCA[02]
VCCP[01]
VCCP[02]
C524 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU) C201 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C247 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
R246
05% 1/16WSMT0402 LR
C181 0.1uF 16V ±10% SMD0603 X7R LR
C184 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C196 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR C179 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C215 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU) C523 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C503 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C202 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C246
0.01uF 16V 10% SMT0402 X7R LR
C200 0.1uF 16V ±10% SMD0603 X7R LR
C497 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C188 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU) C209 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C222 0.1uF 16V ±10% SMD0603 X7R LR
C502 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C197 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C510 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
+
C168
T100uF 2V ±20% ESR=18m SMT7343 EEFCD0D101ER PANASONIC LR
R256
100 1% 1/16WSMT0402 LR
R250
100 1% 1/16WSMT0402 LR R252
05% 1/16WSMT0402 LR
C496 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR
C185 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU) C216 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU) C210 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)

8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Confidential
10mil
10mil
Dual Core THERMAL SENSOR
20mil
10 mil
10 mil
GND
GND
THERMDA
10 mil
THERMDC
Minimum
10 mil
THERMDA
THERMDC
20mil
10 mil
GND
GND
10mil
10 mil
10 mil
10 mil
Quad Core THERMAL SENSOR
10mil
Minimum
Vo VsetVINVEN
30mil
GND
30mil
GNDGNDGND
V02
CPU Thermal
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
C
949Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.
5VDDM
3VDDA
3VDDM
SMCLK_PMU
HOT_DOWN#
THRM_VCC
SMDAT_PMU
TH_ALRT#
THRM_VCC
TH_ALRT#
HOT_DOWN#
SMDAT_PMU
H_QCTHERMDC
H_QCTHERMDA
SMCLK_PMU
3VDDA(18,19,20,21,22,23,24,26,28,29,31,32,33,37,41,43,44,45)
5VDDM(22,25,27,30,35,36,43,44,46,47)
3VDDM(7,11,14,16,17,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,43,45,46,47)
H_THERMDA (7)
HOT_DOWN# (7,37)
H_THERMDC (7)
SMDAT_PMU(37,41)
SMCLK_PMU(37,41)
H_QCTHERMDC (7)
H_QCTHERMDA (7)
FAN_PWM(37)
FAN_SPEED(37)
5VDDM
3VDDA
3VDDM
5VDDM
5VDDM
U15
LNR-IC Temperature Sensor G780-1P81U 3.0-5.5V MSOP-8 8PIN GMT LR(nu)
1
2
3
45
6
7
8VCC
D+
D-
THM#GND
ALRT#
SDATA
SCLK
C164
2200pF 50V10%SMT0402 X7R LR
R504
10K 5%1/16WSMT0402 LR
C674
2.2uF 10V±10%SMT0603X5R C1608X5R1A225KT TDKLR C675 2.2uF 10V±10%SMT0603X5R C1608X5R1A225KT TDKLR
R211
10K 5%1/16WSMT0402 LR
R203
100 5%1/16W SMT0402 LR(NU)
C166
2200pF 50V10%SMT0402 X7R LR(NU)
U39
LNR-IC FAN DRIVER 1.6XG990P11USOP-8 GMT LR
1 2 3 45
6 7 8VEN
VIN
VO
VSETGND
GND GND GND
C162
0.1uF 16V80-20%SMT0402Y5V LR(NU)
R202
100 5%1/16W SMT0402 LR
U14
LNR-IC Temperature Sensor G780P81U 3.0-5.5V MSOP-8 8PIN GMT LR
1
2
3
45
6
7
8VCC
D+
D-
THM#GND
ALRT#
SDATA
SCLK
C460
0.22uF 10V10%0603 X7R
12
R212
10K 5%1/16WSMT0402 LR
CN27
CON ACES SMT TYPE 85205-03001 WIRE1.25P3PIN LR DO'NT CARE
20-24197-20
1
2
3
4
5
C158
0.1uF 16V80-20%0402 Y5VLR

10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
Confidential
for D.C 100
for Q.C 75
10 mil wide / 20 mil spacing
for D.C 24.9
for Q.C 16.9
Crestline Host (1/6)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
C
10 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
FirstInternational Computer, Inc.
H_A#15
H_A#5
H_A#11
H_A#9
H_A#13
H_A#14
H_A#6
H_A#12
H_A#16
H_A#8
H_A#10
H_A#3
H_A#4
H_A#7
H_A#23
H_A#26
H_A#21
H_A#30
H_A#25
H_A#28
H_A#29
H_A#20
H_A#31
H_A#24
H_A#18
H_A#17
H_A#27
H_A#19
H_A#22
H_A#[35..3]
H_REQ#0
H_REQ#2
H_REQ#4
H_REQ#3
H_REQ#1
H_REQ#[4..0]
H_SWING
H_RCOMP
H_SWING
H_RCOMP
H_AVREF
H_DVREF
H_A#32
H_A#33
H_A#34
H_A#35
1.05VDDM
H_D#17
H_D#46
H_D#14
H_D#42
H_D#61
H_D#44
H_D#18
H_D#53
H_D#43
H_D#41
H_D#62
H_D#27
H_D#28
H_D#8
H_D#31
H_D#34
H_D#19
H_D#47
H_D#45
H_D#55
H_D#[63..0]
H_D#48
H_D#22
H_D#38
H_D#32
H_D#12
H_D#56
H_D#13
H_D#37
H_D#25
H_D#3
H_D#1
H_D#54
H_D#29
H_D#9
H_D#33
H_D#24
H_D#57
H_D#59
H_D#49
H_D#40
H_D#2
H_D#21
H_D#0
H_D#52
H_D#60
H_D#6
H_D#16
H_D#15
H_D#39
H_D#26
H_D#30
H_D#10
H_D#35
H_D#50
H_D#11
H_D#4
H_D#5
H_D#36
H_D#51
H_D#58
H_D#7
H_D#63
H_D#20
H_D#23
1.05VDDM(7,8,11,13,14,18,20,22,45)
H_ADSTB#0 (7)
H_DINV#3 (7)
H_DSTBP#1 (7)
H_BREQ# (7)
H_D#[63..0](7)
H_HITM# (7)
H_DSTBN#3 (7)
H_DINV#1 (7)
H_DBSY# (7)
H_DSTBP#2 (7)
H_HIT# (7)
H_DSTBN#1 (7)
H_DRDY# (7)
H_DINV#2 (7)
H_DINV#0 (7)
H_DSTBN#2 (7)
H_REQ#[4..0] (7)
H_DSTBP#0 (7)
H_DSTBN#0 (7)
H_ADS# (7)
H_ADSTB#1 (7)
H_A#[35..3] (7)
H_BNR# (7)
H_DSTBP#3 (7)
H_DPWR# (7)
CLK_MCH_BCLK (18)
CLK_MCH_BCLK# (18)
H_LOCK# (7)
H_BPRI# (7)
H_CPURST#(7)
H_DEFER# (7)
H_RS#0 (7)
H_RS#1 (7)
H_RS#2 (7)
H_CPUSLP#(7)
H_TRDY# (7)
1.05VDDM
1.05VDDM
R558
RES 24.9 1% 1/16WSMT0402 LR
HOST
U31A
CANTIGA_1p0
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
A14
B18
K17
C15
F16
H13
C18
M16
J13
H12
B16
G17
A9
F11
G12
AH6
C12
AH7
F2
F13
B13
G8
M9
L6
N10
AA8
AA2
AE11
D4
H3
B10
M11
J1
J2
N12
J6
P2
L2
R2
N9
F8
M5
J3
N2
R1
N5
N6
P13
N8
L7
E6
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
G2
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
H6
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
H2
AE8
AG2
AD6
F6
E9
J8
L3
Y13
Y1
J11
F9
L10
M7
AA5
AE6
L9
M8
AA6
AE5
A11
B11
C9
H9
E12
H11
B15
K13
B14
B20
F21
K21
L20
C5
E11
E3
B6
F12
C8
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_3
H_A#_30
H_A#_31
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
HPLL_CLK#
H_CPURST#
HPLL_CLK
H_D#_0
H_REQ#_2
H_REQ#_3
H_D#_1
H_D#_10
H_D#_20
H_D#_30
H_D#_40
H_D#_50
H_D#_60
H_D#_8
H_D#_9
H_DBSY#
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_2
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_3
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_4
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_5
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_6
H_D#_61
H_D#_62
H_D#_63
H_D#_7
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DRDY#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_AVREF
H_DVREF
H_TRDY#
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_4
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_SWING
H_CPUSLP#
H_RCOMP
H_RS#_0
H_RS#_1
H_RS#_2
R553
SPWR 0 5% 1/16W0402
R551
RES 221 1% 1/16WSMT0402 RR0510S-2210-FN CYNTEC LR
C490
0.1uF 10V10% 0402 X5R LR(NU)
R552
100 1% 1/16WSMT0402 LR
R550
1K 1% 1/16WSMT0402 LR
C486
0.1uF 10V10% 0402 X5R LR
R549
2K 1% 1/16WSMT0402 LR
12
C177
0.1uF 10V10% 0402 X5R LR(NU)

10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
20miles
0 = Dynamic ODT Disabled
1 = DMI * 4 ( Default )
CFG19
CFG [12:13]
CFG [2:0]
1 = SDVO or PCIE X1 are operatingsimulaneously via the PEG port.
00 = Clock Gating Disable
000=FSB1066
11 = Normal Operation ( Default )
CFG20
CFG5
0 = Only SDVO or PCIE X1 is operationl ( default )
010=FSB800
CFG9
10 = All Z Mode Enable
CFG16
01 = XOR Mode Enabled
0 = DMI * 2
GMCH Strapping Requirements
0 = Lane Reverse 1 = DMI Lane Reversal Enabled ( Default )
1 = Normal Operation ( Default )
Confidential
(DMI lane)
0 = Normal ( Default )
1 = Lanes Reversed
(PCIE)
0.35V
011=FSB667
CFG6 0 = ITPM is enabled
1 = ITPM is disabled ( Default )
CFG7
CFG10
0 = Isolators are bypassed
1= Isolators are active (Default)
1= PCIE loopback disable(Default)
0 = PCIE loopback enable
For checklist v1.2
For checklist v1.2
Install it if GMCH
disable.
Crestline DMI/Graphic (2/6)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
C
11 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
FirstInternational Computer, Inc.
PM_EXTTS#0
MCH_CFG_19
PM_EXTTS#1
SM_RCOMP_VOH
MCH_CFG_16
RST_IN#_MCH
MCH_CFG_13
SM_RCOMP_VOL
MCH_CFG_9
MCH_CFG_12
SM_RCOMP_VOH
SM_RCOMP_VOL
MCH_CFG_5
MCH_CFG_20
CLK_MCH_OE#
PEG_COMP
MCH_CFG_19
SM_RCOMP#
SM_RCOMP
3VDDM
1.8VDDS
M_VREF
TV_DCONSEL1
TV_DCONSEL0
DMI_TXP3
DMI_TXP2
DMI_TXP1
DMI_TXP0
DMI_TXN3
DMI_TXN1
DMI_TXN0
DMI_RXP1
DMI_RXP2
DMI_RXP0
DMI_RXP3
DMI_RXN3
DMI_RXN2
DMI_RXN1
DMI_RXN0
CLK_MCH_OE#
1.05VDDM_PEG
DFGT_VID_2
DFGT_VID_3
DFGT_VID_0
DFGT_VID_1
SM_DRAMRST#
DMI_TXN2
CL_REFCL_REF
DFGT_VID_4
1.05VDDM
MCH_CFG_6
SDVO_CTRL_DATA
SDVO_CTRL_CLK
TV_DCONSEL1
TV_DCONSEL0
MCH_CFG_20
PM_EXTTS#0
PM_EXTTS#1
MCH_CFG_12
TV_DCONSEL1
MCH_CFG_6
MCH_CFG_20
TV_DCONSEL0
MCH_CFG_16
MCH_CFG_9
MCH_CFG_5
MCH_CFG_13
1.8VDDS(13,14,16,17,45)
3VDDM(7,9,14,16,17,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,43,45,46,47)
M_VREF(16,17,45)
1.05VDDM_PEG(14)
1.05VDDM(7,8,10,13,14,18,20,22,45)
LVDS_DDC_CLKU(24)LVDS_DDC_DATAU(24)
LVDS_TXOUT_L1PU(24)
LVDS_TXOUT_L1NU(24)
LVDS_TXOUT_L0PU(24)
LVDS_TXCLK_LPU(24)
LVDS_TXOUT_L2PU(24)
LVDS_TXOUT_L0NU(24)
LVDS_TXOUT_L2NU(24)
LVDS_TXCLK_LNU(24)
Q_VEDATU(25) Q_VECLKU(25)
MCH_BSEL0(18)
MCH_BSEL2(18)
CL_DATA0 (21)
CL_CLK0 (21)
CL_RST#0 (21)
MCH_BSEL1(18)
DREFSSCLK# (18)
DREFSSCLK (18)
DREFCLK (18)
DREFCLK# (18)
H_DPRSTP#(7,20,47)
CLK_PCIE_3GPLL (18)
PM_DPRSLPVR(21,46,47)
PLT_RST#(19)
CLK_PCIE_3GPLL# (18)
PM_EXTTS#1(17)
DELAY_VR_PWRGOOD(23,47)
PM_EXTTS#0(16)
MPWROK (21,23,37)
DMI_TXP1 (19)
DMI_TXP2 (19)
DMI_TXP0 (19)
DMI_TXP3 (19)
DMI_TXN1 (19)
DMI_TXN3 (19)
DMI_TXN2 (19)
DMI_TXN0 (19)
SM_PWROK
LCD_BRIGHTNESS(24,37) LVDS_ENABKL(37)
LVDS_ENALCDU(24)
TV_YU
TV_CU
REDU(25)
BLUEU(25)
GREENU(25)
HSYNCU(25) VSYNCU(25)
M_CLK_DDR#1 (16)
M_CLK_DDR#0 (16)
M_CS#1 (16)
M_CS#3 (17)
M_CLK_DDR#4 (17)
M_ODT2 (17)
M_ODT0 (16)
M_CS#2 (17)
M_CLK_DDR#3 (17)
M_CKE3 (17)
M_ODT3 (17)
M_ODT1 (16)
M_CKE4 (17)
M_CLK_DDR1 (16)
MCH_ICH_SYNC# (21)
M_CS#0 (16)
M_CLK_DDR4 (17)
CLK_MCH_OE# (18)
PM_BMBUSY#(21)
M_CKE0 (16)
M_CKE1 (16)
M_CLK_DDR3 (17)
M_CLK_DDR0 (16)
PM_THRMTRIP#(7,20)
DMI_RXP3 (19)
DMI_RXP0 (19)
DMI_RXP2 (19)
DMI_RXP1 (19)
DMI_RXN2 (19)
DMI_RXN0 (19)
DMI_RXN3 (19)
DMI_RXN1 (19)
DFGT_VID_3 (46)
DFGT_VID_2 (46)
DFGT_VID_0 (46)
DFGT_VID_1 (46)
DFGT_VR_EN (46)
DFGT_VID_4 (46)
MCH_TSATN
1.8VDDS
1.05VDDM
3VDDM
3VDDM
1.05VDDM_PEG
1.8VDDS
1.05VDDM
3VDDM
1.8VDDS
M_VREF
R226 10K 5% 1/16WSMT0402 LR
R248
1K 1% 1/16WSMT0402 LR
T11
1
RP57
RP2.2K 5% SMT1010 4P2R 1/16WLR(NU)
R265 75 1% 1/16WSMT0402 LR
R266 0 5% 1/16WSMT0402 LR(NU)
RP40
10K 5% SMT1010 1/16W4P2R LR
1
24 3
R300
1K 1% 1/16WSMT0402 LR
R270 RES 2.2K 1% 1/16WSMT0402 LR
R271
RES 49.9 1% 1/16WSMT0402
R259 75 1% 1/16WSMT0402 LR
RP58
05% SMT1010 1/16W4P2R LR
1
24 3
R283 10K 1% 1/16WSMT0402 LR(NU)
R298 0 5% 1/16WSMT0402 LR
R296
3.01K 1% 1/10W0603 LR
R279
1K 1% 1/16WSMT0402 LR
C228
0.1uF 10V10% 0402 X5R LR
T13 1
R263 RES 150 1% 1/16WSMT0402 LR
R543
10K 5% 1/16WSMT0402 LR
R235 RES 2.2K 1% 1/16WSMT0402 LR(NU)
R247 RES 150 1% 1/16WSMT0402 LR
R236 RES 2.2K 1% 1/16WSMT0402 LR(NU)
R243 0 5% 1/16WSMT0402 LR
PM
MISC
NC
DDR CLK/ CONTROL/COMPENSATIONCLK
DMI
CFG
RSVD
GRAPHICS VIDMEHDA
U31B
CANTIGA_1p0
AP24
AT21
AV24
AR24
AR21
AU24
BC28
AY28
AY36
BB36
BA17
AY16
AV16
AR13
BC36
BD17
AY17
BF15
AY13
BG22
BH21
P29
R28
P25
T25
R25
T28
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
R29
N33
P32
AT40
AT11
B38
A38
E41
F41
AE41
AE37
AE47
AH39
AE40
AE38
AE48
AH40
AE35
AE43
AE46
AH42
AD35
AE44
AF46
AH43
AL34
AN35
AK34
AM35
BG23
BF23
BH18
BF18
B7
AU20
AV20
AY21
AH9
AH10
AH12
AH13
M36
N36
R33
T33
B33
B32
G33
F33
C34
BF28
BH28
T20
R32
K12
AH37
AH36
AN36
AJ35
AH34
A47
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
G36
E36
K36
T24
H36
B12
E43
F43
BH3
E33
B31
N28
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
AV42
AR36
BF17
M1
B28
B30
B29
C29
A28
M28
B2
SA_CK_0
SA_CK_1
SB_CK_0
SA_CK#_0
SA_CK#_1
SB_CK#_0
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SM_DRAMRST#
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
CFG_18
CFG_19
CFG_2
CFG_0
CFG_1
CFG_20
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
PM_SYNC#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
RSVD10
RSVD12
RSVD11
RSVD13
RSVD22
RSVD23
RSVD24
RSVD25
PM_DPRSTP#
SB_CK_1
SB_CK#_1
RSVD20
RSVD5
RSVD6
RSVD7
RSVD8
RSVD1
RSVD2
RSVD3
RSVD4
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
SM_RCOMP_VOH
SM_RCOMP_VOL
THERMTRIP#
DPRSLPVR
RSVD9
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
NC_26
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
RSVD14
ICH_SYNC#
TSATN#
PEG_CLK#
PEG_CLK
NC_16
GFX_VID_4
RSVD15
DDPC_CTRLCLK
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
SM_VREF
SM_PWROK
SM_REXT
RSVD17
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
DDPC_CTRLDATA
RSVD16
R230 RES 2.2K 1% 1/16WSMT0402 LR(NU)
R299 10K 1% 1/16WSMT0402 LR(NU)
R257 RES 150 1% 1/16WSMT0402 LR
C255
2.2uF 6.3V 80-20% SMT0603 Y5V LR
LVDS
PCI-EXPRESS GRAPHICS
TV VGA
U31C
CANTIGA_1p0
T37
T36
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
J41
Y40
M40
M42
R48
N38
T40
U37
U40
M46
AA46
AA37
AA40
AD43
AC46
M47
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
M32
M33
K33
J33
M29
C44
B43
E37
E38
C41
C40
H47
E46
G40
D45
F40
B37
A37
A41
H38
G37
G38
F37
G32
F25
H25
K25
H24
E28
H32
J32
G28
J29
E29
J28
G29
L29
H48
B42
L32
C31
E32
A40
B40
J37
K37
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_10
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_1
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX#_2
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA_1
LVDSA_DATA_2
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA_1
LVDSB_DATA_2
L_BKLT_EN
TVA_DAC
TVB_DAC
TVC_DAC
TV_RTN
CRT_BLUE
CRT_DDC_CLK
CRT_DDC_DATA
CRT_GREEN
CRT_HSYNC
CRT_TVO_IREF
CRT_RED
CRT_IRTN
CRT_VSYNC
LVDSA_DATA_0
LVDSB_DATA_0
L_BKLT_CTRL
TV_DCONSEL_0
TV_DCONSEL_1
LVDSA_DATA#_3
LVDSA_DATA_3
LVDSB_DATA#_3
LVDSB_DATA_3
R542
10K 5% 1/16WSMT0402 LR
T14 1
R249 75 1% 1/16WSMT0402 LR
R223 4.02K 1% 1/10WSMT0603 LR(NU)
R282 10K 1% 1/16WSMT0402 LR
R239 56 5% 1/16WSMT0402 LR
R544
100 5% 1/16WSMT0402 LR
C253
0.01uF 16V 10% SMT0402 X7R LR
C251
0.01uF 16V 10% SMT0402 X7R LR
R548
100K 1% 1/16WSMT0402 LR(NU)
C248
2.2uF 6.3V 80-20% SMT0603 Y5V LR
R297 499 1% 1/16WSMT0402 LR
R220 4.02K 1% 1/10WSMT0603 LR
R240
RES 2.4K 1% 1/16WSMT0402 LR
T12
1
R237 RES 2.2K 1% 1/16WSMT0402 LR(NU)
R238 RES 2.2K 1% 1/16WSMT0402 LR(NU)
R295
1K 1% 1/16WSMT0402 LR
R261 100K 5% 1/16WSMT0402 LR
R277
499 1% 1/16WSMT0402 LR
R577 RES 80.6 1% 1/10WSMT 0603 LR
R576 RES 80.6 1% 1/10WSMT 0603 LR
R231 RES 2.2K 1% 1/16WSMT0402 LR(NU)

10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
Mini
DIN7
2. RGB signals should be routed on the same layer, have a similar number of bends,
same number of vias
0.5"
150ohm
1. The minimum spacing between each RGB is 40-mils while 50-mils is preferred
Zo=37.5
Filter
TV DAC
Zo=75
0.5"
4. TV DAC route lengths should be lenght match to within 200 mils
TVDAC RoutingGuideline
TV IRTN 150ohm
0.2"
3. All routing should be done with ground referencing as well
12"
Zo=50
GMCH
Confidential
Crestline DDR2 (3/6)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
C
12 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ6
M_A_DQ5
M_A_DQ7
M_A_DQ15
M_A_DQ14
M_A_DQ13
M_A_DQ8
M_A_DQ10
M_A_DQ9
M_A_DQ11
M_A_DQ12
M_A_DQ23
M_A_DQ22
M_A_DQ31
M_A_DQ21
M_A_DQ24
M_A_DQ16
M_A_DQ27
M_A_DQ18
M_A_DQ17
M_A_DQ19
M_A_DQ28
M_A_DQ30
M_A_DQ26
M_A_DQ20
M_A_DQ29
M_A_DQ25
M_A_DQ56
M_A_DQ39
M_A_DQ61
M_A_DQ53
M_A_DQ54
M_A_DQ38
M_A_DQ60
M_A_DQ57
M_A_DQ47
M_A_DQ63
M_A_DQ48
M_A_DQ37
M_A_DQ40
M_A_DQ58
M_A_DQ32
M_A_DQ49
M_A_DQ52
M_A_DQ50
M_A_DQ43
M_A_DQ34
M_A_DQ33
M_A_DQ62
M_A_DQ35
M_A_DQ44
M_A_DQ46
M_A_DQ42
M_A_DQ59
M_A_DQ36
M_A_DQ51
M_A_DQ45
M_A_DQ41
M_A_DQ55
M_A_DQ[63..0]
M_A_DM[7..0]
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ7
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ11
M_B_DQ13
M_B_DQ14
M_B_DQ8
M_B_DQ9
M_B_DQ12
M_B_DQ10
M_B_DQ15
M_B_DQ30
M_B_DQ27
M_B_DQ25
M_B_DQ29
M_B_DQ19
M_B_DQ28
M_B_DQ21
M_B_DQ22
M_B_DQ26
M_B_DQ16
M_B_DQ17
M_B_DQ20
M_B_DQ18
M_B_DQ31
M_B_DQ23
M_B_DQ24
M_B_DQ59
M_B_DQ50
M_B_DQ56
M_B_DQ63
M_B_DQ46
M_B_DQ48
M_B_DQ61
M_B_DQ43
M_B_DQ41
M_B_DQ45
M_B_DQ35
M_B_DQ54
M_B_DQ44
M_B_DQ53
M_B_DQ37
M_B_DQ38
M_B_DQ60
M_B_DQ42
M_B_DQ32
M_B_DQ33
M_B_DQ62
M_B_DQ52
M_B_DQ36
M_B_DQ58
M_B_DQ57
M_B_DQ34
M_B_DQ51
M_B_DQ47
M_B_DQ39
M_B_DQ55
M_B_DQ40
M_B_DQ49
M_A_A7
M_A_A4
M_A_A8M_A_A8
M_A_A[14..0]
M_A_A2M_A_A2
M_A_A11
M_A_A13
M_A_A5M_A_A5
M_A_A6M_A_A6
M_A_A0M_A_A0
M_A_A12
M_A_A1M_A_A1
M_A_A10
M_A_A9
M_A_A3
M_A_DQS#2M_A_DQS#2
M_A_DQS7M_A_DQS7
M_A_DQS1M_A_DQS1
M_A_DQS#5M_A_DQS#5
M_A_DQS#6M_A_DQS#6
M_A_DQS0M_A_DQS0
M_A_DQS2M_A_DQS2
M_A_DQS[7..0]
M_A_DQS#7M_A_DQS#7
M_A_DQS3M_A_DQS3
M_A_DQS6M_A_DQS6 M_A_DQS#[7..0]
M_A_DQS#0M_A_DQS#0
M_A_DQS4M_A_DQS4
M_A_DQS#1M_A_DQS#1
M_A_DQS#4M_A_DQS#4
M_A_DQS5
M_A_DQS#3M_A_DQS#3
M_A_DM0M_A_DM0
M_A_DM3M_A_DM3
M_A_DM4M_A_DM4
M_A_DM5M_A_DM5
M_A_DM2M_A_DM2
M_A_DM6M_A_DM6
M_A_DM7M_A_DM7
M_A_DM1M_A_DM1
M_A_A14 M_B_A13
M_B_A9
M_B_A2
M_B_A8
M_B_A1
M_B_A12
M_B_A0
M_B_A7
M_B_A11
M_B_A6
M_B_A4
M_B_A[14..0]
M_B_A10
M_B_A5
M_B_A3
M_B_A14
M_B_DQS#6
M_B_DQS3
M_B_DQS#1
M_B_DQS2
M_B_DQS#0
M_B_DQS#5
M_B_DQS6
M_B_DQS7
M_B_DQS1
M_B_DQS[7..0]
M_B_DQS#4
M_B_DQS5
M_B_DQS#[7..0]
M_B_DQS0
M_B_DQS#3
M_B_DQS#7
M_B_DQS4
M_B_DQS#2
M_B_DM6
M_B_DM2
M_B_DM1
M_B_DM0
M_B_DM5
M_B_DM4
M_B_DM[7..0]
M_B_DM7
M_B_DM3
M_A_DQ[63..0](16) M_B_DQ[63..0](17)
M_A_A[14..0] (16)
M_A_DQS#[7..0] (16)
M_A_DQS[7..0] (16)
M_B_A[14..0] (17)
M_B_DQS#[7..0] (17)
M_B_DQS[7..0] (17)
M_A_BS0 (16)
M_A_BS1 (16)
M_A_BS2 (16)
M_A_CAS# (16)
M_A_DM[7..0] (16)
M_A_RAS# (16)
M_A_WE# (16)
M_B_BS2 (17)
M_B_BS1 (17)
M_B_BS0 (17)
M_B_RAS# (17)
M_B_WE# (17)
M_B_CAS# (17)
M_B_DM[7..0] (17)
DDR SYSTEM MEMORY B
U31E
CANTIGA_1p0
AK47
AH46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
AP47
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
AP46
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
AJ46
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AJ48
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM48
AM2
AM3
AH3
AJ3
AP48
AU47
AU46
BC16
BB17
BB33
BG16
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BB16
AW33
AY33
BH15
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
AU33
AU17
BF14
SB_DQ_0
SB_DQ_1
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_2
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_3
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_4
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_5
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_6
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_BS_0
SB_BS_1
SB_BS_2
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_14
SB_RAS#
SB_WE#
DDR SYSTEM MEMORY A
U31D
CANTIGA_1p0
AJ38
AJ41
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AN38
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AM38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
AJ36
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AJ40
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AM44
AN12
AM13
AJ11
AJ12
AM42
AN43
AN44
BD21
BG18
AT25
BD20
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ5
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BC21
BG26
BH26
BH17
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BB20
AY20
AY25
SA_DQ_0
SA_DQ_1
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_2
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_3
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_4
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_5
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_6
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DM_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_RAS#
SA_WE#
SA_MA_14

10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
308mils
20mils
VIA=2400mA / 100mils
Confidential
10/2 MODIFY
VIA=7700mA / 320mils
EXT VGA VGA_VDD NEED PULL DOWN
Crestline Power (4/6)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
C
13 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
FirstInternational Computer, Inc.
VCCSM_LF7
VCCSM_LF6
VCCSM_LF5
VCCSM_LF4
VCCSM_LF3
VCCSM_LF2
VCCSM_LF1
1.8VDDS
1.05VDDM
1.5VDDM
VGA_VDD
1.05VDDM(7,8,10,11,14,18,20,22,45)
1.8VDDS(11,14,16,17,45)
1.5VDDM(8,14,19,20,22,29,31,44)
VGA_VDD(45,46)
VSS_AXG_SENSE(46) VCC_AXG_SENSE(46)
1.05VDDM
1.05VDDM
1.8VDDS
1.5VDDM
VGA_VDD
1.05VDDM
VGA_VDD
POWER
VCC NCTF
VCC CORE
U31F
CANTIGA_1p0
AM32
AC30
AJ29
AK25
AA32
Y32
W32
U32
AM30
AL30
AK30
AG30
AF30
AE30
AL32
W30
V30
AK32
AH29
AG29
AE29
AL28
AK28
AL26
AK26
AJ32
AK24
AH32
AG32
AE32
AC32
AC29
AA29
Y29
W29
V29
U30
AL29
AK29
AH30
AB30
AA30
Y30
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32
AK23
VCC_NCTF_1
VCC_NCTF_20
VCC_NCTF_29
VCC_NCTF_42
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_2
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_3
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_4
VCC_NCTF_43
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_16
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_NCTF_44
C219 0.1uF 16V ±10% SMD0603 X7R LR
+
C263 T100uF 2V ±20% ESR=18m SMT7343 EEFCD0D101ER PANASONIC LR C218 0.1uF 16V ±10% SMD0603 X7R LR
C243 0.22uF 10V0603 X7R LR
C549 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C250 1uF 10V+80-20% 0603 Y5VLR
C241 0.22uF 10V0603 X7R LR D13
DIODE SWITCHING 1SS355 80V100mA SOD-323 2PIN PSI LR
N P
C220 0.1uF 10V 10% 0402 X5R LR
C244 0.1uF 10V10% 0402 X5R LR
C231 0.22uF 10V 0603 X7R LR
C232 1uF 10V +80-20% 0603 Y5V LR(NU)
+
C254 220uF 2V ±20% 15m 7343 PANA LR(NU)
POWER
VCC SMVCC GFX
VCC GFX NCTF
VCC SM LF
U31G
CANTIGA_1p0
AY32
BF31
AW29
BD32
BC32
BB32
BA32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
AN33
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
BH32
AV29
AU29
AT29
AR29
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
V28
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
W26
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
V26
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
W25
AH16
AG16
AF16
AE16
AC16
AB16
AA16
V25
W24
V24
W23
AP29
BG32
BF32
W28AP33
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
AM15
AL15
AJ15
AH15
AF15
AB15
AV44
BA37
AM40
AV21
AY5
AM10
BB13
T16
AG15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
AJ14
AH14
Y16
W16
V16
U16
BA36
BB24
BD16
BB21
AW16
AW13
AT13
AE15
VCC_SM_10
VCC_SM_20
VCC_SM_30
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_2
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_3
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_2
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_3
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_4
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_5
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_SM_35
VCC_SM_4
VCC_SM_5
VCC_AXG_NCTF_1VCC_SM_1
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_27
VCC_AXG_28
VCC_AXG_30
VCC_AXG_31
VCC_AXG_33
VCC_AXG_34
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC_AXG_26
VCC_AXG_32
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
VCC_AXG_29
C551 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
+
C205 220uF 2V ±20% 15m 7343 PANA LR
C229 0.1uF 16V ±10% SMD0603 X7R LR C214 0.1uF 10V 10% 0402 X5R LR(NU)
C223 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
R130
RES 10 5% 1/16WSMT0402 LR
C199 0.22uF 10V 0603 X7R LR
C233 0.1uF 10V10% 0402 X5R LR
C234 0.1uF 10V 10% 0402 X5R LR(NU)
C249 1uF 10V+80-20% 0603 Y5VLR
R232
0 5% 1/4WSMT1206 LR
C237 0.47uF 10V ±10% SMD0603 X5R LR
1 2
C236 10uF 10V +80-20% SMT0805 Y5V LR(NU) C169 4.7uF 25V ±10% SMT1206 X5R CM316X5R475K25AT AVX/KYOCERA LR
C204 10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
C217 0.47uF 10V ±10% SMD0603 X5R LR
12
C546 0.1uF 10V 10% 0402 X5R LR

10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
VIA=100mA / 10mils
VIA=250mA / 10mils
VIA=80mA / 10mils
VIA=200mA / 10mils
VIA=5mA / 10mils
VIA=1200mA / 60mils
0.1uf caps in 1.5VDDM_xPLL
need to be located as edge caps
within 200mils
10mils
VIA=80mA / 10mils
VIA=150mA / 10mils
VIA=200mA / 20mils
VIA=100mA / 10mils
VIA=850mA / 40mils
20mils 20mils
(24mA)
Caps used in 2.5VDDM_CRTDAC
should be within 250mils of
edge
VIA=50mA / 10mils
VIA=350mA / 20mils
VIA=250mA / 10mils
(70mA)
Caps used in 1.5VDDM_TVDAC
and 1.5VDDM_QTVDAC should
be within 250mils of edge
VIA=100mA / 10mils
20060117A-EMI
20mils
(24mA)
Confidential
9/14 modified
remove UMA
parts
50mA
150mA
80mA
80mA
100mA
10mA
150mA
5mA
10mA
80mA
40mA
500mA
250mA
Crestline Power (5/6)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
Custom
14 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer, Inc.
1.05VDDM_PEGPLL
3VDDM
1.5VDDM
1.05VDDM
1.8VDDS
1.05VDDM_PEG
VTT_LF3
VTT_LF2
VTT_LF1
1.05VDDM_DMI
1.05VDDM_PEG
3VDDM_HV
3VDDM_HV
1.5VDDM(8,13,19,20,22,29,31,44)
1.05VDDM(7,8,10,11,13,18,20,22,45)
3VDDM(7,9,11,16,17,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,43,45,46,47)
1.8VDDS(11,13,16,17,45)
1.05VDDM_PEG(11)
1.05VDDM
1.05VDDM
1.05VDDM
1.5VDDM
1.05VDDM
1.05VDDM
1.05VDDM
1.5VDDM
1.05VDDM
1.05VDDM
1.05VDDM
3VDDM
1.8VDDS
1.05VDDM_PEG
1.05VDDM
1.05VDDM_MPLL
1.05VDDM_HPLL
1.05VDDM_DPLLB
1.05VDDM_DPLLA
1.05VDDM_MPLL
1.05VDDM_HPLL
1.05VDDM_DPLLA
1.05VDDM_DPLLB
3VDDM
1.8VDDS_TXLVDS
1.8VDDS
1.8VDDS
3VDDM_TVDACA
VCCA_TVDAC
3VDDM_TVDACA
VCCA_TVDAC
3VDDM
1.8VDDS_TXLVDS
1.05VDDM
3VDDM_HV
1.05VDDM_PEGPLL
1.05VDDM_PEGPLL
3VDDM_HV
C487
1uF 10V+80-20%0603Y5V LR
C522
10uF 10V±10%SMT0805 X5R T=1.25mm C2012X5R1A106KT TDKLR
C506
2.2uF 10V±10%SMT0603X5R C1608X5R1A225KT TDKLR
L45 0 5%1/10W SMT0603 LR
C183 0.1uF 10V10%0402X5R LR
C187
0.47uF 10V ±10% SMD0603 X5R LR
12
C492
0.1uF 10V10%0402X5R LR
C194
0.022uF 16V10%SMT0402 X7R LR
R564
11%1/10W SMT0603 LR
DN1
DIODESWITCHING1SS355 80V100mASOD-3232PIN PSI LR
N P
C517
10uF 10V0805 Y5VTDKLR
C230
4.7uF 6.3V ±10% SMT0805 X5R C2012X5R0J475KT TDK LR
L10
100MHz 600 SMT0603FCM1608KF-601T02 TAI-TECH LR
R274 0 5%1/10W SMT0603 LR
C173
0.022uF 16V10%SMT0402 X7R LR
C494
0.47uF 10V±10%SMD0603 X5R LR
12
C518
0.47uF 10V ±10% SMD0603 X5R LR
12
C182
0.1uF 10V10%0402X5R LR
C191
10uF 10V±10%SMT0805 X5RT=1.25mm C2012X5R1A106KT TDK LR(NU)
C226
0.1uF 10V 10% 0402 X5R LR
L12 0 5%1/10W SMT0603 LR
R225
05%1/16W SMT0402 LR
C526
0.1uF 10V10%0402X5R LR
C530
10uF 10V±10%SMT0805 X5R T=1.25mm C2012X5R1A106KT TDKLR
POWER
CRTPLLA PEGA SM
TV
D TV/CRT
LVDS
VTTLF PEG SM CK AXF VTT
DMI HV
A CK A LVDS
HDA
U31H
CANTIGA_1p0
V3
U3
V2
U2
AD48
AA48
B27
A26
F47
L48
AD1
J48
AE1
B24
A24
AA47
U6
T6
U5
T5
T8
U7
T7
AF1
U13
T13
T12
U11
T11
U10
T10
U9
T9
U8
U12
AP28
AN28
A25
M25
A8
L1
AB2
AH48
AF48
BF21
BH20
BG20
BF20
M38
L28
B22
B21
A21
AR20
AP20
AN20
AR17
AP17
AT16
AR16
AP16
K47
J47
C35
B35
V48
L37
U48
V47
U47
U46
AN17
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
T2
V1
U1
A35
AH47
AG47
B25
AL23
A32
VTT_19
VTT_20
VTT_21
VTT_22
VCCA_PEG_BG
VCCA_PEG_PLL
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VCCA_MPLL
VCCA_TV_DAC_1
VCCA_TV_DAC_2
VCCD_PEG_PLL
VTT_15
VTT_16
VTT_17
VTT_18
VTT_12
VTT_13
VTT_14
VCCD_HPLL
VTT_1
VTT_2
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_3
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_DAC_BG
VCCD_TVDAC
VTTLF1
VTTLF2
VTTLF3
VCC_DMI_1
VCC_DMI_2
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
VCCD_LVDS_1
VCCD_QDAC
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCC_TX_LVDS
VSSA_LVDS
VCC_HV_1
VCC_HV_2
VCC_PEG_1
VCCD_LVDS_2
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VCCA_SM_6
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VTT_23
VTT_24
VTT_25
VCC_HV_3
VCC_DMI_3
VCC_DMI_4
VSSA_DAC_BG
VCCA_SM_CK_NCTF_8
VCC_HDA
C171
0.1uF 10V10%0402X5R LR
C482
10uF 10V±10%SMT0805X5R T=1.25mm C2012X5R1A106KT TDKLR
C553
10uF 10V±10%SMT0805X5R T=1.25mm C2012X5R1A106KT TDKLR
C192
0.022uF 16V10%SMT0402 X7R LR R545 RES 10 5%1/16WSMT0402 LR
R565
05%1/10W SMT0603 LR
R568
05%1/10W SMT0603 LR(NU)
C533
10uF 10V±10%SMT0805 X5RT=1.25mm C2012X5R1A106KT TDK LR(NU)
R272
11%1/10W SMT0603 LR
R579 RES 1 1%1/16W SMT 0402 LR
C208
0.1uF 10V10%0402X5R LR
C529
0.1uF 10V10%0402X5R LR
C170
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
C515
4.7uF 6.3V±10%SMT0805X5R C2012X5R0J475KT TDKLR
+
C479
T100uF 2V±20%ESR=18m SMT7343 EEFCD0D101ER PANASONIC LR
R546
05%1/10W SMT0603 LR
C480
10uF 10V±10%SMT0805 X5R T=1.25mm C2012X5R1A106KT TDKLR
C174
0.022uF 16V10%SMT0402 X7R LR
C206
10uF 10V0805 Y5VTDKLR
L36
RES 5.6 5%1/10W SMT0603RTT035R6JTP RALEC LR
C484
0.47uF 10V ±10% SMD0603 X5R LR
12
+
C245
T100uF 2V ±20% ESR=18m SMT7343 EEFCD0D101ER PANASONIC LR
L11 0 5%1/10W SMT0603 LR
C507
4.7uF 6.3V±10%SMT0805X5R C2012X5R0J475KT TDKLR
C195
0.1uF 10V10%0402X5R LR
C481
0.1uF 10V10%0402X5R LR
L14 SPWR 0 5%1/16W0603
L44 0 5%1/10W SMT0603 LR
C491
0.1uF 10V10%0402X5R LR
C240
1uF 10V +80-20% 0603 Y5V LR
C178
0.1uF 10V10%0402X5R LR
C212
0.1uF 10V10%0402X5R LR
R258 0 5%1/16W SMT0402 LR
C193
0.1uF 10V10%0402X5R LR
C238
0.1uF 10V 10% 0402 X5R LR
C239
10uF 10V ±10% SMT0805 X5R T=1.25mm C2012X5R1A106KT TDK LR
C235
10uF 6.3V 10% SMT0805 X5R C2012X5R0J106K TDK LR(NU)
R254 0 5%1/4W SMT1206 LR
C186
10uF 10V±10%SMT0805 X5R T=1.25mm C2012X5R1A106KT TDKLR
C207
0.1uF 10V10%0402X5R LR
C175
10uF 10V±10%SMT0805 X5RT=1.25mm C2012X5R1A106KT TDK LR(NU)
C211
0.1uF 10V10%0402X5R LR
C483
0.022uF 16V10%SMT0402 X7R LR
L41 0 5%1/10W SMT0603 LR
R224 0 5%1/16W SMT0402 LR
C190
0.1uF 10V10%0402X5R LR
R563
05%1/10W SMT0603 LR
R281 0 5%1/10W SMT0603 LR
R264 0 5%1/16W SMT0402 LR
C545
0.1uF 10V10%0402X5R LR
R276 0 5%1/10W SMT0603 LR
C176
0.1uF 10V10%0402X5R LR
R547 0 5%1/16W SMT0402 LR
C548
10uF 10V±10%SMT0805X5R T=1.25mm C2012X5R1A106KT TDKLR
R229 0 5%1/10W SMT0603 LR

8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
55 +/- 15%
Parameter Breakout Guideline
Trace Length-LA (GMCHBreakout)
Outer Layer : 7 mils
Trace Length-LB (GMCHBreakout to Via2)
DMI Routing Guideline
Inner Layer : 7 milsNominal Didderential Pair-Pitch
Max = 3600 mils
Max = 400 mils
Max = 3600 mils
Outer Layer : 37 mils
Inner Layer : 37 mils
Outer Layer : 5 mils
Inner Layer : 27 mils
Uncoupled Single End Impedance Inner Layer : 4 mils
Pair-to-Pair Pitch
Main Route Guideline
Reference Plane
Outer Layer : 5 mils
LA
Nominal Trace Width
Outer Layer : 27 mils
GMCH
55 +/- 15%
Ground Ground
Rx
Inner Layer : 4 mils
LBTx
Tx
Rx
ICH8M
LC LD LE
LZ LXLY LW LV
Bus-to-Bus Pitch Outer Layer : 20 mils Inner Layer : 22 mils Outer Layer : 12 mils Inner Layer : 15 mils
Trace Length-LC (Via2 to Via3) Max = 5900 mils
Trace Length-LD (Via3 to ICH7m Breakout)
Trace Length-LE (ICH7m Breakout ) Max = 400 mils
Max = 400 mils
Trace Length-LY (Via3 to GMCHBreakout) Max = 3600 mils
Max = 400 mils
Max = 5900 mils
Trace Length-LZ (GMCHBreakout)
Max = 3600 milsTrace Length-LW (ICH7m Breakout to Via2)
Trace Length-LX (Via2 to Via3)
TraceLength-LV ( ICH7m Breakout)
Trace Length-L2 (LV+LW+LX+LY+LZ) Max = 8000 mils
Max = 8000 milsTrace Length-L1 (LA+LB+LC+LD+LE)
Breakout/in
LA/LZ
Microstrip Same Routing layer as LA/LZ
LB/LY
Main Route
LD/LW
Same Routing layer as LE/LV
Main Route
LE/LV
Microstrip
Breakout/in
X O
S < 2S
>3W
S = Spacing
S = Trace Width
*** When routing near the edge of their reference plane , trace should maintain at least40
mils space to the edgeof the plane
*** Match the trace lengths of the complementary signals within each differenti al pair to +/- 5mils
Bus-to-Bus Pitch
LB
Outer Layer : 5 mils
Parameter 55 +/- 15% Breakout Guideline
Outer Layer : 20 mils
Rx
Inner Layer : 20 mils
LD/LW
Breakout/in
Express/Mini Card
Inner Layer : 27 mils
Same Routing layer as LE/LV
Outer Layer : 12 mils
Tx
Uncoupled Single End Impedance
Inner Layer : 15 mils
Main Route
LA/LZ
Inner Layer : 4 mils
Outer Layer : 7 mils
LE/LV
LA
Microstrip
LZ
Ground
Stripline
Nominal Trace Width
Pair-to-Pair Pitch
Ground
Outer Layer : 37 mils Outer Layer : 27 mils
PCIE Routing Guideline
Breakout/in
Inner Layer : 7 mils
Microstrip
Rx
Main Route Guideline
Inner Layer : 37 mils
Nominal Differential Trace Space
LB/LC/LY
Inner Layer : 4 mils
55 +/- 15%
LY
Reference Plane
GMCH
Main Route
Outer Layer : 5 mils
Tx
LC
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LA/LZ
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Same Routing layer as LE/LV
Microstrip
Microstrip
Microstrip
Stripline
Stripline
Stripline
Stripline
Stripline
Stripline
Microstrip
Stripline
Microstrip
Stripline
Microstrip
No routing over plane spli tsSplits/Voids No routing over voids
*** When routing near the edge of their reference plane , trace should maintain at least40
mils space to the edgeof the plane
Max = 10750 mils
Trace Length-L1 (LA+LB+LC)
Trace Length-LB (ICH7m Breakout to
AC cap) Max = 10750 mils
Max = 12000 mils
Trace Length-LZ (ICH7m Breakout)
*** Match the trace lengths of the complementary signals within each differential pair to +/- 5mils
Trace Length-LY (PCIe CNto ICH7m
Breakout) Max = 400 mils
Trace Length-LC (AC cap to
PCIe CN)
Trace Length-LA (ICH7m Breakout)
Max = 11950 mils
Max = 400 mils
No routing over plane spli ts
No routing over voids
Splits/Voids
Max = 12000 milsTrace Length-L2 (LY+LZ)
S < 2S
>3W
S = Spacing
S = Trace Width
X O
Confidential
Crestline Ground (6/6)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
C
15 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.
R268 0 5%1/16W SMT0402 LR
R269 0 5%1/16W SMT0402 LR
R267 0 5%1/16W SMT0402 LR
R273 0 5%1/16W SMT0402 LR
VSS
VSS NCTF
VSS SCB
NC
U31J
CANTIGA_1p0
BG21
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
BA16
AU16
AN16
N16
K16
G16
E16
BG15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
BH8
B9
G9
AD9
AM9
AN9
BC9
M10
BF9
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AC15
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
BC3
AV3
AL3
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
R3
P3
BA2
AR2
AU2
AP2
F3
AW2
AE2
AF2
AH2
AJ2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
BB8
AV8
AT8
U24
U28
U25
U29
L12 VSS_199
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_293
VSS_292
VSS_291
VSS_290
VSS_289
VSS_288
VSS_287
VSS_285
VSS_286
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_244
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_327
VSS_328
VSS_329
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
VSS_330
VSS_331
VSS_333
VSS_336
VSS_335
VSS_337
VSS_332
VSS_334
VSS_341
VSS_340
VSS_339
VSS_338
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_294
VSS_295
VSS_296
VSS_351
VSS_352
VSS_353
VSS_354
VSS_200
VSS
U31I
CANTIGA_1p0
AU48
A23
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BD36
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
AU36
AT24
AH24
AB24
L24
AY46
G24
E24
AG23
B23
AY24
AJ24
AF24
R24
K24
J24
F24
BH23
Y23
AK15
AD12
AJ6
VSS_1
VSS_198
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_97
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_99
VSS_182
VSS_184
VSS_186
VSS_188
VSS_18
VSS_191
VSS_193
VSS_195
VSS_197
VSS_181
VSS_183
VSS_185
VSS_187
VSS_189
VSS_190
VSS_192
VSS_194
VSS_196
VSS_98
VSS_180
VSS_199

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SO-DIMM0
Placethese2.2uF caps near
So-Dimm0
Place one cap close to every 2 pu llup resistors
terminated to 0.9VDDT_DDRII
40 mils
Placethese0.1uF caps near
So-Dimm0 pin79~pin115
area
20mil
20mil
160mil
M_VREF 20mil 20mil
Other signal 20mil
Other signal
Confidential
DDR2 SDRAMSO-DIMM0
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
C
16 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.
M_A_DQ[63..0]
3VDDM
1.8VDDS
0.9VDDT_DDRII
M_VREF
M_A_DQ51
M_A_DQ50
M_A_DQ43
M_A_DQ18
M_A_DQ6
M_A_DQS#6
M_ODT0
M_CS#1
M_A_BS1
M_A_DQ61
M_A_DQ35
M_A_DQ32
M_A_DQ23
M_A_DQ22
M_CS#0
M_A_RAS#
M_A_DQ56
M_A_DQ42
M_A_DQ20
M_A_DQ12
M_A_DQ29
M_A_DQ15
M_A_DQ1
M_A_DQS6
M_A_DQ37
M_A_DQ30
M_A_DQ14
M_A_DQS#5
M_A_DM1
M_CKE1
M_CKE0
M_A_DQ62
M_A_DQ55
M_A_DQ41
M_A_DQ24
M_A_DQ3
M_A_DQ0
M_A_DQS#[7..0]
M_A_DQS#7
M_A_DQS#0
M_A_DQS4
M_A_DQS3
M_A_DM2
M_A_BS2
M_A_DQ4
M_A_DM3
M_A_WE#
M_A_DQ54
M_A_DQ47
M_A_DQ25
M_A_DM[7..0]
M_A_DQS#3
M_A_DQS7
M_A_DM0
M_A_DQ48
M_A_DQ5
M_A_DQS0
M_A_CAS#
M_A_DQ46
M_A_DQ21
M_A_DQ17
M_A_DQ16
M_A_DQ10
M_A_DQS#4
M_A_DM6
M_A_DM5
M_A_DM4
M_A_DQ40
M_A_DQ28
M_A_DQ60
M_A_DQ57
M_A_DQ44
M_A_DQ31
M_A_DQ2
M_A_DQS5
M_A_DQ63
M_A_DQ58
M_A_DQ52
M_A_DQ49
M_A_DQS1
M_A_BS0
M_A_DQ59
M_A_DQ45
M_A_DQ36
M_A_DQ34
M_A_DQ33
M_A_DQ26
M_A_DQ19
M_A_DM7
M_A_DQ39
M_A_DQ38
M_A_DQ13
M_A_DQ11
M_A_DQ9
M_A_DQ8
M_A_DQS#2
M_ODT1
M_A_DQ27
M_A_DQS[7..0]
M_A_DQS#1
M_A_DQS2
M_A_DQ53
M_A_DQ7
M_A_A5
M_CS#1
M_A_A7
M_A_CAS#
M_A_A6
M_A_WE#
M_A_A12
M_A_A9
M_A_A1
M_A_BS0
M_A_A3
M_ODT1
M_A_A10
M_A_A13
M_A_RAS#
M_ODT0
M_CS#0
M_A_BS1
M_CKE1
M_A_A4
M_A_A11
M_A_A2
M_A_A0
M_A_A9
M_A_A2
M_A_A5
M_A_A10
M_A_A6
M_A_A7
M_A_BS2
M_A_A14
M_A_A1
M_A_A8
M_A_A3
M_A_A8
M_A_A4
M_A_A13
M_A_A11
M_A_A0
M_A_A14
M_A_A12
M_A_A[14..0]
M_CKE0
0.9VDDT_DDRII(17,45)
1.8VDDS(11,13,14,17,45)
3VDDM(7,9,11,14,17,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,43,45,46,47)
M_VREF(11,17,45)
M_A_DQ[63..0] (12)M_A_A[14..0](12)
M_CKE1(11) M_A_CAS#(12)
M_A_WE#(12)
M_CKE0(11)
M_A_RAS#(12)
SMB_CLK(17,18,21,29,31)SMB_DATA(17,18,21,29,31)
M_ODT1(11) M_ODT0(11)
M_A_DM[7..0](12)M_A_DQS[7..0](12)
M_A_DQS#[7..0](12)
M_A_BS2(12)
M_A_BS1(12) M_A_BS0(12)
M_CS#1(11) M_CS#0(11)
M_CLK_DDR#1(11)
M_CLK_DDR0(11)M_CLK_DDR#0(11) M_CLK_DDR1(11)
PM_EXTTS#0(11)
0.9VDDT_DDRII
1.8VDDS
1.8VDDS
3VDDM
1.8VDDS
M_VREF
C297
0.1uF 16V80-20%0402 Y5VLR(NU)
C290
0.1uF 16V80-20%0402 Y5VLR
C610 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR
C302
0.1uF 16V80-20%0402 Y5VLR
T15 1
RP41
10K 5%SMT1010 1/16W 4P2R LR
1 24
3
C291
0.1uF 16V80-20%0402 Y5VLR(NU)
C294
0.1uF 16V80-20%0402 Y5VLR
C326
0.1uF 16V80-20%0402 Y5VLR
RP35
56 5%SMT1010 1/16W 4P2R RS2N-56R0-J2N CYNTEC LR
1
24 3
C293
0.1uF 16V80-20%0402 Y5VLR
C313 0.1uF 16V 80-20% 0402 Y5V LR C609 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR
RP39
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
R328 1K 1%1/16W SMT0402 LR(NU)
C296
0.1uF 16V80-20%0402 Y5VLR(NU)
C299
0.1uF 16V80-20%0402 Y5VLR(NU)
C300
0.1uF 16V80-20%0402 Y5VLR
RP33
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
C317 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR C611 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR
REV TYPE
CN35
SCKT FOXCONN SMT DDR2 SO-DIMM H=5.2REV AS0A421-N2RN-4F LR
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
102
101
100
99
98
97
94
92
93
91
105
90
89
116
107
106
85
30
32
164
166
79
80
113
108
109
110
115
198
200
197
195
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
112
111
117
96
95
118
81
82
87
103
88
104
199
1
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
83
120
50
69
163
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
86
84
114
119
11
29
49
68
129
146
167
186
203
204
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
BA0
BA1
A16_BA2
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
S0#
S1#
SA0
SA1
SCL
SDA
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDDSPD
VREF1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
NC1
NC2
NC3
NC4
NCTEST
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
A14
A15
ODT0
ODT1
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
GND0
GND1
RP34
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
C315 1000pF 50V 10% SMT0603 X7R LR
C301
0.1uF 16V80-20%0402 Y5VLR(NU)
C292
0.1uF 16V80-20%0402 Y5VLR
RP36
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
C295
0.1uF 16V80-20%0402 Y5VLR(NU)
C608 0.1uF 16V 80-20% 0402 Y5V LR
R327
56 5%1/16W SMT0402 LR
C318 1000pF 50V 10% SMT0603 X7R LR
R329 0 5%1/16W SMT0402 LR
C612 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR C607 0.1uF 16V 80-20% 0402 Y5V LR
C298
0.1uF 16V80-20%0402 Y5VLR
RP37
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
C314 0.1uF 16V 80-20% 0402 Y5V LR
C309
0.1uF 16V80-20%0402 Y5VLR
RP38
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
R330 1K 1%1/16W SMT0402 LR(NU)
+
C328 T100uF 2V ±20% ESR=18m SMT7343 EEFCD0D101ER PANASONIC LR(NU)

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Other signal
Other signal
SO-DIMM1
20mil
M_VREF
Place one cap close to every 2 pu llup resistors
terminated to 0.9VDDT_DDRII
40 mils
20mil 20mil
20mil
20mil
160mil
Placethese0.1uF caps near
So-Dimm0 pin79~pin115
area
Placethese2.2uF caps near
So-Dimm0
Confidential
DDR2 SDRAMSO-DIMM1
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
C
17 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.
M_B_A[14..0] M_B_DQ[63..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
M_B_WE#
M_B_DQ56
M_B_DQ55
M_B_DQ29
M_B_DQ6
M_B_DQ47
M_B_DQ43
M_B_DQ12
M_B_DQS#5
M_B_DQS5
M_B_DQ61
M_B_DQ18
M_B_DQ11
M_B_DM5
M_B_DM0
M_B_DQ60
M_B_DQ19
M_B_DQ5
M_B_RAS#
M_B_DQ53
M_B_DQ36
M_B_DQ34
M_B_DQ24
M_B_DQ15
M_B_DQS1
M_B_DQS#2
M_B_DQS6
M_B_DM6
M_B_DM1
M_CKE4
M_B_BS2
M_B_DQ63
M_B_DQ46
M_B_DQ26
M_B_DQ16
M_B_DQ8
M_B_DQ1
M_B_DQS#3
M_B_DQS#1
M_B_DQ39
M_B_DQ37
M_B_DQ7
M_B_DQ48
M_B_DQ42
M_B_DQ10
M_B_DQS#7
M_B_DQS7
M_B_DQS2
M_B_DM2
M_CS#2
M_B_DQ62
M_B_DQ35
M_B_DQ17
M_B_DQ14
M_B_DQ2
M_ODT2
M_B_DM7
M_B_BS1
M_B_DQ57
M_B_DQ45
M_B_DQ25
M_B_DQ22
M_B_DQ4
M_B_DQS#6
M_B_DQ59
M_B_DQ52
M_B_DQ9
M_B_DM[7..0]
M_B_DQS3
M_CKE3
M_B_DQ23
M_ODT3
M_B_DQS0
M_B_DM3
M_B_DQ58
M_B_DQ54
M_B_DQ40
M_B_DQ32
M_B_DQ30
M_B_DQ27
M_B_DQ21
M_B_DQ3
M_CS#3
M_B_DQ50
M_B_DQ49
M_B_DQ41
M_B_DQ20
M_B_DQ13
M_B_DQ0
M_B_DQS#0
M_B_DQ33
M_B_DQ31
M_B_DQS#4
M_B_DQS4
M_B_DM4
M_B_CAS#
M_B_BS0
M_B_DQ51
M_B_DQ44
M_B_DQ38
M_B_DQ28
3VDDM
1.8VDDS
M_VREF
0.9VDDT_DDRII
M_B_BS2
M_CKE3
M_ODT3
M_CS#3
M_B_A11
M_B_A6
M_B_A7
M_CKE4
M_B_A0
M_B_A4
M_B_BS1
M_B_A2
M_CS#2
M_B_RAS#
M_B_A8
M_B_A12
M_B_A5
M_B_A9
M_B_A10
M_B_A3
M_B_BS0
M_B_A1
M_B_A14
M_B_A10
M_B_A6
M_B_A2
M_B_CAS#
M_B_A3
M_B_A8
M_B_A14
M_B_A11
M_B_WE#
M_B_A7
M_B_A13
M_B_A5
M_ODT2
M_B_A9
M_B_A13
M_B_A4
M_B_A0
M_B_A12
M_B_A1
0.9VDDT_DDRII(16,45)
1.8VDDS(11,13,14,16,45)
M_VREF(11,16,45)
3VDDM(7,9,11,14,16,18,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,43,45,46,47)
M_B_DQ[63..0] (12)M_B_A[14..0](12)
M_CKE4(11) M_B_CAS#(12)
M_B_WE#(12)
M_CKE3(11)
M_B_RAS#(12)
SMB_DATA(16,18,21,29,31)
M_ODT3(11) M_ODT2(11)
M_B_DM[7..0](12)M_B_DQS[7..0](12)
M_B_DQS#[7..0](12)
SMB_CLK(16,18,21,29,31)
M_B_BS2(12)
M_B_BS1(12) M_B_BS0(12)
M_CS#3(11) M_CS#2(11)
M_CLK_DDR#4(11)
M_CLK_DDR3(11)M_CLK_DDR#3(11) M_CLK_DDR4(11)
PM_EXTTS#1(11)
0.9VDDT_DDRII
1.8VDDS
1.8VDDS
3VDDM
3VDDM
1.8VDDS
M_VREF
C563 0.1uF 16V 80-20% 0402 Y5V LR
C336
0.1uF 16V80-20%0402 Y5VLR(NU)
C335
0.1uF 16V80-20%0402 Y5VLR
C324 0.1uF 16V 80-20% 0402 Y5V LR C561 1000pF 50V 10% SMT0603 X7R LR
C341
0.1uF 16V80-20%0402 Y5VLR
CN37
SCKT FOXCONN SMT DDR2 H=4.0STD AS0A421-N4SN-4F LR
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
102
101
100
99
98
97
94
92
93
91
105
90
89
116
107
106
85
30
32
164
166
79
80
113
108
109
110
115
198
200
197
195
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
112
111
117
96
95
118
81
82
87
103
88
104
199
1
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
83
120
50
69
163
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
86
84
114
119
11
29
49
68
129
146
167
186
203
204
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
BA0
BA1
A16_BA2
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
S0#
S1#
SA0
SA1
SCL
SDA
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDDSPD
VREF1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
NC1
NC2
NC3
NC4
NCTEST
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
A14
A15
ODT0
ODT1
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
GND0
GND1
RP48
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
RP44
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
RP42
10K 5%SMT1010 1/16W 4P2R LR
1 24
3
RP45
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
C338
0.1uF 16V80-20%0402 Y5VLR(NU)
RP49
56 5%SMT1010 1/16W 4P2R RS2N-56R0-J2N CYNTEC LR
1
24 3
C331
0.1uF 16V80-20%0402 Y5VLR
C333
0.1uF 16V80-20%0402 Y5VLR
C559 1000pF 50V 10% SMT0603 X7R LR
R337
56 5%1/16W SMT0402 LR
C560 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR C321 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR
C340
0.1uF 16V80-20%0402 Y5VLR(NU)
C339
0.1uF 16V80-20%0402 Y5VLR
C322 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR
R331
1K 1%1/16W SMT0402 LR(NU)
C337
0.1uF 16V80-20%0402 Y5VLR
RP43
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
RP47
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
C323 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR C327 0.1uF 16V 80-20% 0402 Y5V LR
C332
0.1uF 16V80-20%0402 Y5VLR(NU)
+
C558 T100uF 2V ±20% ESR=18m SMT7343 EEFCD0D101ER PANASONIC LR(NU) C562 0.1uF 16V 80-20% 0402 Y5V LR
C334
0.1uF 16V80-20%0402 Y5VLR(NU)
RP46
56 5%SMT2010 1/16W 8P4R 0.5mm LR
1 8
2 7
3 6
4 5
C330
0.1uF 16V80-20%0402 Y5VLR(NU)
R332
1K 1%1/16W SMT0402 LR(NU)
C307
0.1uF 16V80-20%0402 Y5VLR
R333 0 5%1/16W SMT0402 LR
T16 1
C329
0.1uF 16V80-20%0402 Y5VLR
C316 2.2uF 10V ±10% SMT0603 X5R C1608X5R1A225KT TDK LR
C325
0.1uF 16V80-20%0402 Y5VLR

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0
SS3
1
SS2
1
Spread Mode
1.0
3.0 1 1
0
SS1
0
1.5
0
DOWN
Center
0
0Center
Center
1
DOWN
0
1
2.51
0
1
1
0
1
0 +/- 0.3
1
0
DOWN
1
1.75
SS0
1
+/- 0.50
0
1
1
Spread Mode
DOWN 0
SS2
0
Center
+/- 1.25
0
+/- 0.4
0
Center
1
1
DOWN
1.25
0
2.0
1
1
0
0
1
1
1
0
Spread Amount %
DOWN
0
1
Center
1
1
Center
SS3
1
1
1
0
+/- 0.8
SS0
1
Center
1
+/- 1.5
SS1
DOWN
0
0
1
0
0
+/- 1.0
+/- 0.6
0.8
0
0
0
DOWN
0
Spread Amount %
0
1
0
FSC
Frequency MHz
166
FSA
CPU_BSEL1
1 2000
1
CPU_BSEL0CPU_BSEL2
0 1
FSB Host Clock
Confidential
CPU
NB
NB
NB
NB
mini card
10mil
mini card
02/06
LAN
Placed within
500 mils of
CK410M
SB
SB
10mil
VGA
Placed within
500mils of
ICH8M ball
PIN3 HI-->4M / LO-->32K
PIN5&PIN7 LO-->STOP OUTPOU
EMI
V02 NU
V02 NU
Clock Generator IC ICS9LP505-1
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN ,ROC
(886-2)8751-8751
C
18 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
FirstInternational Computer, Inc.
CLK_PCI_1394
CLK_PCIF_ICH
CLK_PCI_MINI
CLK_48M_ICH
CLK_14M_ICH
CLK_PCI_EC
3VDDM
1.05VDDM
3VDDA
CPU_BSEL2
CPU_BSEL0
CPU_BSEL1
CPU0
SRC11
XTAL_IN
SRC8
PCIF5
CPU1#
SS_CLK#
CLK_MCH_R_OE#
CLK_PCI_MINI
CPU0#
SRC4
SRC2
VDDIO_CLK
SRC6
CLK_PCI_EC
SRV_9
SRC4#
XTAL_OUT
DOT96
CLK_14M_ICH
SRC10
CLK_PCIF_ICH
SRC6#
PCI0_OE#_R
SS_CLK
SRC11#
DOT96#
SRC10#
SMB_DATA
SRV_9#
CPU_BSEL0
SRC8#
FSC
FSA
CPU_BSEL2
VDD_CK505
PCI2_TMD
SRC2#
CPU1
SMB_CLK
CPU_BSEL1
PCIF4
3VDDA_LAN
PMU3V
CLK_48M_ICH
VDD
STOP#_4M
STOP#_24M
CLK_4M
STOP#_LAN
VDD CLK_25
SEL_4M STOP#_SATA
CLK_24576
LF
CLK_48M_ICH
1.05VDDM(7,8,10,11,13,14,20,22,45)
3VDDM(7,9,11,14,16,17,19,20,21,22,23,24,25,26,29,30,31,32,33,35,37,43,45,46,47)
3VDDA(9,19,20,21,22,23,24,26,28,29,31,32,33,37,41,43,44,45)
CPU_BSEL2(7)
MCH_BSEL1 (11)CPU_BSEL1(7)
MCH_BSEL2 (11)
MCH_BSEL0 (11)CPU_BSEL0(7)
CLK_48M_ICHSS (21)
CLK_PCIE_RB# (29)
DREFCLK (11)
CLK_CPU_BCLK (7)
CLKREQ_EX0 (31)
CLK_PCIE_MINI# (29)
CLK_PCI_1394
CLK_SATA_QE#(21)
CLK_PCIE_RB (29)
CLK_PCI_EC(37)
CLK_PCIE_SATA# (20)
CLK_PCIE_ICH# (19)
SMB_DATA(16,17,21,29,31)
PM_STPCPU# (21)
CLK_MCH_BCLK# (10)
CLK_PWRGD (21)
CLK_MCH_BCLK (10)
PM_STPPCI# (21)
DREFSSCLK# (11)
CLK_PCIE_ICH (19)
CLK_PCIE_3GPLL (11)
DREFCLK# (11)
CLK_14M_ICH(21)
CLK_PCI_MINI(29)
SMB_CLK(16,17,21,29,31)
CLK_PCIE_LAN (33)
CLK_CPU_BCLK# (7)
CLK_MCH_OE# (11)
CLK_PCIE_LAN# (33)
CLK_PCIE_VGA
CLK_PCIE_EXPCARD# (31)
CLK_PCIE_VGA#
CLK_PCIE_SATA (20)
CLK_48M_CARD(32)
CLK_PCIE_EXPCARD (31)
CLK_PCIF_ICH(19)
CLK_PCIE_MINI (29)
CLK_PCIE_3GPLL# (11)
DREFSSCLK (11)
PMX_4M(37)
3VDDA_LAN(33)
PMU3V(20,37,41,43)
LAN_CLKREQ#(33)
SUSCLK(21)
LAN_25M (33)
RTC_X2(20) RTC_X1(20)
1.05VDDM
3VDDM
VDD_CK505
VDDIO_CLK
3VDDM
VDDIO_CLK
1.05VDDM
3VDDM
3VDDA
VDD_CK505
PMU3V
3VDDA_LAN
U27
IC PSC1P7400 16PIN LR(NU)
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
Xin
Xout
Sel_4M/32.768K
4M/32.768K
STOP#_4M/32.768K
VDD
STOP#_LAN
GND 25M_LAN
25M_SATA
LF
GND
VDD
STOP#_SATA
STOP#_24.576M
24.576M
RP29 0 5% SMT1010 1/16W4P2R LR
1
24 3
R309 1K 5% 1/16WSMT0402 LR(NU)
C278 MO-CAP5pF 50V ±0.5pF SMT0402 NPO LR
R594
05% 1/16WSMT0402 LR(NU)
R540
05% 1/16WSMT0402 LR(NU)
R319
1K 5% 1/16WSMT0402 LR(NU)
R302
05% 1/10WSMT0603 LR
C256 10uF 6.3V 80-20% SMT0805 Y5V H=1.25mm JMK212F106ZG-T TAIYO LR(NU)
RP21 0 5% SMT1010 1/16W4P2R LR
1
24 3
C474
0.01uF 16V10% SMT0603 X7R LR(NU)
R537
05% 1/16WSMT0402 LR(NU)
R323
10K 5% 1/16W SMT0402 LR
R326
05% 1/8WSMT0805 LR
RP22 0 5% SMT1010 1/16W4P2R LR(NU)
1
24 3
R529
05% 1/16WSMT0402 LR(NU)
R197
1K 1% 1/16WSMT0402 LR(NU)
C277 0.1uF 10V 10% 0402 X5R LR
R526
20K 1% 1/16WSMT0402 LR(NU)
R317 RES 33 5% 1/16WSMT0402 LR
R324 RES 475 1% 1/16WSMT0402 LR
R313
2.2K 5% 1/16WSMT0402 LR
R592 10K 5% 1/16W SMT0402 LR(NU)
C463
0.01uF 16V10% SMT0603 X7R LR(NU)
RP25 0 5% SMT1010 1/16W4P2R LR
1
24 3
R528 10K 5% 1/16WSMT0402 LR(NU)
RP20 0 5% SMT1010 1/16W4P2R LR
1
24 3
C276 0.1uF 10V 10% 0402 X5R LR
U28
IC USB EMI Reduction PCS3P73U00AG-08-CR TDFN-8P2x2 PCS(NU)
1
2
3
4 5
6
7
8CLKIN/XIN
REFOUT/XOUT
FS
GND MODOUT
MR
SSXEXTR
VDD
R312
1K 5% 1/16WSMT0402 LR
RP26 0 5% SMT1010 1/16W4P2R LR
1
24 3
C472
MO-CAP4.7uF 10V10% SMT0603 X5R LR(NU)
R322 4.7K 5% 1/16W SMT0402 LR
C269 0.1uF 10V 10% 0402 X5R LR
C270 0.1uF 10V 10% 0402 X5R LR
R325 4.7K 5% 1/16W SMT0402 LR
RP31
RP33 5% SMT1010 1/16W4P2R LR
1
24 3
U17
ASIC CLOCK GENERATOR RTM875N-606-VD-GR QFN 64PIN VER:D REALTEK LR
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
7
6
5
4
3
2
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
65
PCI_0/CLKREQ_A#
VDD_PCI
PCI_1/CLKREQ_B#
PCI_2
PCI_3
^PCI_4/LCDCLK_SEL
PCIF_5/ITP_EN
VSS_PCI
VDD_48
USB_48MHz/FS_A
VSS_48
VDD_I/O
SRC_0/DOT_96
SRC_0#/DOT_96#
VSS_I/O
VDD_PLL3
LCDCLK/27M
LCDCLK#/27M_SS
VSS_PLL3
VDD_PLL3_I/O
SRC_2
SRC_2#
VSS_SRC_1
SRC_3/CLKREQ_C#
SRC_3#/CLKREQ_D#
VDD_SRC_I/O_1
SRC_4
SRC_4#
VSS_SRC_2
SRC_9
SRC_9#
SRC_11#/CLKREQ_G#
SCL
SDA
REF/FS_C/TEST_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FS_B/TEST_MODE
CKPWRGD/PD#
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1_MCH
CPU_1_MCH#
VDD_CPU_I/O
NC
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
VDD_SRC_I/O_3
SRC_7/CLKREQ_F#
SRC_7#/CLKREQ_E#
VSS_SRC_3
SRC_6
SRC_6#
VDD_SRC
PCI_STOP#
CPU_STOP#
VDD_SRC_I/O_2
SRC_10#
SRC_10
SRC_11/CLKREQ_H#
THRM_PAD_1 C287 MO-CAP5pF 50V ±0.5pF SMT0402 NPO LR
R315 22 1% 1/16WSMT0402 LR
C264 0.1uF 10V 10% 0402 X5R LR
R311 475 1% 1/16W0402 LR
C266 0.1uF 10V 10% 0402 X5R LR(NU)
Y4
FREQ XTL 14.318180MHz SMD-49 2PIN 20pF ±30ppm XSA01431AFK1H-O H.ELE LR
R595
05% 1/16WSMT0402 LR
C261 0.1uF 10V 10% 0402 X5R LR
R508
10K 5% 1/16WSMT0402 LR(NU)
C260 0.1uF 10V 10% 0402 X5R LR
C288 MO-CAP5pF 50V ±0.5pF SMT0402 NPO LR
R539
05% 1/16WSMT0402 LR
C273 10uF 10V 0805 Y5V TDK LR
R204 10K 5% 1/16WSMT0402 LR(NU)
C281 MO-CAP 4.7uF 10V 80-20% 0603 Y5V LR
R538 10K 5% 1/16WSMT0402 LR(NU)
RP30
1K 5% SMT1010 1/16W4P2R LR
1
24 3
C676
0.1uF 16V 80-20% SMT0402 Y5V LR(NU)
C279 MO-CAP5pF 50V ±0.5pF SMT0402 NPO LR
C283
33pF 50V5% SMT0402 NPO LR
RP19 0 5% SMT1010 1/16W4P2R LR
1
24 3
R593 1K 5% 1/16WSMT0402 LR
C280 MO-CAP5pF 50V ±0.5pF SMT0402 NPO LR
C289
33pF 50V5% SMT0402 NPO LR
R308 1K 5% 1/16WSMT0402 LR
C259 0.1uF 10V 10% 0402 X5R LR
RP18 0 5% SMT1010 1/16W4P2R LR
1
24 3
R304 RES 475 1% 1/16WSMT0402 LR
RP32
RP2.2K 5% SMT1010 4P2R 1/16WLR
C272 0.1uF 10V 10% 0402 X5R LR
RP24 0 5% SMT1010 1/16W4P2R LR
1
24 3
R318 RES 33 5% 1/16WSMT0402 LR
C286 MO-CAP5pF 50V ±0.5pF SMT0402 NPO LR
C258 0.1uF 10V 10% 0402 X5R LR
R704
05% 1/16WSMT0402 LR(NU)
R591 1K 5% 1/16WSMT0402 LR
R590 10K 5% 1/16WSMT0402 LR
R305 RES 475 1% 1/16WSMT0402 LR
RP27 0 5% SMT1010 1/16W4P2R LR
1
24 3
R314 22 1% 1/16WSMT0402 LR
C271 0.1uF 10V 10% 0402 X5R LR
RP23 0 5% SMT1010 1/16W4P2R LR
1
24 3
C275 0.1uF 10V 10% 0402 X5R LR
RP28 0 5% SMT1010 1/16W4P2R LR
1
24 3
R316 33 5% 1/16WSMT0402 LR Sn
R527
4.7 5% 1/16WSMT0402 LR(NU)
RP61
0 5% 0402*2 1/16W4P2R(NU)
1
24 3

10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
Buffer to reduce loading on PLT_RST#
Place within 500mils of ICH
PCI Pull up
PCIE AC coupling caps need to be
within 250mils of the driver
M/B IO PORT
5/5 mils spacing on microstrip
Place within 500mils of ICH
High = Default
A16 swap overrideStrap
Low =A16 swap override enabled
PCI_GNT#3
PCI_GNT#0
Boot BIOS StrapSPI_CS#1 Boot BIOS Location
0 1
1 0
1 1
SPI
PCI
LPC( Default)
Confidential
CARD READER
Express Card
FINGER PRINT
CCD
MINI CARD (WIRELESS)
ROBSON
MINI CARD (Robson)
MINI CARD (WIRELESS)
LAN
SB/LAN/CD-ROM/EXPRESS CARD/Mini Card
PCMCIA
1394
PCMCIA
1394
Express Card
ICH8MPCI/PCIE/DMI (1/4)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
C
19 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.
PCI_IRQA#
PCI_IRQB#
PCI_IRQC#
PCI_IRQD# PCI_IRQG#
PCI_IRQE#
PCI_IRQH#
PLT_RST#
PLT_RST#
PCI_IRDY#
PCI_DEVSEL#
PCI_PERR#
PCI_STOP#
PCI_SERR#
PCI_FRAME#
PCI_TRDY#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#3
PCI_GNT#0
PCI_GNT#1
PCI_GNT#3
PCI_GNT#3
OC7#
OC6#
OC8#
OC9#
PCI_REQ#2
PCI_LOCK#
PCI_Q_PME#
PCI_IRQF#
PCI_GNT#0
SB_PCIE_TXP1
SB_PCIE_TXN1
3VDDA
1.5VDDM
3VDDM
PCI_GNT#2
OC3#
OC2#
OC1#
OC0#
OC4#
OC5#
OC6#
OC8#
OC2#
OC1#
OC4#
OC9#
OC5#
OC7#
OC0#
PCI_PERR#
PCI_IRQB#
PCI_IRQE#
PCI_REQ#0
PCI_STOP#
PCI_IRQC#
PCI_LOCK#
PCI_IRDY#
PCI_DEVSEL#
PCI_REQ#1
PCI_TRDY#
PCI_IRQD#
PCI_IRQG#
PCI_IRQH#
PCI_SERR#
PCI_IRQF#
PCI_REQ#2
PCI_IRQA#
PCI_REQ#3
PCI_FRAME#
OC10#
OC11#
USB_RBIAS_PN
SPI_SI
OC11#
OC10#
OC3#
PCI_Q_PME#
3VDDM(7,9,11,14,16,17,18,20,21,22,23,24,25,26,29,30,31,32,33,35,37,43,45,46,47)
1.5VDDM(8,13,14,20,22,29,31,44)
3VDDA(9,18,20,21,22,23,24,26,28,29,31,32,33,37,41,43,44,45)
SPI_CLK(23) SPI_CS#0(23)
SPI_SI(23) SPI_SO(23)
PCI_IRDY#
PCI_PAR
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
USB_PN1 (28)
USB_PN5 (28)
USB_PN0 (28)
USB_PP1 (28)
USB_PP0 (28)
USB_PP5 (28)
USB_PN3 (28)
USB_PN7 (29)
USB_PP7 (29)
USB_PN2 (31)
USB_PP2 (31)
USB_PP3 (28)
PCI_C/BE#2
PCI_C/BE#3
PCI_C/BE#0
PCI_C/BE#1
PCI_LOCK#
USB_PN4 (32)
USB_PP4 (32)
USB_PP6 (31)
USB_PN6 (31)
USB_PP8 (29)
USB_PN8 (29)
USB_PP9 (31)
USB_PN9 (31)
PCI_REQ#1
DMI_RXN0 (11)
DMI_RXP0 (11)
DMI_RXN1 (11)
DMI_RXP1 (11)
PCI_REQ#2
CLK_PCIE_ICH# (18)
DMI_RXP3 (11)
DMI_RXN2 (11)
CLK_PCIE_ICH (18)
DMI_RXP2 (11)
DMI_RXN3 (11)
CLK_PCIF_ICH (18)
PCIE_RXN2(29) PCIE_RXP2(29)
PCIE_RXP3(29) PCIE_RXN3(29)
PCI_Q_PME#
SB_PCIE_RXP1(31) SB_PCIE_RXN1(31)
GLAN_RXP(33) GLAN_RXN(33)
PLT_RST# (11)
BUF_PLT_RST# (21,29,31,33)
PCI_RST# (32,37)
PCI_GNT#2
PCI_GNT#1
DMI_TXN0 (11)
DMI_TXP0 (11)
DMI_TXN1 (11)
DMI_TXP1 (11)
DMI_TXP3 (11)
DMI_TXP2 (11)
DMI_TXN2 (11)
DMI_TXN3 (11)
PCIE_TXP1(31) PCIE_TXN1(31)
PCIE_TXP2(29) PCIE_TXN2(29)
PCIE_TXP3(29) PCIE_TXN3(29)
GLAN_TXP(33) GLAN_TXN(33)
1.5VDDM
3VDDM
3VDDM
3VDDA
3VDDM
3VDDM
R143 1K 5%1/16WSMT0402 LR
R169 15 1%1/16W SMT0402 LR
C458 0.1uF 10V10%0402X5R LR
C455 0.1uF 10V10%0402X5R LR
R117
RES 8.2K 5%1/16W SMT0402 LR(NU)
RP5
10K 5%SMT1010 1/16W 4P2R LR
1
24 3
C454 0.1uF 10V10%0402X5R LR
R449
RES 24.9 1%1/16WSMT0402 LR
R444
RES 22.6 1%1/16WSMT0402 LR
RP12
8.2K 5%SMT2010 1/16W 8P4R LR
1 8
2 7
3 6
4 5
R182
RES 20K 5%1/16W SMT0402 LR(NU)
C462 0.1uF 10V10%0402X5R LR
C459 0.1uF 10V10%0402X5R LR
RP16
8.2K 5%SMT2010 1/16W 8P4R LR
1 8
2 7
3 6
4 5
C461
0.1uF 16V80-20%0402 Y5VLR
RP810K 5%SMT1010 1/16W 4P2R LR 1
24 3
PCI
Interrupt I/F
U25B
ICH9M REV 1.0
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
F1
G4
B6
A7
F13
F12
E6
F6
D8
B4
D6
A5
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
C14
D4
R2
J5
E1
J6
C4 G2
F2
K6
H4
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
PIRQA#
PIRQB#
PIRQC#
PIRQD# PIRQH#/GPIO5
PIRQG#/GPIO4
PIRQF#/GPIO3
PIRQE#/GPIO2
R144 1K 5%1/16W SMT0402 LR(NU)
C450
RP9
8.2K 5%SMT2010 1/16W 8P4R LR
1 8
2 7
3 6
4 5
R137
10K 5%1/16W SMT0402 LR(NU)
RP710K 5%SMT2010 1/16W 8P4R LR 8
7
6
54
3
2
1
R505
100K 5%1/16WSMT0402 LR
RP6
10K 5%SMT2010 1/16W 8P4R LR 8
7
6
54
3
2
1
C464 0.1uF 10V10%0402X5R LR
RP15
8.2K 5%SMT2010 1/16W 8P4R LR
1 8
2 7
3 6
4 5
RP14
15 5%SMT1010 1/16W 4P2R RS2N-22R0-J2N CYNTEC LR
1
24 3
C451 0.1uF 10V10%0402X5R LR
U26
DL-IC NC7S08P5X_NL SC70 5PIN FAIRCHILD LR
1
2
53
4
PCI-Express
Direct Media Interface
USB
SPI
U25D
ICH9M REV 1.0
N29
N28
P27
P26
L29
L28
M27
M26
J29
J28
K27
K26
G29
G28
H27
H26
E29
E28
F27
F26
C29
C28
D27
D26
V27
V26
U29
U28
Y27
Y26
W29
W28
AB27
AB26
AA29
AA28
AD27
AD26
AC29
AC28
T26
T25
AF29
AF28
N4
N5
N6
P6
M1
N2
M4
M3
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
AG1
AG2
D23
D24
F23
D25
E23
N3
N1
W2
W1
V2
V3
U5
U1
U4
U2
P5
P3
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBRBIAS#
USBRBIAS
SPI_CLK
SPI_CS0#
SPI_CS1#/GPIO58/CLGPIO6
SPI_MOSI
SPI_MISO
OC8#/GPIO44
OC9#/GPIO45
USBP8P
USBP8N
USBP9N
USBP9P
USBP10N
USBP11N
USBP10P
USBP11P
OC10#/GPIO46
OC11#/GPIO47
RP13
8.2K 5%SMT2010 1/16W 8P4R LR
1 8
2 7
3 6
4 5

8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
20mil
RTC Circuit
20mil
INTVRMEN
Placed within
500mils of
ICH8M ball
1. The ICH8M requires a length less than 1 inch on each branch ( from crystal's terminal to RTCXn ball)
5. Ground guard plane is highly recommended
4. Trace signal coupling must limited as much as possible by avoiding the routing of adjacent PCI signals close to RTCX1 and RTCX2
3. On FR-4, a 5-mils trace has approximately 2pF per inch
2. Routing the RTC circuit should be kept simple to simplify the trace length measurement and increase accuracy on calculating trace capacitances
2. It is recommended that this larger capacitor and small resistor value
in order to reduce the likelihood of glitching of RTCRST#
1. RC delay time should be in the range of 18~25ms
6 mils
ICH8-M internal VR enable
strap
Enable Disable
01(Default)
Low = Internal VR Disabled
High = Internal VR Enabled (Default)
ICH8-M LAN100 SLP Strap
Internal VR for VccLAN1_05 and VccCL1_05)
LAN100_SLP
5mils
Confidential
TPM/MINI CARD/PMX
20mil
Needs to be placed within 2" of ICH7m
For D.C 56
For Q.C 50
For D.C 56
For Q.C 50
ICH8MCPU/IDE/SATA (2/4)
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2)8751-8751
C
20 49Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.
H_A20GATE
H_RCIN#
SM_INTRUDER#
RTC_RST#
RTC_X2
RTC_X1
ICH_INTVRMEN
ICH_INTVRMEN
LAN100_SLP
LAN100_SLP
3VDDA_RTC
1.05VDDM
PMU3V
1.5VDDM
GPIO56
TP8
3VDDM
SATA_RBIAS_PN
3VDDA
3VDDA_LAN
CARD_RST#
LPC_AD0 (29,37)
LPC_AD1 (29,37)
LPC_AD2 (29,37)
LPC_AD3 (29,37)
1.5VDDM(8,13,14,19,22,29,31,44)
1.05VDDM(7,8,10,11,13,14,18,22,45)
PMU3V(18,37,41,43)
3VDDA_RTC(22)
3VDDM(7,9,11,14,16,17,18,19,21,22,23,24,25,26,29,30,31,32,33,35,37,43,45,46,47)
CMOS_CLEAR# (26)
H_A20GATE (37)
H_FERR# (7)
H_RCIN# (37)
PM_THRMTRIP# (7,11)
CLK_PCIE_SATA (18)
SATA_RXP0(27) SATA_RXN0(27)
CLK_PCIE_SATA# (18)
SATA_RXP1(27) SATA_RXN1(27)
LPC_FRAME# (29,37)
H_A20M# (7)
H_DPRSTP# (7,11,47)
H_DPSLP# (7)
H_PWRGD (7)
H_IGNNE# (7)
H_INIT#_R
H_INTR (7)
H_SMI# (7)
H_NMI (7)
H_STPCLK# (7)
SATA_LED#(26,30)
H_INIT# (7)
SATA_TXP0(27) SATA_TXN0(27)
SATA_TXN1(27) SATA_TXP1(27)
3VDDA(9,18,19,21,22,23,24,26,28,29,31,32,33,37,41,43,44,45)
3VDDA_LAN(18,33)
BIT_CLK_CODEC(35) BIT_CLK_MDC(28)
HDA_SDATAIN0(35) MDC_SDATAIN1(28)
MDC_SYNC(28) HDA_SYNC(35)
HDA_RST#(35) MDC_RST#(28)
MDC_SDATAOUT(28) HDA_SDATAOUT(35)
RTC_X1(18) RTC_X2(18)
CARD_RST#(32)
1.05VDDM
1.05VDDM
1.5VDDM
PMU3V
3VDDA_RTC
3VDDA_RTC
3VDDM
3VDDA_RTC
3VDDM
3VDDA
R402
20K 1%1/16WSMT0402 LR
RTCLAN / GLANIHDASATA LPCCPU
U25A
ICH9M REV 1.0
C23
C24
B22
C22
E25
C13
F14
G13
D14
D13
D12
E13
AF6
AH4
AE7
AF4
AG4
AH3
AG5
AG8
AJ16
AH16
AF17
AG17
AH13
AJ13
AG14
AF14
AH18
AJ18
AJ7
AH7
K5
K4
L6
K2
J3
J1
K3
N7
AJ27
AJ25
AE23
AJ26
AD22
AF25
AE22
AG25
L3
AF24
AF23
AH27
AG26
A25
B10
B27
B28
AE5
AG12
AH11
AF12
AJ11
AG27
AG7
AE8
A22
AH9
AJ9
AE10
AF10
F20
RTCX1
RTCX2
INTVRMEN
INTRUDER#
GLAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDOUT
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
LDRQ0#
LDRQ1#/GPIO23
FWH4/LFRAME#
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
CPUPWRGD
IGNNE#
INIT#
INTR
RCIN#
SMI#
NMI
STPCLK#
THRMTRIP#
RTCRST#
GLAN_DOCK#/GPIO56
GLAN_COMPO
GLAN_COMPI
HDA_SDIN3
SATA4TXN
SATA4RXN
SATA4TXP
SATA4RXP
TP8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
LAN100_SLP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SRTCRST#
R520
05%1/16W SMT0402 LR(NU)
R168 RES 24.9 1%1/16WSMT0402 LR
C69 0.01uF 16V10%SMT0603 X7R LR
CN24
CON HR A125WRA-S-02PSMD 2Pin P=1.25Wire H=3.5LR
20-20294-30
1
2
3
4
1
2
3
4
D32
DIODESTKY BAS40C 40V200mASOT-233PIN PSI LR
P PP
N
R403
20K 1%1/16WSMT0402 LR
R73
56 5%1/16WSMT0402 LR
R67 54.9 1%1/16W SMT0402 LR Sn
R404
100 5%1/16W SMT0402 LR
C419
0.1uF 16V80-20%0402 Y5VLR
RP3
RP33 5%SMT1010 1/16W 4P2R LR
1
24 3
GND
Y2
FREQ XTL 32.768KHz 12.5pF±10ppm DT-26 KDS LR
12
3
R398
1K 5%1/16W SMT0402 LR
C59 0.01uF 16V10%SMT0603 X7R LR
C160 12pF 50V5%SMT0402 NPO LR
C68 0.01uF 16V10%SMT0603 X7R LR
R72 56 5%1/16WSMT0402 LR
C428
1uF 10V+80-20%0603Y5V LR
RP4
RP33 5%SMT1010 1/16W 4P2R LR
1
24 3
R83 0 5%1/10W SMT0603 LR
C430
1uF 10V +80-20% 0603 Y5V LR
R516 10K 5%1/16WSMT0402 LR
T4
1
C67 0.01uF 16V10%SMT0603 X7R LR
R66
56 5%1/16W SMT0402 LR
C56 0.01uF 16V10%SMT0603 X7R LR
R524
332K1%1/16W 0603 LR
R401
1M 5%1/16WSMT0402 LR
C57 0.01uF 16V10%SMT0603 X7R LR
RP2
RP33 5%SMT1010 1/16W 4P2R LR
1
24 3
R77
10K 5%1/16WSMT0402 LR
R92 RES 33 5%1/16WSMT0402 LR
C429
1uF 10V +80-20% 0603 Y5V LR
C70 0.01uF 16V10%SMT0603 X7R LR
R512
05%1/16W SMT0402 LR(NU)
C163 12pF 50V5%SMT0402 NPO LR
R523
332K1%1/16W 0603 LR
C58 0.01uF 16V10%SMT0603 X7R LR
R78
RES 24.9 1%1/16WSMT0402 LR
R206
10M 1%1/10WSMT0603 LR
R7610K 5%1/16WSMT0402 LR
R71 SHW 0 5%1/16W 0402