DMA BANK SELECT OVERRIDE:
If DMA requests are, to override the bank select feature" turn ,switch
( 5 ON. If this' switch section is OFF, the board will not distinguish
b••.-~ween DMA transfers and HOST CPU transfers and the settings of the switches
discussed below do not affect the operation oJ ,the OMNIRAM. The transfers will
proceed according to the current bank selection 'status. If S2-5 is ON the two
sections of the OMNIRAM can be set to be active or inactive during DMA tran-
sfers regardless of the current bank selection status. If S2-6 is ON, the
high section of the board is enabled during DMA transfers, if S2-6 is OFF, the
high section is disabled during DMA transfers. If S2-7 is ON, the low section
of the board is enabled during DMA transfers, if S2-7 is OFF, the low section
is disabled during DMA transfers.
THEORY OF OPERATION:
Because the OMNIRAM is a static memory which does not require refresh
cycles to preserve the contents of the memory, its operation is simple and
straightforward. A board select signal is generated by the 8-bit comparator
U21 which accepts inputs from sOUT, PHANTOM*, sINP, sINTA, the extended
addressing circuitry, and from the bank select circuitry. Jumpers are
provided to disable several of these inplits if required. If the 16-bit
transfer option jumpers have been installed, the board will respond to a 16-
bit transfer request by pulling S-IOO buss line 60 (SIXTN*), low to indicate to
the host processer that the board is capable of making a 16-bit transfer. Note
that if the board receives a 16-bit transfer request on an odd address
boundary, it will not acknowledge the request on line 60 (SIXTN*). The INTEL
S6 will not make such a request.
~The OMNIRAM has two internal data busses. All of the memory chips
which are addressed when AO is true are connected to one bus while those chips
which are addressed when AO is false are connected to another bus.
A bipolar prom U22 receives as inputs board select, 16-bit transfer
request, AO, AIS, and sMEMR. This prom arranges the internal data busses of
the OMNIRAM as required by the type of transfer. The contents of this prom
are shown on page 7. If the request is for a 16-bit transfer the cross link
between on the internal data busses U8 is disabled and the two bi-directional
buffers to the S-IOO data bus are enabled. The chip-select/output enable pins
of the appropriate memory chips are activated by the four three-line-to-eight-
line decoders Ul, U2, U9, and UIO. If 8-bit transfers are requested, the
internal bus cross connect U8 is activated as required. Bus contention glit-
ches are avoided by enabling the S-IOO bus buffers U19 and U20 only after the
internal bus connections have been established. This is possible because
sMEMR which determines whether or not the cycle is to be a READ or a WRITE is
established before pDBIN/MWRT is asserted.
Output to the bank select 10 port is recognized by address comparitor
U3 in combination with sOUT and pWR*. This signal generates a clock input to
two sections of the latch US. The state of data input to the two sections of
US is determined by whether or not a TRUE logic level exists on any line of
the 8-100 data bus which is connected to the input of the two 8-input positive
n~nd gates U6 and U7 via a closed bank select switch. If this is so, the
tch assumes an active or selected state. Switch options are provided to set
~
S
