Fulcrum OMNIRAM User manual

·:."
OMNIRAM Manual Version 1.11
O~~IRAM INTRODUCTION:
The Fulcrum Computer Products OMNIRAM for the IEEE 696/S-100 bus
provides 64 kilobytes of fast static random access me~ory. provision is made
for 80r 16-bit trans~ers, extended 24-bit addressing, and for control via the
bus phantom line. In addition, a number.of features are included to make the
OMNIRAM compatihle ·with systems designed before the IEEE-696 standard was
developed. These include bank selection and provision for operation with
IMSAI-type front panels. When the bank select option is activated, the board
is divided into two parts which can reside in separate banks.The division of
the board may be into two 32K sections or into one 16K section and one 48K
gection. provision' is made for bMA overide of bank ~elect if needed. The
board is also compatible with IMSAI-type extended addressing.
In the option selection sections which follow, the board is viewed
from the component side. The edge opposite to the 100 pin S-lOO bus connector
is called the top and is so illustrated in all figures. All of the 8 sec-
tions of the dip switches are numbered from the top down, i.e. Sl-l is the
section of Sl closest to the top of the card. Shorting of pin jumpers is
accomplished with the shorting plugs supplied with the OMNIRAM.. The symbol
which appears in the following sections indicates that the two pins
are shorted by one of the plugs.
EXTENDED.ADDRESSING OPTION:
To enable 24-bit extended
addressing short the two upper pins in
jumper area G. To disable extended
'addressing short the lower top pins in
jumper area G. One or the other of
these two options MUST·be selected. If
extended addressing is selected, the 8
section dip switch S5 is used to select
the extended address of the OMNIRAM.
A16 is selected by section S5-1 while
A23 is selected by section S5-8. If a
switch section is ON (closed) logical
address 0 has been selected for that
address line. For example, to set the
address of the OMNIRAM to OlOOOOH, all
of the sections ofS5 should be in the
ON position except for S5-1 which should
be OFF.
1
G
[J
G
enabled
disabled
I

PHANTOM-IM8AI A16 OPTION:
To make the OMNIRAM respond to
the phantom line, short the lower-right
two pins in jumper area C (between U12
and U13). If this option is selected,
pulling the phantom line low will
disable the OMNIRAM. To enable IMSAI-
type extended address line A16 short the
two middle pins in jumper area C. To
disable control by the phantom or IMSAI-
type extended addressing short the
upper-right two pins in jumper area C.
One of these three options MUST be
selected for the OMNIRAM to function
correctly.
8/16 BIT TRANSFERS:
phantom enabled
IMSAI-A16 enabled
option diabled
If this option is selected the
OMNIRAM will respond to a sixteen bit
transfer request on S-lOO bus line 58 by
pulling 8-100 bus line 60 low and by
reading or writing a sixteen bit word
via the data bus lines. The pins in
jumper area D and E are used to select
this option. To select 16-bit transfers
short the two pins in jumper area D and
short the right two pins in jumper area
E. 8-bit transfers in 16-bit systems
may be forced by setting the jumpers as
required for 8-bit systems. This option
may be used to test by timing programs
that 16-bit transfers are taking place.
pDBIN/sMEMR OPTIONS:
E:::::!J
8-bit transfers
DE
.8-bit systems
~~[]
16-bit transfers
D16-bit syste'''\
£:::::J
8-bit transfers
DE . 16-bit systems
This option is selected in
jumper area F. The sMEMR option should
be chosen. This is accomplished by
shorting the upper two pins in the
jumper area.
2
normal position

32K/64K BOARD OPTION:
Although the OMNIRAM is normally
?lied as a 64K board, it may be
desirable under certain circumstances to
use only'32K of the board. The normal
64K configuration is activated by
shorting the outer-most pairs of pins in
jumper area H. If the 32K option is
selected short the second and third pins
from the top in area H. The address of
the board will be determined by shorting
or not shorting the lower two pins in
that area. If these pins are shorted
the lowest address of the OMNIRAM will
be OOOOH. If they are open, the lowest
address will be 8000H. One of these
options MUST be selected for the OMNIRAM
to function correctly.
FRONT PANEL OPTION:
H
q
1]
H
8
H
64K Option (normal)
32K Option (OOOOH)
32K Option (8000H)
To enable the IMSAI front panel
to write into the OMNIRAM from the front
panel switches, short the left two pins
in jumper area A. To disable this
ction short the right two pins in
Ct_-.:aA. The IMSAI front panel will read
the contents of the OMNIRAM even if this
option is disabled. It is recommended
that this function be disabled if
operation of the front panel is not
required.
~. front panel enabled
A
. E::!1 front panel disabled
A
BANK SELECT OPTION:
To enable bank select-type
extended addressing via an 10 port short
the right two pins in jumper area B. To
disable ALL bank select functions, short
the left two pins in jumper area B. One
or the other of these options MUST be
selected. If the bank select option is
disabled, none of the bank-select switch
settings have any effect on the
operation of the OMNIRAM. If the bank
select option is not desired,integrated
circuits U3,U4,U5,U6,U7, and Ul8 may be
removed. This will reduce the power
c~qsumed by the OMNIRAM.
3
. £::3 Bbank select enabled
bank select disabled

BANK SELECT PORT:
The 10 port address of the bank select function is chosen by dip
switch Sl. The position of switch section Sl-l determines the least signi-
fiant address of the the bank select port while Sl-8 determines the most
significant address. If a switch is ON (closed), logical value 0 is selected.
For example, a common bank select 10 port is 40H. To select this port, turn
ON sections 1,2,3,4,5,6, and 8 of switch Sl and turn OFF section 7.
BANK OCCUPANCY:
The OMNIRAM is divided into two sections, a HIGH ADDRESS section and a
LOW ADDRESS section. The high address section is 32K in length extending from
8000H to FFFFH if switch section S2-8 is ON. The section is 16K in length of
switch S2-8 is OFF. The low address section occupies the portion of the
address space not occupied by the high address sectin.
The banks in which the low address section is located are selected by
switch S4. Bank-O is selected by turning ON switch section S4-1. Bank-7 is
selected by turning ON switch section S4-8. A section of the OMNIRAM may
reside in more than one bank. This is accomplished by turning ON more than one
section of switch S4 at one time.
The banks in which the high address section is located are selecte~y
switch S3. The operation of this switch is similar to that of switch S4.
BANK ACTIVATION:
The two sections of the OMNIRAM can be reset to ACTIVE or DISABLED on
power-on or reset. The following table illustrates the options:
S2-1
S2-2S2-3S2-4
Both sections DISABLED on reset: ON
ONOFFOFF
Low section ENABLED, high section DISABLED:
OFF
ONONOFF
High section ENABLED, low section DISABLED:ON
OFFOFFON
Both sections ENABLED on reset: OFF
OFF
ON
ON
Only those combinations of the switch settings shown in the above
table should be used. Many 8-bit systems execute an automatic jump to a PROM
at a high address such as OCOOOH on reset or power-on. The disk boot routine
will automatically activate the high bank on execution. For such systems, the
LOW SECTION ENABLED, HIGH SECTION DISABLED option should be selected. The high
bank is usually set to reside in bank-O.
4

DMA BANK SELECT OVERRIDE:
If DMA requests are, to override the bank select feature" turn ,switch
( 5 ON. If this' switch section is OFF, the board will not distinguish
b••.-~ween DMA transfers and HOST CPU transfers and the settings of the switches
discussed below do not affect the operation oJ ,the OMNIRAM. The transfers will
proceed according to the current bank selection 'status. If S2-5 is ON the two
sections of the OMNIRAM can be set to be active or inactive during DMA tran-
sfers regardless of the current bank selection status. If S2-6 is ON, the
high section of the board is enabled during DMA transfers, if S2-6 is OFF, the
high section is disabled during DMA transfers. If S2-7 is ON, the low section
of the board is enabled during DMA transfers, if S2-7 is OFF, the low section
is disabled during DMA transfers.
THEORY OF OPERATION:
Because the OMNIRAM is a static memory which does not require refresh
cycles to preserve the contents of the memory, its operation is simple and
straightforward. A board select signal is generated by the 8-bit comparator
U21 which accepts inputs from sOUT, PHANTOM*, sINP, sINTA, the extended
addressing circuitry, and from the bank select circuitry. Jumpers are
provided to disable several of these inplits if required. If the 16-bit
transfer option jumpers have been installed, the board will respond to a 16-
bit transfer request by pulling S-IOO buss line 60 (SIXTN*), low to indicate to
the host processer that the board is capable of making a 16-bit transfer. Note
that if the board receives a 16-bit transfer request on an odd address
boundary, it will not acknowledge the request on line 60 (SIXTN*). The INTEL
S6 will not make such a request.
~The OMNIRAM has two internal data busses. All of the memory chips
which are addressed when AO is true are connected to one bus while those chips
which are addressed when AO is false are connected to another bus.
A bipolar prom U22 receives as inputs board select, 16-bit transfer
request, AO, AIS, and sMEMR. This prom arranges the internal data busses of
the OMNIRAM as required by the type of transfer. The contents of this prom
are shown on page 7. If the request is for a 16-bit transfer the cross link
between on the internal data busses U8 is disabled and the two bi-directional
buffers to the S-IOO data bus are enabled. The chip-select/output enable pins
of the appropriate memory chips are activated by the four three-line-to-eight-
line decoders Ul, U2, U9, and UIO. If 8-bit transfers are requested, the
internal bus cross connect U8 is activated as required. Bus contention glit-
ches are avoided by enabling the S-IOO bus buffers U19 and U20 only after the
internal bus connections have been established. This is possible because
sMEMR which determines whether or not the cycle is to be a READ or a WRITE is
established before pDBIN/MWRT is asserted.
Output to the bank select 10 port is recognized by address comparitor
U3 in combination with sOUT and pWR*. This signal generates a clock input to
two sections of the latch US. The state of data input to the two sections of
US is determined by whether or not a TRUE logic level exists on any line of
the 8-100 data bus which is connected to the input of the two 8-input positive
n~nd gates U6 and U7 via a closed bank select switch. If this is so, the
tch assumes an active or selected state. Switch options are provided to set
~
S

the two bank sel~~t 19t~he~ tQ the active or inactive state when POC* or
RESET* are active. A bipolar prom U4 takes inputs from the two bank select
latches, A15, A14,PHLDA, and three sections of switch S3. These input~re
used to provide a bank select qualifier to the board select comparitor U~
Use caution when removing the memory chips frcm their sockets. CMOS
parts are susceptible to damage from static electricity.
MEMORY CHIP LOCATIONS ON THE OMNIRAM BOARD
(FACE COMPONENT SIDE OF BOARD)
3 2 1 A 8 BCD E F 1 D B C
EEEEEEEEEE0000
54090 2 346 7 5 A 9 8
EEEE00000a0 000
6 7 F E
E E 0 0
EVEN (E) MEANS AO =0 ON BYTE TRANSFERS
ODD (0) MEANS AO = 1 ON BYTE TRANSFERS
6

U22 ROM FOR THE OMNIRAM 64K MEMORY BOARD
-ADDRESS- +-----DATA------ + --------FUNCTION/COMMENTS-----------------+
E D C B A ~ 8 7 6 5 4 3 2 1 ~ (BUS MASTER'S POINT OF VIEW)
----------+-----------------+------------------------~------------------+
B A 1 A S ~ D E C DOE D 0 ~
S06 1 M ~ 0 V RID V I D ~
*0 5 E ~ E NOR D NED ~
K M ~ N H S L L N H ~
R ~ *ISO 0 *I ~
~ * * * ~
----------+-----------------+-------------------------------------------+
o0000~011101 1 1 ~ BYTE-WRITE-EVEN-LOW-
o0001 ~ 1 1 0 0 0 101 ~ BYTE-READ--EVEN-LOW-
o0 0 10~001 1 0 0 1 1 ~ BYTE-WRITE-EVEN-HIGH
o0 0 1 1 ~ 1 0000001 ~ BYTE-READ--EVEN-HIGH
o010 0 ~ 0 1111101 ~ WORD-WRITE-EVEN-LOW-
o0101 ~ 01 1 01 1 01 ~ WORD-READ--EVEN-LOW-
o01 1 0 ~ 0 0 1 1 0000~ WORD-WRITE-EVEN-HIGH
o0111~0 0 10 0 0 0 0 ~ WORD-READ--EVEN-HIGH
o10 0 0 ~ 0 101 1 01 1 ~ BYTE-WRITE-ODD--LOW-
o10 0 1 ~ 1 1 1 010 0 1 ~ BYTE-READ--ODD--LOW-
o1010~01010 0 10 ~ BYTE-WRITE-ODD--HIGH
o101 1 ~ 1 1 1 0 0 0 0 0 ~ BYTE-READ--ODD--HIGH
o1 1 0 0 ~ 11110 0 1 1 ~ WORD-WRITE-ODD--LOW- (NO RESPONSE)
, 1 01 ~ 1 1 1 1 0 0 1 1 ~ WORD-READ--ODD--LOW- (NO RESPONSE)
~_L 1 1 0 ~ 1 1 1 1 0 0 1 1 ~ WORD-WRITE-ODD--HIGH (NO RESPONSE)
o1 1 1 1 ~ 1 1 1 1 0 0 1 1 ~ WORD-READ--ODD--HIGH (NO RESPONSE)
----------+-----------------+-------------------------------------------+
10000~11110 0 1 1 ~ NO RESPONSE
10001~11110 0 1 1 ~ NO RESPONSE
10 0 10 ~ 11110 0 1 1 ~ NO RESPONSE
10 0 1 1 ~ 1 1 1 1 0 0 1 1 ~ NO RESPONSE
1-0 100~11110 0 1 1 ~ NO RESPONSE
10101~11110 0 1 1 ~ NO RESPONSE
101 1 0 ~ 11110 0 1 1 ~ NO RESPONSE
10 III ~ 11110 0 1 1 ~ NO RESPONSE
1 1 000~11110 0 1 1 ~ NO RESPONSE
1 1 0 0 1~11110 0 1 1 ~ NO RESPONSE
1 1 010 ~ 11110 0 1 1 ~ NO RESPONSE
1 1 011~11110 0 1 1 ~ NO RESPONSE
1 1 1 00~11110 0 1 1 ~ NO RESPONSE
11101 ~ 1 1 1 1 0 0 1 1 ~ NO RESPONSE
11110 ~ 11110 0 1 1 ~ NO RESPONSE
1 1 1 1 1 ~ 1 1 1 1 0 0 1 1 ~ NO RESPONSE
----------+-----------------+-------------------------------------------+
7

For
use
with CROMEMCO CD08 and CROMIX operating systems
the
jumper
area connections are the same. These are as follows:
·ll .
[J
AD· B
.c:JC
D
.
.Et:::::J
Fz::::::::J
GlJ
H .
D
8witch settings for the CD08 system are as follows
(X=either) :
81
82838485
1
ONOFFONONX
2ONON
ONON
X
3ON
ONONONX
4ON
OFFONONX
5ON
OFFONONX
6ON
ON
ON
ON
X
7OFF
ONONON
X
8ON
ON
ON
ONX
/~
8witch settings for the system bank in a one user CROMIX system are as
follows (X=e:ither):
81
82838485
1
ONOFF
ONON
X
2ON
ON
OFFOFFX
3ON
ONON
ON
X
4ON
OFF
ON
ONX
5ONOFF
ON
ONX
6ON
ONONON
X
7OFF
ONONONX
8ON
ONON
ONX
8

If the omniram is to be used with the Seattle Computer Products l6-bit
8086 system the OMNIRAM jumper areas should be connected as follows:
A • E:::J BE::J . C • (J D\. ~I C1
H •
[J
The switch settings are given below.
The address of the board in this
illustration begins at 00000 (X=either position).
81
82
8384
S5
1
ON
X
X
XX
2ON
XX
XX
3ON
XX
XX
4ON
X
X
X
X
5ONX
X
XX
6ON
XXXX
7ON
XXXX
8ONX
X
XX
9

If the OMNIRAM is to be used with the IMSAI MPU-B (8085)
system without front panel the jumper settings are as follows:
If the OMNIRAM is to be used with the IMSAI
front panel the jumper settings are as follows:
FG::::i:J G[]
[J
H .
[J
MPUA-A
(8080)
system
with
D .
D . []
H .
[]
ALL switch settings are inoperative when using IMSAI protocal
phantom. (A-16)
10

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Col1n1dio"s COM ,",on
to 0.11 581eS'j. FULCRUM (EUROPE)
VALLEY HOUSE
PURLEIGH
ESSEX, ENGLAND CM3 6QH
TELEPHONE~ [phone]
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27014
REV. o
12 11 10 9