GENNUM EB-GS2972 User manual

EB-GS2972
Evaluation Board User Guide
1 of 22
EB-GS2972 www.gennum.com
Evaluation Board User Guide
50283 - 2 May 2012

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012
2 of 22
Contents
Overview ..............................................................................................................................................................3
1. Board User Guide ..........................................................................................................................................5
1.1 Power (J1) ............................................................................................................................................5
1.2 Switch Settings (SW6 & SW7) .......................................................................................................5
1.3 Inputs ....................................................................................................................................................7
1.3.1 Audio Input.............................................................................................................................7
1.3.2 Parallel Video Input .............................................................................................................7
1.4 SDI Outputs (J3 and J4) ...................................................................................................................7
1.5 Control and Status ............................................................................................................................8
1.5.1 GSPI Header (JP8) .................................................................................................................8
1.5.2 JTAG Header (JP1) ................................................................................................................8
1.5.3 Lock Status..............................................................................................................................8
1.6 Modes of Operation .........................................................................................................................8
2. Board Schematics ..........................................................................................................................................9
2.1 Top Level Schematic ........................................................................................................................9
2.2 Audio Input Schematic ................................................................................................................ 10
2.3 GS2972 Schematic ......................................................................................................................... 11
2.4 Power Schematic ........................................................................................................................... 12
3. Board Layout................................................................................................................................................ 13
4. Bill of Materials............................................................................................................................................ 19
Version ECR Date Changes and / or Modifications
2 158067 May 2012 Changed R14 value from 380Ωto 200Ω.
Also, changed mistake in 1.5.2 JTAG
Header (JP1) section.
1 151327 January 2009 Updates to Board Layout figures.
0 149901 June 2008 New document.

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Overview
Together with the EB-GS2972 Evaluation Board, this document serves as a guide for
evaluating the GS2972, a Gennum 3Gb/s, HD, SD SDI Transmitter. This document
contains four main sections:
1. Evaluation Board User Guide.
2. Evaluation Board Schematics.
3. Evaluation Board Layout.
4. Evaluation Board Bill of Materials.
The figure below shows a block diagram of the features and the functions of the
EB-GS2972.
The board includes a power supply, 2 SDI output ports, a GS2972 Transmitter, a parallel
video input connector, an audio input with four BNCs for AES audio, an optional
four-pin header for serial audio, an audio conditioning block, a JTAG/GSPI header, a dip
switch and some status indicator LEDs.
The GS2972 can be configured in SD-SDI, HD-SDI, 3G-SDI or DVB-ASI mode. This may
be selected manually through a DIP switch. The serialized video is available on the SDI
output BNC connectors.
The EB-GS2972 also provides a JTAG interface and access to the GS2972’s internal
registers via GSPI and USB. A GSPI dongle is included in the kit, to communicate with the
GS2972 and Sample Rate Converters (SRCs) through a USB connection.The GSPI dongle
has the provision to control and monitor an additional EB-GS2970 board connected to
the EB-GS2972.

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Block Diagram of the EB-GS2972
GS2972
(Transmitter)
Power
SDO
SDO
3G-SDI
3G-SDI
20-bit Video
PCLK
LED’s
FVH
GSPI
7
GSPI Header
Audio
DIP Switch
AES (x4)
Serial Audio
Group 2
4

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1. Board User Guide
Figure 1-1 shows the inputs, outputs and power connections for the EB-GS2972.
Figure 1-1: GS2972 Evaluation Board (EB-GS2972)
1.1 Power (J1)
The EB-GS2972 requires a single +5V DC power supply. The board is powered through
J1.
LED (D7) indicates the power on/off state of the board.
Through the use of JP7, the user can select the I/O voltage to be either 1.8V or 3.3V.
If the EB-GS2972 and the EB-GS2970 are connected together, one supply will power
both boards. Therefore, the +5V DC power is only required on either the EB-GS2972 or
the EB-GS2970.
1.2 Switch Settings (SW6 & SW7)
DIP switches (SW6 and SW7) are populated on the board with each bit labelled on the
silk-screen. They are used to set the operation mode of GS2972.
Power Supply Connector (J1)
DIP Switches (SW6& SW7)
Audio Input Group One
(AES 1/J13 & AES 2/J14)
Audio Input Group Two
(AES 2/J115 & AES 2/J16)
Parallel Video Input
Connector (J25)
H, V & F TimingSignals
Connector (J27)
GSPI Header (JP8)
JTAGHeader (JP1)
Lock Status LED (U25)
SDI Outputs (J3 & J4)
1.8V/3.3V Jumper (JP7)
Power Status LED (D7)
GSPI Connector for Interface
with the GS2970 Receiver (J29)
Serial Audio Input (Group Two)

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NOTE: Some signals are active LOW so that you will need to switch the bit OFF to
activate the signal.
Refer to the GS2972 Data Sheet for definitions of each bit.
Table 1-1: SW6 and SW7 Settings
Bit Name Description
TIM861
(SW6)
Connected to the GS2972 TIM_861 pin. Used to select external CEA-861 timing mode.
When DETECT_TRSis LOW and TIM-861 is LOW, the device extracts all internal timing from the supplied H:V:F
timing signals. When DETECT_TRSis LOW and TIM-861 is HIGH, the device extracts all internal timing from the
supplied HSYNC, VSYNC, DE timing signals.
When DETECT_TRSis HIGH, the device extracts all internal timing from TRSsignals embedded in the supplied
video stream.
SMPTE_BYPASSn
(SW6)
Connected to the GS2972 SMPTE_BYPASS pin. Used to enable/disable all forms of encoding/decoding,
scrambling and EDH insertion.
When set LOW, the device operates in Data Through mode (DVB_ASI= LOW), or in DVB_ASI mode (DVB_ASI =
HIGH). No SMPTE scrambling takes place and none of the I/O processing features of the device are available
when SMPTE_BYPASS is set LOW.
When set HIGH, the device carries out SMPTE scrambling and I/O processing.
DVB_ASI
(SW6)
Connected to the GS2972 DVB_ASI pin. Used to enable/disable the DVB-ASI data transmission.
When set HIGH, the device will carry out DVB_ASI, word-alignment, I/O processing and transmission. The
SMPTE_BYPASS pin must be set LOW.
When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in data-through mode.
RATE_SEL0,
RATE_SEL1
(SW6)
Connected to the GS2972 RATE_SEL0 and RATE_SEL1 pins. Used to configure the operating data rate.
IOPROC_EN/DISn
(SW6)
Connected to the GS2972 IOPROC_EN/DISpin. When IOPROC_EN/DISis HIGH, the I/O processing features of the
device are enabled. When IOPROC_EN/DISis LOW, the I/O processing features of the device are disabled. Only
applicable in SMPTE mode.
20bit/10bitn
(SW6)
Connected to the GS2972 20bit/10bit pin. Used to select the input bus width.
SDO_EN/DISn
(SW6)
Connected to the GS2972 SDO_EN/DISpin. Used to enable or disable the serial digital output stage.
When SDO_EN/DISis LOW, the serial digital output signals SDO and SDO are disabled and become
high-impedance.
When SDO_EN/DISis HIGH, the serial digital output signals SDO and SDO are enabled.
DETECT_TRS
(SW7)
Connected to the GS2972 DETECT_TRSpin. Used to select external HVF timing mode or TRSextraction timing
mode.
When DETECT_TRSis LOW, the device extracts all internal timing from the supplied H:V:F or CEA-861 timing
signals, dependent on the status of the TIM861 pin. When DETECT_TRSis HIGH, the device extracts all internal
timing from TRSsignals embedded in the supplied video stream.
RATE_SEL0 Data Rate
0
0
1
0
1
X
1.485 or 1.485/1.001Gb/s
2.97 or 2.97/1.001Gb/s
270Mb/s
RATE_SEL1

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1.3 Inputs
1.3.1 Audio Input
Up to 8 channels of audio are supported by the EB-GS2972.
Group One (AES 1/J13 and AES 2/J14) goes to SRCs. Through the software, the SRC can
be programmed to output AES or serial (synchronous or asynchronous) audio signals to
the GS2972. The master clock for the SRCs is supplied by the GS4911B on the
EB-GS2972.
Group Two can be connected directly to the GS2972 as AES (AES 3/J15 and AES 4/J16)
or serial audio (Header J30). In the case where synchronous audio is required, external
synchronization must be applied. This configuration is meant to allow users to have the
capability of evaluating audio embedding. For SD audio, when embedding audio with
both groups, the audio needs to be synchronized externally.
1.3.2 Parallel Video Input
The EB-GS2972 has a 48-pin parallel connector for the serialized video input (J25). The
video input includes the 20-bit video data and pixel clock.
The related timing signals (F,V,H) are on the 10-bit parallel connector (J27).
1.4 SDI Outputs (J3 and J4)
The EB-GS2972 includes two SDI outputs on J3 and J4.
ANC_BLANKn
(SW7)
Connected to the GS2972 ANC_BLANK pin.
When ANC_BLANK is LOW, the Luma and Chroma input data is set to the appropriate blanking levels during the
H and V blanking intervals.
When ANC_BLANK is HIGH, the Luma and Chroma data pass through the device unaltered. Only applicable in
SMPTE mode.
GRP1_EN/DISn
(SW7)
Connected to the GS2972 GRP1_EN/DISpin. Enable Input for Audio Group 1. Set HIGH to enable.
GRP2_EN/DISn
(SW7)
Connected to the GS2972 GRP2_EN/DISpin. Enable Input for Audio Group 2. Set HIGH to enable.
STANDBY
(SW7)
Connected to the GS2972 STANDBY pin. HIGH to power-down device.
NOTE: Cable Driver is not powered down.
JTAG_HOSTn
(SW7)
Connected to the GS2972 JTAG/HOSTpin. Used to select JTAG test mode or Host Interface mode.
When JTAG/HOSTis HIGH, the Host Interface port is configured for JTAG test.
When JTAG/HOSTis LOW, normal operation of the Host Interface port resumes and the separate JTAG pins
become the JTAG port (JP1).
Table 1-1: SW6 and SW7 Settings
Bit Name Description

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1.5 Control and Status
1.5.1 GSPI Header (JP8)
The GS2972 contains a set of internal status and configuration registers. These registers
are available to the host via the GS2972s GSPI pins. To communicate with the GS2972
and the two SRCs, a Gennum USB to GSPI dongle must be connected to the GSPI header.
A GSPI dongle is provided for communication to the GSPI interface. If you have the
EB-GS2972 and the EB-GS2970 connected together, only one GSPI dongle is required,
and can be connected to either of the boards. On the EB-GS2972, connector J29 provides
interface with the EB-GS2970.
1.5.2 JTAG Header (JP1)
This header is used for the JTAG test of the GS2972. It can also be used to communicate
with the GSPI interface of the GS4911B to program the part. To change this header to the
GS4911B GSPI interface, populate R115 and R113 with 0Ω, and unpopulate R114 and
R22. However, under normal conditions, the GS4911B will not need to be programmed.
1.5.3 Lock Status
LED U25 indicates the lock status of the GS2972.
1.6 Modes of Operation
The GS2972 supports four distinct modes of operation that can be set through the DIP
switch or by programming internal registers through the GSPI. These modes are: SMPTE
mode, Data-Through mode, DVB-ASI mode and Standby mode.
In SMPTE mode, the GS2972 performs all SMPTE processing features. Both SMPTE 425M
Level A and Level B formats are supported with optional conversion from Level A to
Level B for 1080p 50/60 4:2:2 10-bit.
In DVB-ASI mode, the device will perform 8b/10b encoding prior to transmission.
In Data-Through mode, all SMPTE and DVB-ASI processing is disabled. The device can
be used as a simple parallel to serial converter.
The device can also operate in a lower power Standby mode. In this mode, no signal is
generated at the output.
The DIP switches (SW6 and SW7) correspond directly to pins on the GS2972. Refer to the
GS2972 Data Sheet for a more detailed explanation of the operation of these pins in each
mode.

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2. Board Schematics 2.1 Top Level Schematic Figure 2-1: Top Level Schematic
TCK1
GND
2
TDO 3
VDD
4
TMS 5
NC
6
NC7
NC
8
TDI 9
GND
10
JP1
TSW-105-07-L-D
VCC_3.3V
C69 0.1u
IOVDD_2972
SD 1RATE_SEL0 X
TIM861
RATE_SEL1
SMPTE_BYPASSn DV B_A SI RAT E_SEL 0
S_AUDIO_1 GS2972_Audio1
0 0 HD
GND 2
RESET
1
MR
3
Vcc 5
WDI
4
U1
MAX6823V
ANC_BLANKn
0 1 3G
IOPROC_EN/DI Sn RAT E_SEL 1 20BIT /10BIT n DETECT_TRS SDO_EN/DISn
RATE_SEL1 Pin _ctrl8
IOPROC_EN/DISn Pin _ctrl7
SDO_EN/DISn Pin _ctrl5
1
3
2
J13BCJ-FPLV01
IOVDD_2972
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
RN1
T/R b0 2
A0 3 A1 4 A2 5 A3 6
T/R b3 7
T/R b2
10
B3
11 B2 12 B1 13 B0 14
T/R b1
15
VCCA1
VCCB16
GND
8
OEb
9
U17
FXL4TD 245
TIM861 Pin _ctrl12
GSPI_GS4911_2
RATE_SEL0 Pin _ctrl9
DVB_ASI Pin _ctrl10
SMPTE_BY PASSn Pin _ctrl11
GND
IOVDD_2972
R20 10K
IOVDD_2972
R21 10K
IOVDD_2972
R22 10K
JTAG/GSPI_GS4911
DETECT_TRS Pin _ctrl4
S_AUDIO_2 GS2972_Audio2
JTAG0
SDOUT SRC4382_SPI0
R102 75R
GND
GND
ANC_BLANKn Pin _ctrl3
R103 75R
AES 2
GND R104
75R
GNDGND
AES 3
GND
GS2972_GSPI3
R105 75R
GNDA_2972
AES 4
SDI Output
GND
AES 1
GND
1
3
2
J4 UCBBJE20-1
1
3
2
J3 UCBBJE20-1
GRP1_EN_DISn Pin _ctrl2
+SDO
GNDA_2972
-SDO
GSPI
GND
GND
R115 NP
CS2 CS1
JTAG/HOSTb
R80 10K R79 10K R78 10K
CS3
R77 10K
GS2972_GSPI2
GS2972_GSPI0
GS2972_GSPI1
GND
GRP2_EN_DISn Pin _ctrl1
STANDBY Pin _ctrl13
CS0
GND
Pin _ctrl0JTAG_HOSTn
S_AUDIO_3 GS2972_Audio3
Sch_GS2972 GS2972
SDO
SDOn
GS2972_PCLK GS2972_DIN[19:0] GS2972_HVF[2:0]
GS2972_Audio[7:0]
GS2972_RESETn
GS2972_Locked
Pin _ctrl[13:0]
JTAG[3:0]
GS2972_GSPI[3:0]
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
RN2
PCLK_GS4911
Sch_Audio_In Audio_In
AES_IN1_2 AES_IN3_4 AES_IN5_6 AES_IN7_8
S_AUDIO_[3:0]
GS2972_AES5_6 GS2972_AES7_8
Audio_RST HVF_IN[2:0] SRC4382_SPI[4:0]
PCLK_GS4911
GSPI_GS4911_[3:0]
12 34 56 78 910
JP8
TSW-105-07-L-D
Sch_Power
Power
CS1
GND
R107 1.15K
PCLK_IN
GSPI_GS4911_2
GSPI_GS4911_3TCK
GSPI_GS4911_[3:0]
GSPI_GS4911_0 GSPI_GS4911_1TMS
R1140R
TDI
R108
0R
SDIN SRC4382_SPI1
GS2972_Audio7 GS2972_Audio6
WCLK_connGS2972_Audio5 ACLK_connGS2972_Audio4
GND GND
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47
J25
SQT-124-01-F-D-RA
PCLK
FEMA L E: TOP- SIDE
2 4 6 8 10
1 3 5 7 9
J27
SQT-105-01-F-D-RA
FEMA L E: TOP- SIDE
VGS2972_HVF1
GND
HGS2972_HVF0
IOVDD_2972
GS2972_DIN2 GS2972_DIN1 GS2972_DIN0
PCLK_IN
GS2972_DIN6 GS2972_DIN5 GS2972_DIN7 GS2972_DIN4 GS2972_DIN3
GS2972_DIN17 GS2972_DIN12 GS2972_DIN11
GS2972_DIN8 GS2972_DIN9
GS2972_DIN10 GS2972_DIN19 GS2972_DIN15 GS2972_DIN16 GS2972_DIN18 GS2972_DIN14
Pin _ctrl[13:0]
SDIN SCLK SDOUT
GS2972_DIN13
2 4 6 8 10
1 3 5 7 9
J29
SQT-105-01-F-D-RA
FEMA L E: TOP- SIDE
CS1
CS3 CS2
R106NP
GS2972_GSPI[3:0]
TMS
GND
JTAG2
OPEN
CLOSED 0
1
0
1
SW6
SW8_LOGIC_DIP_TH
S_AUDIO_[3:0]
OPEN
CLOSED 0
1
0
SW7 SW6_LOGIC_DIP_TH
R113NP
RST
CS0
SCLK
1
3
2
J14 BCJ-FPLV01
TDO
FGS2972_HVF2
20BIT/10BITn Pin _ctrl6
P.O. Box 489, Station A
Pin _ctrl0
STANDBY
SDIN
GND
R109 NP
GRP1_EN_DISn GRP2_EN_DISn ST A NDBY
VCC_3.3V
SCLK SRC4382_SPI2
CS1
JTAG_HOSTn
Lock
A1 green
1
A2 red
2
K1 3 K2 4
U25
HSMF-C165
R101 75R
GND
R112 0R
GS2972_Audio[7:0]
GS2972_DIN[19:0]
VCC_5V
TCK
GS2972_HVF[2:0]
RESET
IOVDD_2972
SDOUT
GND
1
3
2
J16
BCJ-FPLV01
1 2 3 4
J304 HEADER
IOVDD_2972
VCC_3.3V
JTAG3
CS2 SRC4382_SPI3
SRC4382_SPI[4:0]
JTAG[3:0]
JTAG1
GND GND
S1
B3S-1002
RESET
PCLK_GS4911
S_AUDIO_0 GS2972_Audio0
GND
RESET
CS3 SRC4382_SPI4
RESET
GS2972_Audio6
GSPI_GS4911_[3:0]
GND
VCCA1
VCCB10
A0 2 A1 3
TR0 4 TR1 6
GND
5
OEb
7
B0
9
B1
8
U28 FXL2TD245
VCC_3.3V
IOVDD_2972
GND
GS2972_Audio7
GS2972_HVF[2:0]
TDO
1
3
2
J15BCJ-FPLV01
500R500R

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2.2 Audio Input Schematic
Figure 2-2: Audio Input Schematics
AES_IN3_4
Master clock for SRC
GND
Audio_RST
IO_V_SRC4382
Audio_RST
slow_48k
SRC4382_SPI0
TP16
GSPI_GS4911_3
ACLK_GS4911
Audio_RST
SRC4382_SPI1
Audio outputs andSPI
TP17
GND
SRC4382_SPI2
R86
1.15K
3V3_SRC4382
GND
GSPI_GS4911_2
SRC4382_SPI3
ACLK_GS4911
SRC4382_SPI3
AES3_4_SRC4382
C122 0.1u
C148 0.1u
GND
GND
Gr2_AES_Ser
Part R ef erence
105R
GND
AES1_2_SRC4382
C143
0.1u
C144
0.1u
A
3
B
4
R5
GND
2
Vcc
1
110R
U10
SN65LVDT2
VCC_3.3V
GND
GND GND
GSPI_GS4911_1
Connect pin 44 to pin 10.
Pin 10 is then connectedto
the groundplane.
GND
GND
slow_48k
S_AUDIO_[3:0]
GND
GND
SRC4382_SPI2
GSPI_GS4911_0
3V3_SRC4382
PCLK_GS4911
S_AUDIO_2
1B1
3B2
S
6
GND
2
A4
5Vcc
U18
SN74LVC1G3157
IO_V_SRC4382
SRC4382_SPI4
SRC4382_SPI4
GND
GND
R111
105R
AES3_4_SRC4382
C146
0.1u
C145
0.1u
VCC_3.3V
GND
A
3
B
4
R5
GND
2
Vcc
1
110R
U11
SN65LVDT2
GND GND
GND
RX1+
1
RX1-
2
RX2+
3
RX2-
4
RX3+
5
RX3-
6
RX4+
7
RX4-
8
VCC
9
AGND
10
LOCKb
11
RXCKO
12
RXCKI
13
MUTE
14
RDYb
15
DGND1
16
VDD18
17
CPM
18
CSb
19
CCLK
20
CDIN
21
CDOUT
22
INTb
23
RSTb
24
MCLK 25
GPO1 26
GPO2 27
GPO3 28
GPO4 29
DGND2 30
TX- 31
TX+ 32
VDD33 33
AESOUT 34
BLS 35
SYNC36
BCKA 37
LRCKA 38
SDINA 39
SDOUTA 40
NC41
VIO 42
DGND3 43
BGND 44
SDOUTB 45
SDINB 46
LRCKB 47
BCKB 48
U26
SRC4382
GND
AES_IN5_6AES5_6
R92
105R
C126
0.1u
GND
C125
0.1u
A
3
B
4
R5
GND
2
Vcc
1
110R
U12
SN65LVDT2
GND GND
SRC4382_SPI2
VCCA1 VCCB10
A0 2
A1 3
TR0 4
TR1 6
GND
5
OEb
7
B0
9
B1
8
U24
FXL2TD245
GND
PCLK_GS4911
GSPI_GS4911_3
RX1+
1
RX1-
2
RX2+
3
RX2-
4
RX3+
5
RX3-
6
RX4+
7
RX4-
8
VCC
9
AGND
10
LOCKb
11
RXCKO
12
RXCKI
13
MUTE
14
RDYb
15
DGND1
16
VDD18
17
CPM
18
CSb
19
CCLK
20
CDIN
21
CDOUT
22
INTb
23
RSTb
24
MCLK 25
GPO1 26
GPO2 27
GPO3 28
GPO4 29
DGND2 30
TX- 31
TX+ 32
VDD33 33
AESOUT 34
BLS 35
SYNC36
BCKA 37
LRCKA 38
SDINA 39
SDOUTA 40
NC41
VIO 42
DGND3 43
BGND 44
SDOUTB 45
SDINB 46
LRCKB 47
BCKB 48
U27
SRC4382
AES_IN7_8
GND
S_AUDIO_0
AES7_8
R93
105R
C128
0.1u
C127
0.1u
VCC_3.3V
GND
A
3
B
4
R5
GND
2
Vcc
1
110R
U13
SN65LVDT2
GND GND
GND
SRC4382_SPI1
GND
1V8_SRC4382
S_AUDIO_1
GS2972_AES5_6
AES_IN1_2
S_AUDIO_2 GS2972_AES7_8
AES7_8
AES5_6
R88
1.15K
1V8_SRC4382
S_AUDIO_3
GSPI_GS4911_[3:0]
GS2972_AES5_6
GS4911_genlockb
HVF_IN[2:0]
SRC4382_SPI1
GS2972_AES5_6
GS2972_AES7_8
GS2972_AES7_8
1V8_SRC4382
SRC4382_SPI0
VCC_3.3V
S_AUDIO_0
Connect pin 44 to pin 10.
Pin 10 is then connectedto
the groundplane.
GSPI_GS4911_0
GSPI_GS4911_[3:0]
GSPI_GS4911_1
TP21
GND
IOVDD_2972
GSPI_GS4911_2
SRC4382_SPI[4:0]
S_AUDIO_0
SRC4382_SPI0
1V8_SRC4382
S_AUDIO_1
IO_V_SRC4382
SRC4382_SPI[4:0]
AES1_2_SRC4382
C1160.1u
SRCA
C147 0.1u
GND
1V8_Core_GS4911
Audio_RST
3V3_PLL_SRC4382_A
SRCB
GND
GND
GND
S_AUDIO_1
GND
R95
10K
HVF_IN1
HVF_IN2
ACLK_GS4911
V_STD_Sel
HVF_IN0
IO_V_GS4911
HVF_IN[2:0]
PCLK_GS4911
1V8_GS4911
IO_V_GS4911
1V8_GS4911
1V8_Core_GS4911
1V8_GS4911
GS4911_genlockb IO_V_GS4911 1V8_GS4911 1V8_GS4911
IO_V_GS4911
IO_V_GS4911
V_STD_Sel
1V8_GS4911
V_STD_Sel
Audio_RST
VID_PLL_GND
4VID_PLL_VDD
3
XTAL_VDD
5
X1
6
X2
7
XTAL_GND
8
CORE_GND
9
PHS_GND 55
PHS_VDD 54
ANALOG_VDD
10
NC
11
ANALOG_GND
12
AUD_PLL_GND
13
AUD_PLL_VDD
14
10FID
15
HSYNC
16
VSYNC
17
IO_VDD
18
FSYNC
19
NC
20
VID_STD0
21
VID_STD1
22
VID_STD2
23
VID_STD3
24
VID_STD4
25
VID_STD5
27
ACLK1
28
ACLK2
29
ACLK3
30
IO_VDD
31
CORE_VDD
26
ASR_SEL2
32
ASR_SEL1 33
ASR_SEL0 34
TIMING_OUT1 35
TIMING_OUT2 36
IO_VDD 38
TIMING_OUT4 39
TIMING_OUT3 37
TIMING_OUT5 40
LVDS/PCLK3_VDD 45
PCLK3 46
LVDS/PCLK3_GND 48
PCLK3 47
PCLK2 49
PCLK1&2_GND 52
PCLK1 51
IO_VDD 50
TIMING_OUT641
TIMING_OUT7 42
TIMING_OUT8 43
PCLK1&2_VDD 53
LOCK_LOST
1
REF_LOST
2
GENLOCK64
CORE_VDD 44
JTAG/HOST 56 SCLK_TCLK 57
SDIN_TDI 58
SDOUT_TDO 59
CS_TMS 60
RESET 61
IO_VDD 62
NC63
GND_PAD
65
U20
GS4911
AES inputs 1_2 and3_4 with SRCs
1V8_GS4911
Y2
27.000MHZ VDD_XTAL_GS4911
R99
10K
C120
24p
C119
38p
R98
22R
R97
1M
IO_V_GS4911
TP23
TP22 GND
GND
S_AUDIO_[3:0]
3V3_PLL_SRC4382_B
GND
Gr2_AES_Ser
AES inputs 5_6and7_8
S_AUDIO_3
1B1
3B2
S
6
GND
2
A4
5Vcc
U22
SN74LVC1G3157
IO_V_SRC4382
VCC_3.3V

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2.3 GS2972 Schematic Figure 2-3: GS2972 Schematic
TP12
C18 10u
R17 DNP
C41 4u7
R27 75R R24 75R
C24 10n
C16
1u
C5 10n
C37 1u
C6 10n
TP11
C33
1u
TP8
C34 10n
C3610u
C9 10n
R1 0R
R9 0R
C39 4u7
R28 75R
C29 10n
R23
750R
C32 10n
C8 1u
C15 1u
L3 5n6
C31
1u
R13 0R
TP10
R2675R
R6 0R
R14 200R
C10 10n
R11 0R
R65
NP
C7 10u
SDO
R7 105R
Return Loss compensation Network
SDOn
C30 1u
C35 100p
Pins A5,E1,K8,G10
C17 10n
GS2972_SDI_SDOn GS2972_SDI_SDO
(SUBJECT TO CHA NGE)
VCO_VDD B7
VBG
A8
VCO_GND
B8
TDI E7
RSV A9
TIM_861G3
PCLK
B4
IO_VDD G1
DIN18
A2 DIN19 B3
LF
A7
AVDD A10
AGND
B10
DIN17
A1
CORE_VDD K8
GRP1_EN/DI S H6
DETECT_TR S F3
CORE_GND
E6
AGND
B9
DIN16
B2
CORE_VDD G10
PLL_VDD A6
PLL_VDD B6
RSV D5
STANDBY D3
ACLK1
K7
WCLK1
J7
AIN_1/2
J6
DIN14
C2DIN15
B1
CORE_GND
C5CORE_GND
B5
RSV D6 RSV D7
DVB_ASI G5
LOCKED H4
GRP2_EN/DI S H5
AIN_3/4
K6
DIN12
C3DIN13 C1
RSV D8
TMS E8
TDO F8
RATE_SEL0 E3
CORE_GND
E5
CORE_VDD E1
ACLK2
K5
IO_VDD H10
DIN10
D2 DIN11 D1
RSV F4
TCKJ8
CORE_GND
G9
20BIT/10BIT G4
CORE_GND
F5
CORE_VDD A5
WCLK2
J5
IO_GND
G2
DIN8
F2 DIN9 F1
RSV F7
CD_GND
F9 CD_GND
E9
IOPROC_EN/DIS G7
SMPTE_BYPASS G6
RESET
G8
AIN_5/6
J4
ANC_BLANK H3
DIN6
H2 DIN7 H1
CD_GND
D9
CORE_GND
E2
AUDIO_INT H7
CS_TMS K9
SCLK_TCKJ10
SDOUT_TDO J9
AIN_7/8
K4
H/HSYNC
A4
DIN4
J2DIN5 J1
CORE_GND
F6
PLL_GND
C8PLL_GND
C7PLL_GND
C6
SDO_EN/DI S D4
SDIN_TDI K10
V/VSY NC
C4
IO_GND
H9
DIN2
K2 DIN3 K1
RSET F10
CD_VDD E10
SDO C10 SDO D10
CD_GND
C9
JTAG/HOST H8
F/DE
A3
RATE_SEL1 E4
DIN0
K3 DIN1
J3
U5 GS2972
C40 10n
L4 5n6
C19 10n TP9
C14 10n
C4 10n
C25 1u
C3 10n
GS2972_PCLK
SDOn SDO
GS2972_HVF[2:0] GS2972_DIN[19: 0]
GS2972_RESETn
GS2972_Audio[7:0]
JTAG[3:0]
Pin _ctrl[13:0]
GS2972_Locked
GNDA_2972
GS2972_GSPI[3:0]
GNDA_2972
GNDA_2972
GNDA_2972
VCC_3.3V
GNDA_2972
GNDA_2972
VCC_3.3V
+1.2V
+1.2V
CDVDD_2972
+1.2VA_2972
IOVDD_2972
+3.3VA_2972
+1.2VA_2972
+1.2VA_2972 IOVDD_2972 +3.3VA_2972
CDVDD_2972
+1.2V
GNDA_2972
CDVDD_2972
GND
CDVDD_2972
GND
GND
GND
GND
GND
GND
GND
C38 DNP
Close to GS2972.
GS2972_PCLK
R82
0R
R81
0R
GS2972_Locked
GS2972_AIN3_4GS2972_Audio3 GS2972_AIN1_2GS2972_Audio2
GS2972_WCLK1GS2972_Audio1
GS2972_ACLK1GS2972_Audio0
GS2972_AIN7_8GS2972_Audio7
GS2972_AIN5_6GS2972_Audio6
GS2972_WCLK2GS2972_Audio5
GS2972_ACLK2GS2972_Audio4
Close to GS2972.
GS2972_HGS2972_HVF0 GS2972_VGS2972_HVF1 GS2972_FGS2972_HVF2
GS2972_RESETn
GS2972_DIN14
Power Decoupling& Filtering
GS2972_DIN16 GS2972_DIN15 GS2972_DIN2 GS2972_DIN1 GS2972_DIN19 GS2972_DIN18 GS2972_DIN17 GS2972_DIN6 GS2972_DIN5 GS2972_DIN0 GS2972_DIN4 GS2972_DIN3 GS2972_DIN7 GS2972_DIN11 GS2972_DIN10 GS2972_DIN9 GS2972_DIN8 GS2972_DIN13 GS2972_DIN12
JTAG_HOSTn Pin _ctrl0
20BIT/10BITn Pin _ctrl6
SDO_EN/DI Sn Pin _ctrl5 DETECT_TR S Pin _ctrl4 ANC_BLANKn Pin _ctrl3
TIM861 Pin _ctrl12
GRP2_EN_DISn Pin _ctrl1
SMPTE_BYPASSn Pin _ctrl11
DVB_ASI Pin _ctrl10
RATE_SEL0 Pin _ctrl9 RATE_SEL1 Pin _ctrl8
IOPROC_EN/D ISn Pin _ctrl7
GRP1_EN_DISn Pin _ctrl2
Pin A10
IO_V
Pins A6,B6
GS2972_TDI2 JTAG0 GS2972_TMS2 JTAG1 GS2972_TCK2 JTAG3 GS2972_TDO2 JTAG2
3.3V or 1.8V
GS2972_SDO GS2972_GSPI0 GS2972_SDI GS2972_GSPI1 GS2972_SCKGS2972_GSPI2 GS2972_CSn GS2972_GSPI3
Pin E10
Pin _ctrl13STANDBY
Pins G1,H 10

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Evaluation Board User Guide
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2.4 Power Schematic
Figure 2-4: Power Schematic
C129
10u C82
10n
+1.2V
TP2
C26
0.1u
C102
10n
Between pins 33 and30
SRC-A
He at s in k
on copper
C27
22u
Between pins 33 and30
SRC-B
IN
8
SHDN
5
AGND
4PGND
6
SENSE 3
OUT 2
NC1
NC7
U4
LT3021ES8-1.2
500mA
C99
10n
C100
10n
C101
10n
C98
10n
C95
10u
DECOUPLING
@ PIN 5
GND
Between pins 16and17
SRC-B
Between pins 16and17
SRC-A
R760R
C134
10u
C135
10u
GND
1V8_SRC4382
C136
10u
C137
0.1u
C138
0.1u
VCC_1.8V
1V8_Core_GS4911VCC_1.8V
C112
10u
GND
C114
0.1u
C113
10u
C111
0.1u
R71
0R
1
2
3
JP7
()
VCC_3.3V
1.8V 3.3V
VCC_1.8V
IO V
IO_V
C88
10n
C86
1u
5V
R32
240R
R66
49.9K
R4
1.15K
+1.8V
C84
0.1u
TP3
PWR
C85
22u
He at s in k
on copper
IN
8
SHDN
5
AGND
4PGND
6
SENSE 3
OUT 2
NC1
NC7
U16
LT3021ES8-1.8
VCCA
1
GND
2
A
3B4
DIR 5
VCCB6
SN74LVC1T45DBVR
U15
C87
22u
500mA
VCC_3.3V
PWRGD_3V3
C90
1u
R2
3.57K
VCC_1.8V
C12
22u
GND
GND
VCC_5V
IN
5
IN
6
IN
7
IN
8
BIAS
10
PG
9
OUT 1
OUT 18
OUT 19
OUT 20
NC17
FB 16 EN
11
SS 15
GND
12
NC
13
NC
14
NC
2
NC
3
NC
4
Pad
21
U14
TPS74201_RGW
D7
LNJ311G8P
GND
VCC_5V
GNDGND
GND
VCC_3.3VVCC_5V
VCC_3.3V
VCC_5V
GND
GND
PWRGD_3V3
POWER SUPPLIES
C118
10n
C117
10n
GND
IO_V_GS4911
DECOUPLING@ PINS18,31,38,50,62
R68
0R
C96
0.1u
C97
0.1u
C78
10n
C75
10n
C76
10n
C77
10n
C74
10n
VCC_3.3V
C70
1u
IO_V
+1.2V
Between pins 43 and42
SRC-A
Between pins 43 and42
SRC-B
3V3_SRC4382
R72 2R
C20
EEV-FK1C221XP
R690R
C91
22u
GND
C139
10u
Between pins 9 and10
SRC-A
C140
0.1u
DECOUPLING@
PINS 26,44
C104
10u
GND
C105
10u
J1
5V Input
GND
VDD_XTAL_GS4911VCC_3.3V
C107
10u
C106
10u
R70
0R
C115
0.1u
3V3_PLL_SRC4382_A
C130
10u
GND
GND
R75 0R
C131
10u
R73 2R
3V3_SRC4382
Between pins 9 and10
SRC-B
C142
0.1u
C141
10u
GND
3V3_PLL_SRC4382_B
GS4911 decoupling
SRC4382 power decoupling
3V3_SRC4382
IO_V_SRC4382
GND
GND
C110
10u
1V8_GS4911VCC_1.8V
C73
10u
GND
C80
10u
C92
0.1u C81
0.1u
R67
0R
C108
0.1u
C72
0.1u
C94
0.1u
C93
10u
C109
0.1u
IO_V
VCC_3.3V
C83
10n
DECOUPLING@ PINS 3,10,14,45,53,54

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3. Board Layout
Figure 3-1: Layer 1 (Top Layer)

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Evaluation Board User Guide
50283 - 2 May 2012
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Figure 3-2: Layer 2 (Ground)

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Evaluation Board User Guide
50283 - 2 May 2012
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Figure 3-3: Layer 3 (Power)

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Evaluation Board User Guide
50283 - 2 May 2012
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Figure 3-4: Layer 4 (Signal 1)

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Evaluation Board User Guide
50283 - 2 May 2012
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Figure 3-5: Layer 5 (Signal 2)

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Evaluation Board User Guide
50283 - 2 May 2012
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Figure 3-6: Layer 6 (Bottom Layer)

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4. Bill of Materials
Table 4-1: Bill of Materials
Quantity Reference Part
14 C3, C4, C5, C6, C9, C10, C14, C17, C19, C24,
C29, C32, C34, C40
10nF Capacitor (402)
22 C7, C18, C36, C73, C80, C93, C95, C104, C105,
C106, C107, C110, C112, C113, C129, C130,
C131, C134, C135, C136, C139, C141
10μF Capacitor (0603)
8 C8, C15, C16, C25, C30, C31, C33, C37 1μF Capacitor (0603)
5 C12, C27, C85, C87, C91 22μF Capacitor (0805)
1 C20 EEV-FK1C221XP Capacitor
(CT-CAP/PANA_FK_D8)
30 C26, C69, C72, C81, C84, C92, C94, C96, C97,
C108, C109, C111, C114, C115, C116, C122,
C125, C126, C127, C128, C137, C138, C140,
C142, C143, C144, C145, C146, C147, C148
0.1μF Capacitor (0603)
1 C35 100pF Capacitor (0402)
2 C39, C41 4.7μF Capacitor (0603)
2 C43, C44 16pF Capacitor (0603)
3 C70, C86, C90 1μF Capacitor (0402)
15 C74, C75, C76, C77, C78, C82, C83, C88, C98,
C99, C100, C101, C102, C117, C118
10nF Capacitor (0402)
1 C119 38pF Capacitor (0402)
1 C120 24pF Capacitor (0402)
1 D7 LNJ311G8P (1206_LED)
2 JP1, JP8 TSW-105-07-L-D
1JP7 BLKCON
.100/VH/TM1SQ/W.100/3
1 J1 5V Input
(CON_WEID5MM_2_PWR)
2 J3, J4 UCBBJE20-1 (BNC_EDGEMNT
_GHZ-POUR-2LYR-ER3.8)
4 J13, J14, J15, J16 BCJ-FPLV01
1J25 SQT-124-01-F-D-RA (HEADER
2MM_48_2X24_INVERSE)
2 J27, J29 SQT-105-01-F-D-RA (HEADER
2MM_10_2X5_INVERSE)
1 J30 4 HEADER (header_4_1x4)

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2 L3, L4 5.6nH Inductor (0402)
16 R1, R6, R9, R11, R13, R67, R68, R69, R70, R71,
R75, R76, R81, R82, R112, R114
0ΩResistor (0603)
1 R2 3.57kΩ Resistor (0603)
3 R4, R86, R88 1.15kΩResistor (0603)
6 R7, R92, R93, R107, R110, R111 105ΩResistor (0603)
1 R14 200ΩResistor (0603)
9 R20, R21, R22, R77, R78, R79, R80, R95, R99 10kΩResistor (0603)
1 R23 750ΩResistor (0402)
9 R24, R26, R27, R28, R101, R102, R103, R104,
R105
75ΩResistor (0402)
1 R32 240ΩResistor (0603)
1 R66 49.9kΩResistor (0603)
2R72,R73 2ΩResistor (0805)
1 R97 1MΩResistor (0402)
1 R98 22ΩResistor (0603)
1R108 0ΩResistor (0402)
2 RN1, RN2 500ΩResistor Network
1SW6 SW8_LOGIC_DIP_TH
1SW7 SW6_LOGIC_DIP_TH
1S1B3S-1002
12 TP2, TP3, TP8, TP9, TP10, TP11, TP12, TP16,
TP17, TP21, TP22, TP23
Via (CT-TP)
1 U1 MAX6823V (SOT23)
1 U4 LT3021ES8-1.2 (CT-SOIC_8)
1U5 GS2972
(CT-BGA_100_11X11_1.00)
4 U10, U11, U12, U13 SN65LVDT2 (SOT23-5)
1 U14 TPS74201_RGW
(20QFN-5X5(MOD))
1U15 SN74LVC1T45DBVR (sot23-6)
1 U16 LT3021ES8-1.8 (CT-SOIC_8)
1 U17 FXL4TD245 (mlp16e)
2 U18, U22 SN74LVC1G3157 (SOT23-6)
1U20 GS4911B (64QFN-9X9-P65)
Table 4-1: Bill of Materials
Quantity Reference Part