Haier L42V6-A8K User manual

L42V6-A8K

1. Features
2. Safety Precautions
3. Images of Module and Circuit Boards
4.Key IC Description& Trouble Shooting Guide
5.Signal Flowing Chart
6. Bus Control Adjustment
7. Circuit Diagram

Features
1、Power equipment
This product requires AC power supply. The voltage value is as per the
information specified on the rating label,which is fixed on the back of the
television set.
2、Power consumption
The power consumption is less than 160 watt which is marked on the back
cover.
3、Ports
Power in、Antenna input、Earphone output 、Video and Audio input、S-Video
input、D-SUB input(Use as monitor)、YUV(YPbPr/YCbCr) and Audio
input、DVI input、DVI/PC audio input.
4、Color system: PAL/NTSC/SECAM, Sound system:BG/DK/I/M.
Multi-sound mode and picture mode.

Safety Precations
Warning
To avoid fire or electric hazards,never place your television receiver in an area with
heavy moisture.Attention should be paid to avoid accidental scratches or impacts
onto the LCD screen.The function of sound may be lost and the function may be
disordered in electrostatic discharge ,they can be restored by operation of the
controls.
Caution
Unauthorized disassembly of this product is prohibited.
Power supply
This product requires AC power supply. The voltage value is as per the information
specified on the rating label,which is fixed on the back of the television set.
Disconnect the televison set with the power source or antenna plug when it heavily
rains with thunderstorm or power supply is interrupted.Do not
tie the electric cables to any other objects to avoid accident damages.
Application area
Do not expose the television set directly to floodlight,sunlight,heavy humidity,high
temperature or thick dusts.Locate the television set in a well-ventilated area,away
from vibration and blockage of ventilation port on the television rear side.
Cleaning
Unplug the television set when the LCD screen is to be cleaned.Use soft fabrics for
cleaning the screen and electric cables.If necessary, a piece of wet but clean soft
cloth can be used for cleaning the screen,but never use any liquid or spray
detergent.

Images of Module and Circuit Boards
Circuit Boards
LCD Module:

Key IC Description& Trouble Shooting Guide
Trouble shooting guide
This diagram is suitable to elementary trouble shooting,if you want further
service,please contact us.

Signal Flowing Chart

Bus Control Adjustment
Instruction of remote controller

Factory menu
Factory menu options
1. To enter factory menu you can follow the steps:
A.Press “MENU”, and the main menu will display on the screen.
B.Press “DISPLAY” three times continuously, and a red “M” will display
on the top-left corner of the screen.
2. To change to next page, press ”MENU” please.
3. To quit from factory menu, please press”DISPLAY”.
4. Factory menu items:
A. Version informations:
Manufacturer
Version
Date
B. TV/AV position items
H-Position
V-Position
C. White banlance adjusting items:
R_DRV
G_DRV
B_DRV
R_CUT
G_CUT
B_CUT
R_Offset1
G_Offset1
B_Offset1
Backlight
Note:a. There is two separate group parameters you can change:
TV/AV/Svideo/USB and HDTV. Two group parameters are saved
separately. Press “TV/AV” to switch beween the two groups.
b. In this menu, you can press “-/--/---” to adjust white banlance automatically.
But if you doesn’t like the auto-adjust result,please adjust the parameters
manually.
D. Brightness and contrast numerical value range adjusting.
Video_Bri_MAX
Video_Bri_MID
Video_Bri_MIN
Video_Con_MAX
Video_Con_MID
Video_Con_MIN
HDTV_Bri_MAX
HDTV_Bri_MID
HDTB_Bri_MIN
HDTV_ Con _MAX
HDTV_ Con _MID

HDTV_ Con _MIN
PC_Bri_MAX
PC_Bri_MID
PC_Bri_MIN
PC _ Con _MAX
PC_Con_MID
PC_Con_MIN
E. EEPROM menu
a. Page 3
Index 10
Value 0: DVI channel disable.
1: DVI channel enable.
b. Page 3
Index 9
Value 0: OSD zoom disable
1: OSD zoom enable.
c. Page 3
Index 8
Value 0: Photo channel disable
1: Photo channel enable.
d. Page 4
Index 11
Value 0: Sumsang panel
1: LG.PHILIPS panel.
F. DEBUG menu
Slave addr
Page
Index
Value
G. Power on status
Power on status 0: When AC power on, the TV set will start up to “TV” channel
directly, no stand-by.
1: When AC power on, the TV set will be stand-by state. If you
press “Power”(DC power on), it will start up to “TV” channel.
2: The TV set will store the current source channel before
power down. When AC power on, it will start up to the source
channel stored directly, no stand-by.
3: The TV set will store the current source channel before
power down. When AC power on, it will be stand-by state.
Press”Power”(DC power on), then it will start up to the stored
channel.
H. Piture status mode menu
a. Bright Mode:
Brightness
Contrast
Color

Sharpness
b. Standard Mode:
Brightness
Contrast
Color
Sharpness
c. Soft Mode:
Brightness
Contrast
Color
Sharpness
Note:There is two separate group parameters you can change: TV/AV/Svideo/USB
and HDTV. Two group parameters are saved separately. Press “TV/AV” to
switch beween the two groups.
I.Sound status mode menu.
a. Music Mode
Treble
Bass
b. Standard Mode
Treble
Bass
c. News Mode
Treble
Bass
J. Volume adjust
Volume 1
Volume 25
Volume 50
Volume 75
Volume 100
K. ADC
GM5221
ADC Phase Delay
ADC Phase CLK
Note:There is two separate group parameters you can change: TV/AV/Svideo/USB
and HDTV. Two group parameters are saved separately. Press “TV/AV” to
switch beween the two groups.

Circuit Diagram
PrIN 10
R4
3.3K
R9 100
MCSCL 2,7,8,9,11
C3
100nF
RaisingSun Co.Ltd
+12V
MCSDA2,7,8,9,11
J2
DVI_IN/Female
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2625
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GG
Y2IN9
D1 BAV70
3
2 1
+5V
DDC_SCL_DVI 7
J1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
51 52
RXC+ 7 DDC_SDA_DVI 7
CrIN9
HDMI_AUDIO_L MP3_L 8
DDC_SCL_DVI 7
CbIN9
RXC- 7
DDC_SDA_DVI 7
RX1+7
RX2- 7
DVI and Interface V0.1
RS LCD TV
B
112Saturday, February 05, 2005
RaisingSun Co.Ltd
Title
Size Document Number Rev
Date: Sheet of
MUTE7 FB_IN9
Add Pin20 and Pin22 as Scart signal
STBY_AMP 7
RX0-7 RX2+ 7
RX0+7
AS_27
RX1-7
AS_3 7
Pin20&22:
9.5–12V = SCART 4 3
接口有：信号
5–8V = SCART 16 9 接口有 ： 信号
0–2V = SCART 接口无信号
PIP_TV9
R363 100R
AS_1 7
+5V_5221
MP_TV9
C1
100nF
D2
BAV99L
1
3
2
RESETn 7,8,9,11
AFT 7
VS1 7
DDC_SDA
AV_IN 9
+5V_5221
C2
10uF
R396
0R
SC_IN 9
R8 100
Scart_Signal_2 9
U1
24LC02
1
2
3
4
5
6
78
NC1
NC2
NC3
GND
SDA
SCL
VCLK VCC
HDMI_AUDIO_R
R7
0
SY_IN 9
R5
3.3K
Scart_Signal_1 9
Hot plug detection
+5VA
Video_Out 9
Y1IN 10
+5V
R395
0R_NC
STBY_34XY7
D3
BAV99L
1
3
2
DDC_SCL
MP3_R8
PbIN 10
R3 10
R11
4.7K

WP7
D22
BAV99L/OP
1
3
2
MCSCL_EE7 R19 100
R14
10K/NC
R353
10K/OP
R16
10K
C7
100nF
R352
0R
R350
10K/OP
R393 0R
+3.3V_LBADC
C8
22uF
10V
R397 0R/OP
Keypad
Keypad Jtag IR V0.1
RS LCD TV
A
212Saturday, February 05, 2005
Title
Size Document Number Rev
Date: Sheet of
LED7
R13
10K_NC
CN2
TJC3-9A
1
2
3
4
5
6
7
8
9
FB3
1 2
MCSDA 1,7,8,9,11
R355
0R
U2
24LC16
1
2
3
45
6
7
8A0
A1
A2
VSSSI
SCK
WP
VCC
MCSCL 1,7,8,9,11
Q18
2N7002/OP
3
1
2D
G
S
R18 100
D21
BAV99L/OP
1
3
2
3.3V_AVDD
C6
100nF
C338
47pF
R17
10K
MCSDA_EE7
C337
47pF
MOLEX 53261-1000
Q17
2N7002/OP
3
1
2D
G
S
+5V_5221
R351
10K/OP
MCSCL_EE7
R394 4.7K
C5
220pF
+5V_5221
+5V_5221
ADC_IN27
NV RAM
INTERFACE
R354
10K/OP
IR_IN7,8
+3.3V_LBADC +5V_5221
R15
0R
Q19
MMBT3904
3
1
2
ADC_IN17
LBADC_GND
MCSDA_EE7

R315 0R
HSYNC
+3.3V_AVDD
R37 100
R33100
C10
100nF
+3.3V_AVDD
RaisingSun Co.Ltd
VSYNC10
D6
BAV99L
1
3
2
R28
75
L3
FB
+3.3V_AVDD
+5V
R21 75
Graphic VGA Input V0.1
RS LCD TV
B
312Saturday, February 05, 2005
Title
Size Document Number Rev
Date: Sheet of
D8
BAV99L
1
3
2
R29
75
GGIN L6
40_OHM@100MHz
R231 0_NC
D9
BAV99L
1
3
2
U5
PI5V330Q
9
10
2
1
5
3
6
14
13 12
11
15
4
168
7
DD
S2D
S1A
IN
S1B
S2A
S2B
S1C
S2C DC
S1D
/EN
DA
VCCGND
DB
TV_B10
VGA_TV_SW7
R36 100
+5V
VGA_5V
HSYNC_23008
U4F
74HC14
13 12
147
TV_G10
U4A
74HC14
1 2
147
U4D
74HC14
9 8
147
U4E
74HC14
11 10
147
AVSYNC 7
DDC_SDA_VGA_1 7
HSYNC
D10 BAV70
3
2 1
DDC_SCL_VGA 7
+5V
L4
40_OHM@100MHz
AHSYNC 7
+3.3V_AVDD
R232 0_NC
VGACON 7
TV_R10
+5V
GSCL
R316 0R
+5V_5221
GAIN 7
L8
40_OHM@100MHz
R27
75
GSDA
RAIN 7
R317 0R
R20 75
GRIN
C11
100nF
D11
BAV99L
1
3
2
+5V_5221
+5V
C17
10uF
GBIN
C15
12pF
BAIN 7
R24 10K
C16
100nF
D7
BAV99L
1
3
2
+3.3V_AVDD
R32
3.3K/OP
RGSA
GVSI 10
R31
3.3K/OP
+3.3V_AVDD
U4B
74HC14
3 4
147
C13
12pF
+5V
RGSL
R34100
R22 0_NC
D4
BAV99L
1
3
2
C14
12pF
U4C
74HC14
5 6
147
D5
BAV99L
1
3
2
GVSI
GHSI
GHSI R233 100
P2
DB15HD/Female
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
R26
10K
C12
10uF
U6
24LC02_NC
1
2
3
4
5
6
78
NC1
NC2
NC3
GND
SDA
SCL
VCLK VCC
+5V

BRI 7
R43
4.7K
LVDS test points right on the trace to avoid extra length
R39
2.7K
TXOC-
FB46
BEAD
1 2
PBIAS 7
R45
4.7K/NC
LV_O2
TXOC+
PANEL_POWER
LV_O[0..9]5,7
LV_E7
FB42
1 2
LV_O4
FB6
FB_NC
1 2
+5V
R40 470
U7
SI9933ADY
1
2
3
4
8
7
6
5
S1
G1
S2
G2
D1
D1
D2
D2
TXO3-
CN12
CONN2_200MM
1
2
CN4
HDR_10X2X2.0mm
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Backlight
Inverter
Connector
+12V
+3.3V_DVDD
LV_E1
LV_O0
Q1
MMBT3904
3
1
2
LV_O7
TXO3+
LV_E[0..9]5,7
Q3
MMBT3904
3
1
2
FB48
BEAD
1 2
R44
4.7K/NC
TXO0-
PWM07 R41 1K
TXE0+
JP1
PH10/DGREE90
1
2
3
4
5
6
7
8
9
10
LV_E5
Q14
MMBT3904
3
1
2
DO NOT
INSTALL
PANEL_POWER
LV_O8
LV_E4
CN3
HDR_10X2X2.0mm
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
LV_O9
LV_O6
C19
22uF
LVDS Output V0.1
RS LCD TV
C
412Saturday, February 05, 2005
Title
Size Document Number Rev
Date: Sheet of
R322 0R/OP
TXE1-
+3.3V_DVDD
FB44
BEAD
1 2
R38
2.7K
Panel Power Voltage Selection
+3.3V_DVDD
PANEL_POWER
DE5
R318
2.7K
LV_E2
TXO0+
TXE1+
C20
100nF
Panel Power Switch
+12V BRI 7
R323
?
LV_E3
LV_O5
LV_E6
TXE2-
R320
2.7K/NC
Q2
MMBT3904
3
1
2
2.0mm PIN Header
+5V
ENBKL 7
C21
22uF
FB47
BEAD
1 2
TXE2+
TXE0-
R42 4.7K
PANEL_POWER
FB4
1 2
2.0mm PIN Header
LV_E9
ENBKL7
C18
100nF
TXEC-
PPWR7
TXO1-
+5V
FB49
BEAD
1 2
R321
2.7K/NC
LVDS Output
Connector
+3.3V_DVDD
LV_E8
R319
2.7K
TXEC+
+12V
BRI7
TXO1+
FB43
BEAD
1 2
LCD Control Output
AUX12V
+5V
+3.3V_DVDD
LV_O3
R324 4.7K
TXE3-
PPWR
TXO2-
PBIAS
+5V
ENBKL7
F1
3A
R46
4.7K
RaisingSun Co.Ltd
LV_O1
CN6
DF14A-30P-1.25H
1
2
3
4
6
8
10
12
14
16
18
20
22
24
26
28
30
7
9
11
13
15
17
19
21
23
25
27
29
5
LV_E0
FB5
FB
1 2
TXE3+
TXO2+
DO NOT
INSTALL

LV_O3
LV_O7
EG3
EB3
ER3 ER1
EG0
ER7
LV_E5
ER1
DVS
EG7
DE
EB0
ER3
EB5
EB5
ER4
EG[0..7]
LV_E9
HS
EB1
EB3
CLK
DEN7
EG5
EG5
EB6
LV_O2
ER3
RN422Rx4
8
7
6
5 4
3
2
1
LV_O4
EB7
EG1
RN1 22Rx4
8
7
6
5 4
3
2
1
EG0LV_E3 ER6
ER5
DHS
ER5
LV_E1
PANEL_POWER
ER1
RN222Rx4
8
7
6
5 4
3
2
1
EG1
LV_E7 ER2
EG7
RN622Rx4
8
7
6
5 4
3
2
1
EB4
EG3
ER[0..7]
DE
LV_O0
EG4
PD21
VS
EB2
ER2
EB2
DCLK
ER0
DCLK7
PD23
ER7
VS
LV_E0
DHS7
EG2
LV_E6
EG6
EB7
EB6
R55 22 1%
EB1
EG2
LV_O1
TTL Output V0.1
RS LCD TV
B
512Saturday, February 05, 2005
Title
Size Document Number Rev
Date: Sheet of
PD22
ER2
PANEL_POWER
EB0
EG6
EB0
LV_O8
EB4
VS
PD20
DE
CN5
CON50A
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
TTL panel
Digital Port
Output
Connector
HS
ER6
R54 22 1%
PD[20..23]7
LV_E4
EG0
ER4
EB2
DVS7
EB4
LV_E[0..9]4,7
LV_O6
R53 22 1%
ER0
LV_O[0..9]4,7
ER7
CN7
TTL-OUT-2X20X2mm
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
P32
P34
P36
P38
P40
P1
P3
P5
P7
P9
P11
P13
P15
P17
P19
P21
P23
P25
P27
P29
P31
P33
P35
P37
P39
CLK
RaisingSun Co.Ltd
EG4
LV_O9 EG1
LV_O5
DE 4
EB6
ER5
ER0
CLK
RN322Rx4
8
7
6
5 4
3
2
1EG3
EG2
LV_E2
EG4
EG6
DEN
ER4
EB7
RN522Rx4
8
7
6
5 4
3
2
1
EG5
EB[0..7]
HS
EB3
LV_E8
ER6
EB5
EB1
EG7
R56 22 1%

5VAON7
C46
47uF
10V
R20R
C29
100nF
C23
470uF/25V U9
LM3485
4
81
2
37 6
5
FB
VinISENSE
GND
NC PGATE PW GND
ADJ
J4 DIN/JackPower
1 2 3 4
5
6
7
8
9
1 2 3 4
5
6
7
8
9
C42
100nF
D13
SK22B
21 U10
LD1086DT33
1
3 2
4
ADJ
VIN VOUT
VO4
FB10
1 2
R404
0R
C26
100nF
R348100R
FB9
1 2
R407
0R
FB45
1 2
U8
AP4435M
4
81
2
37 6
5
G
DS
S
SD D
D
J6
CON9
1
2
3
4
5
6
7
8
9
R65
10K
UOC POWER CONTROL
MD6
HOLE
1
R403
0R
C40
220uF
10V
C33
100nF
+5V_5221
U29
SI9933BDY
1
2
3
4
8
7
6
5
S1
G1
S2
G2
D1
D1
D2
D2
C41
100uF
10V
+5V
+5V
R63
47K
C37
22uF
MD3
HOLE
1
+5V_5221
C30
470uF
10V
R64
10K
U11
LD1086DT33
1
3 2
4
ADJ
VIN VOUT
VO4
C24
100nF
C27
100uF
16V
+5VA
+3.3VD
R12
0R
+12V_IN
+12V_IN
D24
TZM5232B/5.6V
U13
LD1086DT18
1
3 2
4
GND
VIN VOUT
VO4
MD2
HOLE
1
D23DL4001-SMT
D16
DL4001-SMT
+3.3V_DVDD
+12V
+5V
D20DL4001-SMT
D18
SK22B
2 1
C52
100nF
F3
5A
RaisingSun Co.Ltd
+5V_5221
C31
100nF
+5V
MD1
HOLE
1
D17
DL4001-SMT
R349100R
CN11
TJC3-4A
1
2
3
4
D12
FM5820
2 1
C45
100nF
C48
47uF
10V
C35
100nF
R406
0R
+5V_5221
R62
15K
+5V
D15
SK22B
21
FB11
1 2
L3510uH
+1.8V_AVDD
C50
100nF
+5V
R60R/OP
PDP POWER
R67
10K
L11
33uH
D19DL4001-SMT
C51
100uF
10V
Power V0.1
RS LCD TV
RaisingSun Co.Ltd
B
612Saturday, February 05, 2005
Title
Size Document Number Rev
Date: Sheet of
CN13
TJC3-4A
1
2
3
4
1Vf
L3410uH
FB12 12
STBY 7
R57 47K
JP5
CONN3_250MM/OP
1 2 3
R405
0R
C43
100nF
C32
470uF
10V
R362
15K_NC
C36
22uF
STBY 7
C47
100nF
MD5
HOLE
1
TEMP_DETECT 7
C346 560pF
R66
10K_NS
C49
100uF
10V
C44
47uF
10V
C38
100nF
MD4
HOLE
1
J7
TJC3-2
1
2
FB7 12
R57=12K Then 5V/4A
+3.3V_AVDD
C28
100nF
FB13
1 2
C34
100nF
+1.8V_DVDD U12
LD1086DT18
1
3 2
4
GND
VIN VOUT
VO4
R10R
Q7
MMBT3904
3
1
2
R408
0R

CVDD_1.8
RMADDR10
R784.7K
R9310K_NC
DDC_SDA_DVI1
Close to respective power Pins
LV_O3
RMADDR16
R87
10K
LV_E6
RMDATA6
R235
4.7K
C140
100nF_SC
DDC_SCL_VGA3
3.3V_AVDD
LV_E1
RX1-1
RMADDR5
JP4
CONN3_250MM
1
2
3
RMADDR10
RMDATA2
C66
220pF
3.3V_AVDD
MCSDA_EE 2
LV_O4
Scart_Signal_2 1
AS_31
VGAHS
C81
100nF
R337
0R
RX1+
RMADDR0
UART_DO
C96
220pF
10K_NC R111
R325
0R/OP
PBIAS
LBADC_IN1
Initial state of OCM ROM:
RMDATA5
C57
100nF
+5V_5221
C112
100nF
DVS 5
ENBKL4
RMADDR7
RMADDR2
BLUE-
R236
4.7K
FB14
1 2
R313100R
LV_E3
RMADDR8
RMADDR3
C78
22uF
PD23
BLUE- DVS
R10310K_NC
RMADDR[6:0]
AS_21
R8910K_NC
R234
4.7K
DDC_SCL_DVI1
SOCKET:
IC51-2084-1052
RX0-
RXC+
GREEN+
R85
470K
C70
100nF
RX1+1
SPI_EN: 0 = parallel ROM I/F. 1 = SPI
serial ROM and Cache control
LV_E[0..9] 4,5
RMADDR12
RMADDR12
XTAL
RMADDR16
RMDATA3
R9610K_NC
C89
15pF
RMADDR11
C59
100nF
R360100R
C10510nF
RMDATA5
R48100
LV_E5
PWM1
C109
47pF
R10710K_NC
DDC_SDA_VGA_13
3.3V_AVDD
RED-
X1
14.318MHz
C82
100nF
C72
100nF
AS_11
G_UART_DI
DDC_SCL_DVI
RMADDR1 R94
33K
RMADDR4
C80
100nF
RESETn1,8,9,11
LV_E9
C63
100nF
R700R/OP
R326100R
DHS 5
MCSCL_EE 2
RMADDR8
For I2C address [6:0] to JTAG bridge
Host I/F, to determine device address.
SELECT ONE
AVDD_1.8
RMADDR2 LBADC_IN3
DDC_SCL_VGA
R10510K_NC
Close to respective power Pins
RMDATA[0..7]
RMADDR17
C58
100nF
RMADDR15
+1.8V_AVDD
LV_O1
R794.7K
RMDATA0
C71
100nF
RX2-1
Scart_Signal_1 1
RMADDR9
C77
220pF
C103
10nF
C92
100nF
FB15
1 2
R73
47R
3.3V_DVDD
BRI4
STBY_AMP 1
R311100R
R137
12K
C94
100nF
5221 V0.1
RS LCD TV
C
712Friday, April 22, 2005
Title
Size Document Number Rev
Date: Sheet of
GREEN-
RMADDR7
VGACON 3
LV_E0
RMADDR2
C95
100nF
ADCIN:
2.53–3.2V = SCART 4 3
接口有：信号
1.33–2.13V = SCART 16 9 接口有 ： 信号
0–0.54V = SCART 接口无信号
+1.8V_DVDD
C61
100nF
R6910K
RMADDR13
PD20
SW1
SW PUSHBUTTON
SOG10
11 = External parallel control bus using
ROM Addr/Data
RX0+
GREEN-
RMDATA2
C90
22uF
R92100
C60
100nF
R71
0R
R138 0R
KEYBOARD INPUT
TO LBW ADC
ROM_OEn
C55
100nF
C67
22uF
R760R
+3.3V_DVDD
ADC_IN1 2
RMADDR13
R359100R
DEN 5
RMADDR[12:7]
R88
10K
YUV_TV_SW 10
RMADDR0
R90 100R_SC
C87
220pF
C93
100nF
C79
100nF
3.3V_AVDD
SDA
PPWR
DEN
MCSDA
R86
470K_NC
R10010K_NC
CN9
TJC3-10A
1
2
3
4
5
6
7
8
9
10
DDC_SDA_VGA_1
RMADDR5
RX2+1
5VAON 6
IR_IN 2,8
RMADDR9
LV_O5
ENBKL
RMADDR11
C74
100nF
C53
22uF
BOOTSTRAP OPTIONS SELECT
(NOT POPULATED SHOULD BE
HARD WIRED)
C73
100nF
C101
10nF
User_Bits[5:0] for configuration setting
CN8
1
2
3
4
C111
100nF
MUTE 1
DHS
UART_DI
R9810K_NC
C110
100nF
00 = Normal. UART in 186 on system pins.
BRI
RMDATA7
R133
33K
C86
220pF
R97
12K
DCLKC102
10nF
R47100R
RMDATA1
RMDATA7
C91
100nF
AVSYNC3
RX1-
GPROBE
DEBUG
PORT
DHS5
C83
100nF
R361100R
10K_NC R101
VGA_TV_SW 3
RX2+
LV_E7
LV_E4
RMADDR6
U15
AT49F020-70JC
3
29
28
4
25
23
26
27
5
6
7
8
9
10
11
12
21
20
19
18
17
15
14
13
24
31
32
116
2
30
22
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
WE
VCC
NC GND
A16
NC/A17
CE
RXC-1
RMADDR[14:13]
RMADDR15
DDC_SDA_DVI
C113
100nF
Close to respective power Pins
10 = JTAG port, 5 wires
RX2-
RMADDR3
AHSYNC3
STBY 6 STBY_34XY 1
LV_O2
PD22
RED+
RMADDR15
R10610K
C100
100nF
+5V_5221
R102
10K
R80 270
RAIN3
RMDATA[0..7]
C98
100nF
R9510K_NC
Close to respective power Pins
ROM_CSn
BootStrap Signals
RMADDR1
LBADC_GND
R10410K_NC
CVDD_1.8
+5V
RMADDR1
C10410nF
R3120
01 = I2C to JTAG bridge.
SoftReset
R9910K_NC
C84
100nF
+5V_5221
RMADDR11
C75
100nF
+3.3V_AVDD
AVDD_1.8
PWM0 4
ADC_IN2 2
RMADDR6
RMADDR10
R10810K_NC R10910K_NC
C69
100nF
C68
100nF
R247
4.7K
R74
47R
0 = internal ROM on, and mapped to top
32K of OCM and OCM boot will be from
internal ROM codes.
WP 2
3.3V_AVDD
RMADDR14
R3140
C64
100nF
RXC+1
OSC_SEL: 0 = Xtal and internal oscillator.
1 = TTL oscillator (on TCLK pin)
+5V
TCLK
RMDATA3
C54
100nF
C56
100nF
OP_MODE[1:0]:
3.3V_DVDD
C107 100pF
R11010K_NC
PBIAS 4
3.3V_A
AGND
U14
gm5221
PQFP208
151
152
147
148
142
143
119
118
124
123
129
128
169
170
98
99
100
101
35
36
133
132
114
71
72
77
78
79
80
178
92
93
69
202
201
200
199
198
197
196
195
194
185
4
3
2
1
208
207
204
203
186
187
193
189
192
188
5
154
150
149
153
144
122
117
23
50 73 190 205 166 9 41 75 96 116
67
68
12
121
25
126
28
115
171
26
172
24
137
11
164
181
182
8
42
51
74
76
94
97
140
180
163
165
136
155
48
47
87
86
66
65
33
34
62
59
61
60
58
57
63
64
46
45
44
43
38
37
55
56
32
31
30
29
22
21
49
54
18
17
16
15
14
13
19
20
167
70
135
27
40
113
120
125
130
134
141
145
7
6
95
184
183
191
206
139 179
177
39
168
156
131
127
146
81
82
83
84
85
88
89
90
91
138
10
102 103 106 107 108 109 110 111 112 52 53 104 105 157 158 159 160 161 162
173
174
175
176
RED+
RED-
GREEN+
GREEN-
BLUE+
BLUE-
RX2-
RX2+
RX1-
RX1+
RX0-
RX0+
XTAL
TCLK
PWM0/GPIO11
PWM1/GPIO12
PWM2/GPIO13
PWM3/GPIO14
CH1P_LV_O(PD16/EB0)
CH1N_LV_O(PD17/EB1)
RXC-
RXC+
REXT
HOST_SCL/UART_DI
HOST_SDA/UART_DO
DDC_SCL_VGA
DDC_SDA_VGA
DDC_SCL_DVI
DDC_SDA_DVI
RESETn
GPIO9/SCL
GPIO10/SDA
STI_TM1/GPIO15
ROM_ADDR0
ROM_ADDR1
ROM_ADDR2
ROM_ADDR3
ROM_ADDR4
ROM_ADDR5
ROM_ADDR6
ROM_ADDR7
ROM_ADDR8
ROM_ADDR15
ROM_DATA0
ROM_DATA1
ROM_DATA2
ROM_DATA3
ROM_DATA4
ROM_DATA5
ROM_DATA6
ROM_DATA7
ROM_ADDR14
ROM_ADDR13
ROM_ADDR9
ROM_ADDR11
ROM_ADDR10
ROM_ADDR12
ROM_OEn
AVDD_ADC_33
AVDD_RED_33
AGND_GREEN
AGND_RED
AGND_BLUE
AGND_RX1
AGND_RX2
AVSS_OUT_LV_E
RVDD_33 RVDD_33 RVDD_33 RVDD_33
VDD_RPLL_18
CVDD_18 CVDD_18 CVDD_18 CVDD_18
VDD_RX2_18
PPWR
PBIAS
AVSS_OUT_LV_E
VDD_RX1_18
AVSS_LV
VDD_RX0_18
AVSS_OUT_LV_O
AGND_IMB
AVDD_RPLL_33
AVDD_LV_33
LBADC_VDD_33
AVDD_OUT_LV_E_33
VDD_RXPLL_18
AVDD_OUT_LV_E_33
VDD1_ADC_18
HSYNC
VSYNC
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
GND1_ADC
GND_RPLL
GND_RXPLL
ADC_TEST
DHS
DEN
CRVSS
CVDD_18
PD37/OG5
PD33/OG1
CH2P_LV_O(PD14/EG6)
CH2N_LV_O(PD15/EG7)
PD30/OR6
PD27/OR3
PD29/OR5
PD28/OR4
PD26/OR2
PD25/OR1
PD31/OR7
PD32/OG0
PD23/EB7
PD22/EB6
PD21/EB5
PD20/EB4
CH0N_LV_O(PD19/EB3)
CH0P_LV_O(PD18/EB2)
DCLK
PD24/OR0
CLKN_LV_O(PD13/EG5)
CLKP_LV_O(PD12/EG4)
CH3N_LV_O(PD11/EG3)
CH3P_LV_O(PD10/EG2)
CH0N_LV_E(PD9/EG1)
CH0P_LV_E(PD8/EG0)
DVS
NC
CH2N_LV_E(PD5/ER5)
CH2P_LV_E(PD4/ER4)
CLKN_LV_E(PD3/ER3)
CLKP_LV_E(PD2/ER2)
CH3N_LV_E(PD1/ER1)
CH3P_LV_E(PD0/ER0)
CH1P_LV_E(PD6/ER6)
CH1N_LV_E(PD7/ER7)
VBUFC_RPLL
STI_TM2
VBUFC_DVI
AVDD_OUT_LV_O_33
AVDD_OUT_LV_O_33
AVDD_IMB_33
AVDD_RX2_33
AVDD_RX1_33
AVDD_RX0_33
AVDD_RXC_33
AVDD_BLUE_33
AVDD_GREEN_33
ROM_CSn
ROM_WEn
RVDD_33
ROM_ADDR16
ROM_ADDR17
CRVSS
CRVSS
CVDD_18 CVDD_18
LBADC_GND
AVSS_OUT_LV_O
AGND_RPLL
AGND_ADC
AGND_RXC
AGND_RX0
SOG_MCSS
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7/IRQin
GPIO8/IRQout
CLKOUT
VCO_LV
VDATA7/GPIO16 VDATA6/GPIO17 VDATA5/GPIO18 VDATA4/GPIO19 VDATA3/GPIO20 VDATA2/GPIO21 VDATA1/GPIO22 VDATA0/GPIO23 VCLK NC NC NC NC NC NC NC NC NC NC
LBADC_IN1
LBADC_IN2
LBADC_IN3
LBADC_RETURN
+5V_5221
DVS5
GAIN3
MCSDA 1,2,8,9,11
T_STATE 11
LV_O9
LV_O6
RMADDR5
R409
10K
R238 3.3K
LV_E2
G_UART_DO
R237
4.7K
FB28 FB/OP
1 2
C10610nF
R9110K_NC
FB16
FB0805
1 2
PD21
BLUE+
RMADDR4
R75
47R
RMADDR14
C97
220pF
RMDATA6
FB17
1 2
C88
15pF
+5V_5221
RMADDR6
FB27 FB
1 2
RMADDR17
TEMP_DETECT 6
RMADDR14
LV_O7
RMADDR16
RMADDR0
LBADC_IN2
R770R
R83 100R/OP
RaisingSun Co.Ltd
RMADDR8
RXC-
C65
100nF
R3280R/OP
VGAVS
C108
47pF
R6810K
RX0-1
PPWR 4
RMADDR7
GPIO1
SoftReset
RED-
C76
100nF
LED 2
RMADDR17
RMADDR9
RS232
+5V_5221
PD[20..23] 5
RMADDR12
SCL
R327100R
BAIN3
+5V
GPIO0
RMADDR15
RMDATA4
1 = Internal ROM off. The external ROM
mapped to entire upper 512K of OCM
address. OCM boot from external ROM
code.
RMDATA4
MCSCL
RX0+1
J5
JUMPER
1 2
3.3V_AVDD
MP3_GPIO8
CVDD_1.8
C85
100nF
+5V_5221
MCSCL 1,2,8,9,11
LV_O0
RMADDR17
R336
4.7K/OP
C9910nF
Close to respective power Pins
VBI_INTR 9
LV_E8
RMADDR3
R723.3K/OP
LV_O8
RMADDR4
Route (LBADC_IN1, LBADC_RET) and
(LBADC_IN2, LBADC_RET) as differential
tracks close to each other and ground the
return track of each pair very close to the
5221 and ground pin
ROM_WEn
RMADDR16
RMDATA0
C62
100nF
32-Pin PLCC Socket
+5V_5221
SOG_MCSS
RMADDR13
3.3V_DVDD
RMDATA1
DCLK 5
3.3V_DVDD
LV_O[0..9] 4,5
VS11
R84
470K

MC3
MHBLK
C119
100nF
Fli2300 V0.1
RS LCD TV
C
812Saturday, February 05, 2005
Title
Size Document Number Rev
Date: Sheet of
IR_IN 2,7
ADDR6
+
C125
100uF
R117 22
DAC3.3V
DATA23
MY4
MPCLK
FB25
1 2
DATA0
MY0
DATA22
+
C139
100uF/16V
DATA30
ADDR7
ADDR10
SDRAM_CLK
DATA7
0
ADDR4
C155
47pF
DATA3
C169
100nF
R310
0R/OP
R2030R
0
DATA24
DATA26
YUV1
ADDR1
R11475
C9
100nF
+3.3VD DECFIELD9
MC3
MY3
D14
DL4001-SMT
C152
100nF
R121
100
DATA0
DAC1.8V
MC5
C131
15pF
12
DATA14
MC4
+3.3VIO
DATA28
L16
FB
C161
100nF
12
R204100
DATA6
+
C158
100uF
C128
100nF
R122
0R
MCSCL1,2,7,9,11
MC1
MVBLK
C167
100nF
C151
100nF
C147
100nF
C120
100nF
+3.3VIO
YUV3
ADDR2
DATA20
DATA20
MY6
MVBLK
DATA12MY4
R116 330R
86 PIN TSOP
U18
HY57V643220CT-6/IS42S32200B-6T
2
4
5
7
8
10
11
13
74
76
77
79
80
82
83
85
25
26
27
60
61
62
63
64
65
66
24
186
72 58 6 32 12 38
15 29 3 9 35 41 4946
30
57
69
70
73
22
23
19
18
20
17
68
67
14
21
31
33
34
36
37
39
40
42
45
47
48
50
51
53
54
56
16
71
28
59
55 75 81 43
52 78 84 44
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VDDVSS
VSS VSS VSSQ VSSQ VSSQ VSSQ
VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQVSSQ
NC
NC
NC
NC
NC
BA0
BA1
RAS
CAS
CS
WE
CLK
CKE
NC
NC
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM0
DQM1
DQM2
DQM3
VDDQ VDDQ VDDQ
VDD
VSSQ VSSQ VSSQ VSS
PLL1.8V
DATA2
DATA27
C144
100nF
DATA13
DATA18
ADDR1
C149
100nF
C163
100nF
FB19
1 2
MCSDA1,2,7,9,11
DATA8
R207
0R/OP
DATA11
R11275
DATA23
DATA18
DATA8
DATA15
DATA10
MY1
MC0
+
C129
10uF
DAC1.8V
MC4
PWCON
MC6
L12
FB
DATA12
ADDR8
R202
0R
DECHS9,11
DATA5
MY1
+
C124
47uF
C179
100nF
R309
10K
C164
100nF
RaisingSun Co.Ltd
DATA17
ADDR[0..10]
+
C127
10uF
C159
100nF
12
+
C126
100uF
+
C173
100uF
+3.3VD
DATA6
MY7
MFLD
YUV0
ADDR8
ADDR5
R11375
PLL1.8V
+1.8V
R341
4.7K
C121
100nF
DATA22
DATA19
VSYNC_2300 10
DATA2
C157
100nF
DAC1.8V
YUV5
+5VA
DATA[0..31]
R127
470
DATA25
MC7
DATA29
DATA9
C171
100nF
MP3_R 1
R115
470K
+
C137
10uF
C174
100nF
+3.3VIO
DECVS9,11
DATA16
MHBLK
MC7
+1.8V
C145
100nF
X2
13.5MHz
L14 FB
+3.3VIO
YUV2
MY6
DATA7
YUV6
DATA17
MCSCL
0
DATA24
ADDR2
C135
100nF
DATA26
U19
LD1086DT18
1
3 2
4
ADJ
VIN VOUT
VO4
MY5
C143
100nF
R126
NL
YUV7
MP3_L 1
DATA1
C136
47uF/16v
HSYNC_2300 3
MPCLK
+
C160
47uF
C156
47pF
DATA27
DATA5
R125
100
FB26
1 2
VDDQ
+5VA
DATA14
+
C162
100uF
C117
100nF
C154
100nF
C175
100nF
FB24
1 2
2300 I2C ADDRESS IS D0
PWCON
MY0
C115
100nF
WEN
DATA11
ADDR7
DATA21
R124
10K
C130
15pF
12
ADDR3 ADDR0
C170
100nF C180
100nF
DATA31
+1.8VD
MP3_GPIO 7
ADDR6
DECCLK9 YUV[0..7]9
DATA13
MY5
FB21
1 2
MC6
C150
100nF
L15 FB
ADDR9
C177
100nF
MFLD
DATA10
DATA30
MY2
R118 22
DATA1
JP6
CONN2X14_250MM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
+3.3VD
DATA29
R119
10K/NC
DATA21 DATA31
DATA9
ADDR9
VDDQ
DECCLK 9
MY3
MC2 ADDR3
C168
100nF
C134
100nF
+3.3VD
+1.8VD
C138
100nF
+3.3VIO
DATA16
MC5
VDDQ
MCSDA
VDDM
R120 100
DATA4
MY2
+5VA
DATA19
ADDR5
R329 10K
+
C133
47uF/16V
RESETn1,7,9,11
BOUT10
ADDR4
C166
100nF
C132
100nF
+1.8VD
U16
LD1086DT33
1
3 2
4
ADJ
VIN VOUT
VO4
C123
100nF
+3.3VD
ADDR0
Fli2300
U17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
HSYNC1_PORT1
VSYNC1_PORT1
FIELD ID1_PORT1
IN_CLK1_PORT1
HSYNC2_PORT1
VSYNC2_PORT1
FIELD ID2_PORT1
VDD1(3.3)
VSSio
IN_CLK2_PORT1
PORT1_A0
PORT1_A1
PORT1_A2
PORT1_A3
PORT1_A4
VDDcore1(1.8)
VSScore
PORT1_A5
PORT1_A6
PORT1_A7
PORT1_B0
PORT1_B1
PORT1_B2
PORT1_B3
PORT1_B4
PORT1_B5
PORT1_B6
PORT1_B7
PORT1_C0
VDD2(3.3)
VSSio
PORT1_C1
PORT1_C2
PORT1_C3
PORT1_C4
VDDcore2(1.8)
VSScore
PORT1_C5
PORT1_C6
PORT1_C7
IN_SEL
FILM SYNC_IN
DEV_ADDR1
DEV_ADDR0
SCLK
SDATA
RESET_N
VDD3(3.3)
VSSio
SDRAM DATA0
SDRAM DATA1
SDRM DT2
SDRAM DATA3 SDRAM DATA4 SDRAM DATA5 SDRAM DATA6 SDRAM DATA7 SDRAM DATA8 SDRAM DATA9 SDRAM DATA10 SDRAM DATA11 VDD4(3.3) VSSio SDRAM DATA12 SDRAM DATA13 SDRAM DATA14 SDRAM DATA15 VDDcore3(1.8) VSScore SDRAM DATA16 SDRAM DATA17 SDRAM DATA18 SDRAM DATA19 SDRAM DATA20 SDRAM DATA21 SDRAM DATA22 SDRAM DATA23 SDRAM DATA24 SDRAM DATA25 VDDcore4(1.8) VSScore SDRAM DATA26 SDRAM DATA27 SDRAM DATA28 SDRAM DATA29 SDRAM DATA30 SDRAM DATA31 VDD5(3.3) VSSio TEST IN SDRAM ADDR10 SDRAM ADDR9 SDRAM ADDR8 SDRAM ADDR7 SDRAM ADDR6 VDDcore5(1.8) VSScore SDRAM ADDR5 SDRAM ADDR4 SDRAM ADDR3 SDRAM ADDR2 SDRAM ADDR1 SDRAM ADDR0 WEN
OE
VID_OUT7
VID_OUT6
VID_OUT5
VID_OUT4
VID_OUT3
VID_OUT2
VID_OUT1
VID_OUT0
VSSio
VDD8(3.3)
VID_OUT15
VID_OUT14
VID_OUT13
VID_OUT12
VID_OUT11
VID_OUT10
VSScore
VDDcore7(1.8)
VID_OUT9
VID_OUT8
VID_OUT23
VID_OUT22
VID_OUT21
VID_OUT20
VID_OUT19
VID_OUT18
VSSio
VDD7(3.3)
VID_OUT17
VID_OUT16
CLKOUT
VSScore
VDDcore6(1.8)
CTLOUT4
CTLOUT3
CTLOUT2
CTLOUT1
CTLOUT0
TEST OUT1
TEST OUT0
TEST3
SDRAM CLKIN
VSSio
VDD6(3.3)
SDRAM CLKOUT
DQM
CSN
BA0
BA1
CASN
RASN
HSYN_PORT2
VSYN_PORT2
FILDID_PRT2
PORT2_7 PORT2_6 PORT2_5 PORT2_4 PORT2_3 PORT2_2 PORT2_1
VSScore
VDDcore8(1.8)
PORT2_0
IN_CLK_PORT2
VSSio
VDD9(3.3)
XTAL OUT
XTAL IN
TEST2 TEST1 TEST0
DAC_PVDD(3.3)
DAC_GR_AVDD(3.3)
DAC_GR_AVSS
DAC_AVSS
DAC_AVDD(3.3)
DAC_VREFIN
DAC_VREFOUT
DAC_RSET
DAC_COMP
DAC_AVSSR
DAC_AVDDR(3.3)
DAC_ROUT
DAC_AVSSG
DAC_AVDDG(3.3)
DAC_GOUT
DAC_AVSSB
DAC_AVDDB(3.3)
DAC_BOUT
DAC_VSS
DAC_VDD(1.8)
DAC_PVSS
AVSS_PLL_FE
AVDD_PLL_FE(1.8)
AVDD_PLL_SDI(1.8)
AVSS_PLL_SDI
AVSS_PLL_BE2
AVDD_PLL_BE2(1.8) AVDD_PLL_BE1(1.8)
AVSS_PLL_BE1
PLL_PVSS
PLL_PVDD(1.8)
DATA3
C146
100nF
R2080R/OP
PLL1.8V
DATA15
DATA28
ADDR10
C153
100nF
C116
100nF
DATA4
YUV4
MC0
C118
100nF
L17
FB
ROUT10
C148
100nF
DAC3.3V
GOUT10
DATA25
MC2
C141
100nF
C172
100nF
C165
100nF
MC1
DAC3.3V
MY7
C176
100nF
C122
100nF
C114
100nF
C178
100nF
R123
10K