Holtek HT68FB240 User manual
USB Low Speed Flash MCU
HT68FB240
Revision: V1.10 Date: November 26, 2019
Rev. 1.10 2 November 26, 2019 Rev. 1.10 3 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
Table of Contents
Features............................................................................................................ 6
CPU Features ......................................................................................................................... 6
Peripheral Features................................................................................................................. 6
General Description......................................................................................... 7
Block Diagram.................................................................................................. 7
Pin Assignment................................................................................................ 8
Pin Description ................................................................................................ 8
Absolute Maximum Ratings.......................................................................... 10
D.C. Characteristics....................................................................................... 10
A.C. Characteristics........................................................................................11
LVD & LVR Electrical Characteristics .......................................................... 12
Power on Reset Characteristics................................................................... 12
System Architecture...................................................................................... 13
Clocking and Pipelining......................................................................................................... 13
Program Counter................................................................................................................... 14
Stack ..................................................................................................................................... 15
Arithmetic and Logic Unit – ALU ........................................................................................... 15
Flash Program Memory................................................................................. 16
Structure................................................................................................................................ 16
Special Vectors ..................................................................................................................... 16
Look-up Table........................................................................................................................ 16
Table Program Example........................................................................................................ 17
In System Programming – ISP.............................................................................................. 18
Flash Memory Read/Write Page Size ................................................................................... 18
ISP Bootloader ...................................................................................................................... 20
Flash Program Memory Registers ........................................................................................ 20
In Application Program – IAP ................................................................................................ 24
In Circuit Programming – ICP ............................................................................................... 28
On-Chip Debug Support – OCDS ......................................................................................... 29
RAM Data Memory ......................................................................................... 29
Structure................................................................................................................................ 29
Special Function Register Description........................................................ 31
Indirect Addressing Register – IAR0, IAR1 ........................................................................... 31
Memory Pointers – MP0, MP1 ............................................................................................. 31
Bank Pointer – BP ................................................................................................................ 32
Accumulator – ACC............................................................................................................... 32
Program Counter Low Register – PCL ................................................................................. 32
Look-up Table Registers – TBLP, TBHP, TBLH .................................................................... 32
Status Register – STATUS ................................................................................................... 33
Rev. 1.10 2 November 26, 2019 Rev. 1.10 3 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
Oscillator ........................................................................................................ 35
Oscillator Overview .............................................................................................................. 35
System Clock Congurations ............................................................................................... 35
Internal RC Oscillator – HIRC .............................................................................................. 37
Internal 32kHz Oscillator – LIRC .......................................................................................... 37
Operating Modes and System Clocks ........................................................ 37
System Clocks ..................................................................................................................... 37
System Operation Modes ..................................................................................................... 38
Control Register .................................................................................................................... 40
Operating Mode Switching ................................................................................................... 41
Standby Current Considerations .......................................................................................... 45
Wake-up ............................................................................................................................... 45
Programming Considerations ............................................................................................... 46
Watchdog Timer............................................................................................. 46
Watchdog Timer Clock Source.............................................................................................. 46
Watchdog Timer Control Register ......................................................................................... 46
Watchdog Timer Operation ................................................................................................... 47
WDT Enable/Disabled using the WDT Control Register ....................................................... 47
Reset and Initialisation.................................................................................. 48
Reset Overview..................................................................................................................... 48
Reset Functions ................................................................................................................... 49
Reset Initial Conditions ........................................................................................................ 53
Input/Output Ports ......................................................................................... 56
Pull-high Resistors ................................................................................................................ 56
Port Wake-up ........................................................................................................................ 57
I/O Port Control Registers ..................................................................................................... 58
I/O Pin Structures.................................................................................................................. 60
Programming Considerations ............................................................................................... 60
Timer Modules – TM ...................................................................................... 61
Introduction ........................................................................................................................... 61
TM Operation ........................................................................................................................ 61
TM Clock Source................................................................................................................... 61
TM Interrupts......................................................................................................................... 62
TM External Pins .................................................................................................................. 62
TM Input/Output Pin Control Registers ................................................................................. 62
Programming Considerations................................................................................................ 64
Compact Type TM – CTM .............................................................................. 65
Compact TM Operation ........................................................................................................ 65
Compact Type TM Register Description................................................................................ 66
Compact Type TM Operating Modes .................................................................................... 70
Compare Match Output Mode............................................................................................... 70
Timer/Counter Mode ............................................................................................................ 73
PWM Output Mode ............................................................................................................... 73
Rev. 1.10 4 November 26, 2019 Rev. 1.10 5 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
Serial Interface Module – SIM ...................................................................... 76
SPI Interface ........................................................................................................................ 76
SPI Interface Operation ........................................................................................................ 76
SPI Registers ........................................................................................................................ 77
SPI Communication ............................................................................................................. 80
SPI Bus Enable/Disable ........................................................................................................ 82
SPI Operation........................................................................................................................ 82
I2C Interface ................................................................................................... 84
I2C Interface Operation ......................................................................................................... 84
I2C Registers ......................................................................................................................... 85
I2C Bus Communication ....................................................................................................... 89
I2C Bus Start Signal .............................................................................................................. 89
I2C Bus Slave Address ......................................................................................................... 90
I2C Bus Read/Write Signal ................................................................................................... 90
I2C Bus Slave Address Acknowledge Signal ........................................................................ 90
I2C Bus Data and Acknowledge Signal ................................................................................ 90
I2C Time Out Operation ......................................................................................................... 92
Peripheral Clock Output................................................................................ 93
Peripheral Clock Operation ................................................................................................... 93
Pulse Width Modulator ................................................................................. 94
PWM Operation..................................................................................................................... 94
6+2 PWM Mode .................................................................................................................... 95
7+1 PWM Mode .................................................................................................................... 96
PWM Output Control ............................................................................................................. 97
PWM Programming Example................................................................................................ 97
Interrupts ........................................................................................................ 98
Interrupt Registers................................................................................................................. 98
Interrupt Operation .............................................................................................................. 101
External Interrupt................................................................................................................. 103
USB SIE Interrupt................................................................................................................ 103
USB Setup Token Interrupt ................................................................................................. 103
USB Endpoint 0 IN Token Interrupt ..................................................................................... 103
USB Endpoint 0 OUT Token Interrupt ................................................................................. 104
Serial Interface Module Interrupt......................................................................................... 104
LVD Interrupt ...................................................................................................................... 104
Multi-function Interrupt ........................................................................................................ 104
TM Interrupts ...................................................................................................................... 105
Interrupt Wake-up Function................................................................................................. 105
Programming Considerations.............................................................................................. 105
Low Voltage Detector – LVD ....................................................................... 106
LVD Register ....................................................................................................................... 106
LVD Operation..................................................................................................................... 107
Rev. 1.10 4 November 26, 2019 Rev. 1.10 5 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
USB Interface ............................................................................................... 108
Power Plane........................................................................................................................ 108
USB Suspend Wake-Up Remote Wake-Up ........................................................................ 108
USB Interface Operation ..................................................................................................... 109
USB Interface Registers...................................................................................................... 109
Application Circuits......................................................................................116
Instruction Set...............................................................................................117
Introduction ..........................................................................................................................117
Instruction Timing .................................................................................................................117
Moving and Transferring Data..............................................................................................117
Arithmetic Operations...........................................................................................................117
Logical and Rotate Operation ..............................................................................................118
Branches and Control Transfer ............................................................................................118
Bit Operations ......................................................................................................................118
Table Read Operations ........................................................................................................118
Other Operations..................................................................................................................118
Instruction Set Summary .............................................................................119
Table Conventions................................................................................................................119
Instruction Denition................................................................................... 121
Package Information ................................................................................... 130
SAW Type 46-pin QFN (6.5mm×4.5mm) Outline Dimensions ............................................ 131
48-pin LQFP (7mm×7mm) Outline Dimensions .................................................................. 132
Rev. 1.10 6 November 26, 2019 Rev. 1.10 7 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
Features
CPU Features
• Operating voltage:
♦VDD (MCU)
fSYS = 6MHz: 2.2V~5.5V
fSYS = 12MHz: 3.3V~5.5V
♦VDD (USB mode)
fSYS = 6MHz/12MHz: 3.3V~5.5V
fSYS = 16MHz: 4.5V~5.5V
• Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V
• HALT function and wake-up feature reduce power consumption
• Oscillators:
♦Internal 12MHz RC – HIRC
♦Internal 32kHz RC – LIRC
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• All instructions executed in one or two instruction cycles
• Table read instructions
• 63 powerful instructions
• 8-level subroutine nesting
• Bit manipulation instruction
Peripheral Features
• Flash Program Memory: 4K × 16
• RAM Data Memory: 160 × 8
• USB 2.0 Low Speed compatible
• Up to 3 endpoints supported including endpoint 0
• All endpoints except endpoint 0 support interrupt transfer
• Endpoint 0 supports control transfer for Setup, In and Out token respectively
• Endpoint 0 has 8 bytes FIFO size, supports DMA interface for congure USB descriptor
• Support 3.3V LDO and integrate an internal 1.5K ohm pull-up resistor on UDN line
• Internal 12MHz RC OSC with 1.5% accuracy for all USB modes
• Watchdog Timer function
• Up to 34 bidirectional I/O lines
• Two pin-shared external interrupts
• Two Compact Timer Modules for time measure, compare match output, PWM output functions
• Serial Interface Modules with SPI and I2C interfaces
• Low voltage reset function
• Low voltage detect function
• In-system programmable in 32 words sector
• Support 3 channels 8-bit PWM
• Support ISP/IAP function
• Flash program memory can be re-programmed up to 10,000 times
• Flash program memory data retention > 10 years
• OCDS debug Interface for HT68VB240 only
• Package types: 46-pin QFN, 48-pin LQFP
Rev. 1.10 6 November 26, 2019 Rev. 1.10 7 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
General Description
The HT68FB240 is Flash Memory I/O with USB type 8-bit high performance RISC architecture
microcontrollers, designed for applications that interface directly to analog signals and which require
an USB interface. Oering users the convenience of Flash Memory multi-programming features,
these devices also include a wide range of functions and features. Other memory includes an area of
RAM Data Memory.
Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM
generation functions. Communication with the outside world is catered for by including fully
integrated SPI,I2C and USB interface functions, three popular interfaces which provide designers
with a means of easy communication with external peripheral hardware. Protective features such as
an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent
noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical
environments. The external interrupt can be triggered with falling edges or both falling and rising
edges.
A full choice of two oscillator functions are provided including two fully integrated system
oscillators which requires no external components for their implementation. The ability to operate
and switch dynamically between a range of operating modes using different clock sources gives
users the ability to optimise microcontroller operation and minimise power consumption.
The inclusion of exible I/O programming features along with many other features ensure that the
devices will nd specic excellent use in a wide range of application possibilities such as sensor
signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc.
This device is fully supported by the Holtek range of fully functional development and programming
tools, providing a means for fast and ecient product development cycles.
Block Diagram
Flash
Program
Memory
8-bit
RISC
MCU
Core
Watchdog
Timer
Interrupt
Controller
LIRC
Oscillator
HIRC
Oscillator
SIM TMn
Reset
Circuit
I/O PWM
8-bit × 3
USB 2.0
XCVR
RAM
Data
Memory
USB 2.0
Low Speed
Engine
Low
Voltage
Detect
Low
Voltage
Reset
3.3V
Regulator
Flash
Programming
Circuitry (ICP)
Stack
Rev. 1.10 8 November 26, 2019 Rev. 1.10 9 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
45
464748 3738394041424344
HT68FB240
48 LQFP-A
PC2
NC
UDN/GPIO0
UDP/GPIO1
V33O
UBUS/VDD
PD0
PD1
PC6/PWM2
PA2
PA1
PA0/OCDSDA
PC1
PC4/PWM0
PD7/TP1B
PD6/TP0B
NC
PA5
PA4
PC7
PB7/INT1
PB5/PCK
NC
NC
NC
PD3
PD2
PD5/TCK1
PD4/TCK0
PA6/TP0
PA7/TP1
PC5/PWM1
PB0
PB1/SDO/SDA
PB2/SDI/SCL
PB3/SCK
PB4/SCS
PB6/INT0
PA3
PC3
VSS
RES/OCDSCK
NC
PE1
PE0
NC
NC
PC0
1
2
3
4
5
6
7
8
910 11 1213 14 15 16 17 1819 20 21
24
25
26
27
28
29
30
31
32
43
444546 3536373839404142
HT68FB240
46 QFN-A
PE0
PC7
UDN/GPIO0
UDP/GPIO1
V33O
UBUS/VDD
VSS
RES/OCDSCK
PD4/TCK0
PA2
PA0/OCDSDA
PD3
PD2
PD1
PD0
PA4
PD7/TP1B
PD6/TP0B
PD5/TCK1
PB7/INT1
PB5/PCK
PA7/TP1
PA6/TP0
PA5
PC1
PC0
PC3
PC2
PC4/PWM0
PC5/PWM1
PC6/PWM2
PB0
PB1/SDO/SDA
PB2/SDI/SCL
PB3/SCK
PB4/SCS
PB6/INT0
PA3
PE1
NC
NC
NC
NC
NC
22 23
3334
PA1
NC
Pin Description
The pins on this device can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the
digital I/O function of the pins. However these Port pins are also shared with other function such as
the Serial Port pins etc. The function of each pin is listed in the following table, however the details
behind how each pin is congured is contained in other sections of the datasheet.
Pin Name Function OPT I/T O/T Description
PA0/
OCDSDA
PA0 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
OCDSDA — ST CMOS OCDS data input/output, for EV chip only.
PA1~PA5 PAn PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
PA6/TP0 PA6 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
TP0 TMPC ST CMOS TM0 output
PA7/TP1 PA7 PAPU
PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
TP1 TMPC ST CMOS TM1 output
PB0 PB0 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
PB1/SDO/
SDA
PB1 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
SDO — — CMOS SPI serial data output
SDA — ST NMOS I2C data line
PB2/SDI/SCL
PB2 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
SDI — ST — SPI serial data input
SCL — ST NMOS I2C clock line
PB3/SCK PB3 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
SCK — ST CMOS SPI serial clock
Rev. 1.10 8 November 26, 2019 Rev. 1.10 9 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
Pin Name Function OPT I/T O/T Description
PB4/SCS PB4 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
SCS — ST CMOS SPI slave select pin
PB5/PCK PB5 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
PCK — — CMOS Peripheral output clock
PB6/INT0 PB6 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
INT0 — ST — External interrupt 0
PB7/INT1 PB7 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
INT1 — ST — External interrupt 1
PC0~PC3 PCn PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
PC4/PWM0 PC4 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
PWM0 PWMC — CMOS PWM0 output
PC5/PWM1 PC5 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
PWM1 PWMC — CMOS PWM1 output
PC6/PWM2 PC6 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
PWM2 PWMC — CMOS PWM2 output
PC7 PC7 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
PD0~PD3 PDn PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
PD4/TCK0 PD4 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
TCK0 — ST — TM0 clock input
PD5/TCK1 PD5 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
TCK1 — ST — TM1 clock input
PD6/TP0B PD6 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
TP0B TMPC ST CMOS TM0 inverter output
PD7/TP1B PD7 PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
TP1B TMPC ST CMOS TM1 inverter output
PE0~PE1 PEn PXPU
PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up.
RES/
OCDSCK
RES — ST — Reset input
OCDSCK — ST — OCDS clock input, for EV chip only.
UDN/GPIO0 UDN — ST CMOS USB UDN line
GPIO0 — ST CMOS General purpose I/O
UDP/GPIO1 UDP — ST CMOS USB UDP line
GPIO1 — ST CMOS General purpose I/O
UBUS/VDD UBUS — PWR — USB SIE VDD
VDD — PWR — Power supply
Rev. 1.10 10 November 26, 2019 Rev. 1.10 11 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
Pin Name Function OPT I/T O/T Description
V33O V33O — — PWR 3.3V regulator output
VSS VSS — PWR — Ground
Note: I/T: Input type; O/T: Output type
OP: Optional by conguration option (CO) or register option
PWR: Power; CO: Conguration option
ST: Schmitt Trigger input; CMOS: CMOS output
Absolute Maximum Ratings
Supply Voltage ................................................................................................VSS−0.3V to VSS+6.0V
Input Voltage ..................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature....................................................................................................-50˚C to 125˚C
Operating Temperature..................................................................................................-40˚C to 85˚C
IOH Total ..................................................................................................................................-100mA
IOL Total ................................................................................................................................... 150mA
Total Power Dissipation ........................................................................................................ 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum
Ratings" may cause substantial damage to these devices. Functional operation of these devices at
other conditions beyond those listed in the specication is not implied and prolonged exposure to
extreme conditions may aect devices reliability.
D.C. Characteristics
Ta= 25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VDD
Operating Voltage
(HIRC OSC) ─fSYS=12MHz 3.3 — 5.5 V
IDD1
Operating Current
(HIRC OSC, fSYS=fH,
fS=fSUB=fLIRC)
3V No load, fH=12MHz, WDT enable
USB disable, LVR enable
— 2.2 3.3 mA
5V — 5.0 7.5 mA
IDD2
Operating Current
(LIRC OSC, fSYS=fL=fLIRC,
fS=fSUB=fLIRC)
3V No load, WDT enable, fLIRC=32K,
Clear CLK_ADJ (SYSC.7=0)
USB disable, LVR enable
─35 70 μA
5V — 70 100 μA
IDD3
Operating Current
(HIRC OSC, fSYS=fH,
fS=fSUB=fLIRC)
3V No load, fH=12MHz, WDT enable,
USB enable, V33O on, LVR enable
— 4.8 10 mA
5V — 11 16 mA
ISTB1
Standby Current (Idle 0)
(HIRC OSC, fSYS=o,
fS=fSUB=fLIRC)
3V No load, system HALT, WDT enable,
fSYS=12MHz o (FSYSON=0),
Clear CLK_ADJ (SYSC.7=0)
— 1.5 3.0 μA
5V — 3.0 6.0 μA
ISTB2
Standby Current (Sleep 0)
(HIRC OSC, fSYS=o,
fS=fSUB=fLIRC)
3V No load, system HALT, WDT disable,
fSYS=12MHz,
Clear CLK_ADJ (SYSC.7=0)
— 0.1 1 μA
5V — 0.3 2 μA
ISUS1
Suspend Current (Sleep 0)
(HIRC OSC, fSYS=o,
fS=fSUB=fLIRC)
5V
No load, system HALT, WDT disable,
LVR disable
USB transceiver, 3.3V Regulator on,
clr SUSP2 (UCC.4) and clr RCTRL
(UCC.7),Clear CLK_ADJ (SYSC.7=0)
— 330 400 μA
Rev. 1.10 10 November 26, 2019 Rev. 1.10 11 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
ISUS2
Suspend Current (Sleep 0)
(HIRC OSC, fSYS=o,
fS=fSUB=fLIRC)
5V
No load, system HALT, WDT disable,
LVR disable
USB transceiver, 3.3V Regulator o,
set SUSP2 (UCC.4) and set RCTRL
(UCC.7),Clear CLK_ADJ (SYSC.7=0)
— 220 300 μA
VIL1
Input Low Voltage for I/O
Ports, TCK and INT
5V — 0 ─0.3VDD V
— (Except VDD=5V) 0 ─0.2VDD V
VIH1
Input High Voltage for I/O
Ports, TCK and INT
5V — 0.7VDD ─VDD V
— (Except VDD=5V) 0.8VDD ─VDD V
VIL2 Input Low Voltage (RES) — — 0 ─0.4VDD V
VIH2 Input High Voltage (RES) — — 0.9VDD ─VDD V
IOL I/O Port Sink Current 5V VOL=0.4V 2 4 ─mA
IOH I/O Port Source Current 5V VOH=3.4V -2 -4 ─mA
VV33O 3.3V regulator output 5V IV33O=20mA 3.0 3.3 3.6 V
RUDN
Pull-high Resistance
between UDN and V33O 3.3V — -5% 1.5 +5% kΩ
RPH
Pull-high Resistance of I/O
Ports
3V — 20 60 100 kΩ
5V — 10 30 50 kΩ
A.C. Characteristics
Ta= 25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
fSYS
System clock (HIRC OSC)
USB mode (USB On)
4.2V~
5.5V Ta=25°C -3% 12 +3% MHz
fLIRC System clock (32K RC)
5V Ta=25°C -10% 32 +10% kHz
2.2V~
5.5V Ta=-40°C to 85°C -50% 32 +60% kHz
tTCK TCKn Input Pin Minimum Pulse Width — — 0.3 — — μs
tRES
External Reset Minimum Low Pulse Width
— — 10 — — μs
tINT Interrupt Minimum Pulse Width — — 10 — — μs
tSST
System Start-up Timer Period
(Wake-up from HALT, fSYS o at HALT
state, Slow Mode → Normal Mode)
— fSYS=HIRC 1024 — — tSYS
— fSYS=LIRC 2 — — tSYS
System Start-up Timer Period (Wake-
up from HALT, fSYS on at HALT state) — — 2 — — tSYS
tRSTD
System Reset Delay Time (Power On
Reset, LVR reset, LVR S/W (LVRC)
reset, WDT S/W (WDTC) reset)
— — 25 50 100 ms
System Reset Delay Time (Any Reset
except Power On Reset, LVR reset,
LVR S/W (LVRC) reset, WDT S/W
(WDTC) reset)
— — 8.3 16.7 33.3 ms
Rev. 1.10 12 November 26, 2019 Rev. 1.10 13 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
LVD & LVR Electrical Characteristics
Ta= 25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VLVR1 Low Voltage Reset Voltage — LVR Enable -5% 2.1 +5% V
VLVD1
Low Voltage Detector Voltage —
LVDEN = 1, VLVD = 2.0V
-5%
2.0
+5%
V
VLVD2 LVDEN = 1, VLVD = 2.2V 2.2 V
VLVD3 LVDEN = 1, VLVD = 2.4V 2.4 V
VLVD4 LVDEN = 1, VLVD = 2.7V 2.7 V
VLVD5 LVDEN = 1, VLVD = 3.0V 3.0 V
VLVD6 LVDEN = 1, VLVD = 3.3V 3.3 V
VLVD7 LVDEN = 1, VLVD = 3.6V 3.6 V
VLVD8 LVDEN = 1, VLVD = 4.0V 4.0 V
ILVR
Additional Power Consumption if
LVR is used
3V LVR disable → LVR enable — 30 45 μA
5V — 60 90 μA
ILVD
Additional Power Consumption if
LVD is used
3V LVD disable → LVD enable
(LVR disable)
— 40 60 μA
5V — 75 115 μA
3V LVD disable → LVD enable
(LVR enable)
— 30 45 μA
5V — 60 90 μA
tLVR Low Voltage Width to Reset — — 120 240 480 μs
tLVD Low Voltage Width to Interrupt — — 20 45 90 μs
tSRESET Software Reset Width to Reset — — 45 90 120 μs
tLVDS LVDO stable time —For LVR enable, LVD o →on — — 15 μs
—For LVR disable, LVD o →on — — 15 μs
Power on Reset Characteristics
Ta= 25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VPOR
VDD Start Voltage to Ensure Power-on
Reset — — — — 100 mV
RRVDD VDD Rise Rate to Ensure Power-on Reset — — 0.035 — — V/ms
tPOR
Minimum Time for VDD Stays at VPOR to
Ensure Power-on Reset — — 1 — — ms
Rev. 1.10 12 November 26, 2019 Rev. 1.10 13 November 26, 2019
HT68FB240
USB Low Speed Flash MCU
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to
their internal system architecture. The range of the device take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the
exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set
operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement,
branch decisions, etc. The internal data path is simplied by moving data through the Accumulator
and the ALU. Certain internal registers are implemented in the Data Memory and can be directly
or indirectly addressed. The simple addressing methods of these registers along with additional
architectural features ensure that a minimum of external components is required to provide a
functional I/O control system with maximum reliability and flexibility. This makes the device
suitable for low-cost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four
internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the
instruction will take one more instruction cycle to execute.
System Clocking and Pipelining
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to rst obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
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USB Low Speed Flash MCU
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is ex-
ecuted except for instructions, such as "JMP" or "CALL" that demands a jump to a non-consecutive
Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are
directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Program Counter
High Byte Low Byte (PCL Register)
PC11~PC8 PCL7~PCL0
Program Counter
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly. However, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
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USB Low Speed Flash MCU
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is organized into 8 levels and neither part of the data nor part of the program space,
and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of
the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request ag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
If the stack is overow, the rst Program Counter save in the stack will be lost.
Progra m Counte r
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 8
Progra m
Memory
Top of S ta ck
Stack
Poin te r
Bottom o f Stack
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specied register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement INCA, INC, DECA, DEC
• Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
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USB Low Speed Flash MCU
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For this device series
the Program Memory is Flash type, which means it can be programmed and re-programmed a large
number of times, allowing the user the convenience of code modication on the same device. By
using the appropriate programming tools, the Flash device oer users the exibility to conveniently
debug and develop their applications while also offering a means of field programming and
updating.
Structure
The Program Memory has a capacity of 4K×16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which
can be setup in any location within the Program Memory, is addressed by a separate table pointer
register.
0FFFH
Reset
0000H
HT68FB240
0004H
0024H
Interrupt
Vector
16 bits
Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
Look-up Table
Any location within the Program Memory can be dened as a look-up table where programmers can
store xed data. To use the look-up table, the table pointer must rst be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
dene the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the "TABRD [m]" or "TABRDL [m]" instructions, respectively. When the instruction is executed,
the lower order table byte from the Program Memory will be transferred to the user defined
Data Memory register [m] as specified in the instruction. The higher order table data byte from
the Program Memory will be transferred to the TBLH special register. Any unused bits in this
transferred higher order byte will be read as 0.
The accompanying diagram illustrates the addressing data ow of the look-up table.
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USB Low Speed Flash MCU
Register T BLHUser S electe d
Register
High B yteLow B yte
Last p age o r
TBHP R egister
TBLP R egis te r
Data
Address
16 b its
Table Program Example
The following example shows how the table pointer and table data is dened and retrieved from the
microcontroller. This example uses raw table data located in the Program Memory which is stored
there using the ORG statement. The value at this ORG statement is "F00H" which refers to the start
address of the last page within the 4K Program Memory of the microcontroller. The table pointer
is setup here to have an initial value of "06H". This will ensure that the rst data read from the data
table will be at the Program Memory address "F06H" or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to the rst address of the present page if the
"TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal
to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is
executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Table Read Program Example
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
mov a, 06h ; initialise low table pointer - note that this address
mov tblp, a ; is referenced
mov a, 0Fh ; initialise high table pointer
mov tbhp, a
:
tabrd tempreg1 ; transfers value in table referenced by table pointer data at
program
; memory address F06H transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer data at
program
; memory address F05H transferred to tempreg2 and TBLH in this
; example the data 1AH is transferred to tempreg1 and data 0FH to
; register tempreg2
:
org F00h ; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
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USB Low Speed Flash MCU
In System Programming – ISP
The provision of Flash type Program Memory provides the user with a means of convenient and
easy upgrades and modications to their programs on the same device.
As an additional convenience, Holtek has provided a means of programming the microcontroller
in-system using a two-line USB interface. This provides manufacturers with the possibility of
manufacturing their circuit boards complete with a programmed or un-programmed microcontroller,
and then programming or upgrading the program at a later stage. This enables product manufacturers
to easily keep their manufactured products supplied with the latest program releases without removal
and re-insertion of the device.
The Program Memory can be programmed serially in-system using the USB interface, namely using
the UDN and UDP pins. The power is supplied by the UBUS pin. The technical details regarding the
in-system programming of the devices are beyond the scope of this document and will be supplied
in supplementary literature. The Flash Program Memory Read/Write function is implemented using
a series of registers.
Flash Memory Read/Write Page Size
The Flash memory page size is 32 words. The page and buer size are assigned as 32 words.
The following diagram illustrates the Read/Write page and buer assignment. The write buer is
controlled by the CLWB bit in the FRCR register. The CLWB bit can be set high to enable the Clear
Write Buer procedure, as the procedure is nished, this bit will be cleared to low by hardware.
The Write Buer is lled when the FWEN bit is set to high, when this bit is set high, the data in the
Write buer will be written to the Flash ROM, the FWT bit is used to indicate the writing procedure.
Setting this bit high and check if the write procedure is nished, this bit will be cleared by hardware.
The Read Byte can be assigned by the address. The FDEN is used to enable the read function and
the FRD is used to indicate the reading procedure. When the reading procedure is nished, this bit
will be cleared by hardware.
Device Page Size (Words) Write Buer (Words)
HT68FB240 (4K×16) 32 32
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USB Low Speed Flash MCU
Flash Memory
Write Buffer
Read one word to FD0L/FD0H
FARH FARL
FD0H FD0L
CLWB
Flash Memory
FARH FARL
FD0H FD0L
Write one word to FD0L/FD0H
Note: 1. Writing a data into high byte, which means the High/Low byte Data is written into Write
Buer, will cause the Flash memory address increased by one automatically and the new
address will be loaded to the FARH and FARL registers. However, the user can also ll the
new address by lling the data into FARH and FARL registers in the same page, then the
data will be written into the corresponding address.
2. If the address already reached the boundary of the ash memory, such as 11111b of the 32
words, at this moment, the address will not be increased and the address will stop at the last
address of that page and the writing data is invalid.
3. At this point, the user has to set a new address again to ll a new data.
4. If the data is writing using the write buer, the write buer will be cleared by hardware
automatically after the write procedure is ready in 2ms.
5. First time use the Write buer or renew the data in the Write buer, the user can use to
Clear buer bit (CLWB) to clear write buer.
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USB Low Speed Flash MCU
ISP Bootloader
The devices provide the ISP Bootloader function to upgrade the software in the Flash memory.
The user can select to use the ISP Bootloader application software provided by Holtek IDE tool or
to create his own Bootloader software. When the Holtek Bootloader software is selected, that will
occupy 0.5K words area in the Flash memory. The accompanyimg diagram illustrates the Flash
memory structure with Holtek Bootloader software.
Bootloader
Last Page
0000H
0D00H
0DFFH
HT68FB240
Flash Program Memory Registers
There are two address registers, four 16-bit data registers and one control register. The control
register is located in Bank 1 and the other registers are located in Bank 0. Read and Write operations
to the Flash memory are carried out in 16-bit data operations using the address and data registers
and the control register. Several registers control the overall operation of the internal Flash Program
Memory. The address registers are named FARL and FARH, the data registers are named FDnL and
FDnH, and the single control register is named FCR. As the FARL and FDnL registers are located
in Bank 0, they can be directly accessed in the same was as any other Special Function Register.
The FARH, FDnH, FCR and FRCR registers however, being located in Bank 1, cannot be addressed
directly and can only be read from or written to indirectly using the MP1 Memory Pointer and
Indirect Addressing Register, IAR1.
Program Memory Register List
Register
Name
Bit
7 6 5 4 3 2 1 0
FARL D7 D6 D5 D4 D3 D2 D1 D0
FARH — — — — D11 D10 D9 D8
FD0L D7 D6 D5 D4 D3 D2 D1 D0
FD0H D15 D14 D13 D12 D11 D10 D9 D8
FD1L D7 D6 D5 D4 D3 D2 D1 D0
FD1H D15 D14 D13 D12 D11 D10 D9 D8
FD2L D7 D6 D5 D4 D3 D2 D1 D0
FD2H D15 D14 D13 D12 D11 D10 D9 D8
FD3L D7 D6 D5 D4 D3 D2 D1 D0
FD3H D15 D14 D13 D12 D11 D10 D9 D8
FCR CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD
FRCR — — — FSWRST — — — CLWB
Table of contents
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