HYCON HY12P User manual

© 2015-2017 HYCON Technology Corp
www.hycontek.com
UG-HY12S65-V05_EN
HY12P Family
User’s Guide
Digital Multimeter
.

HY12S65 User’s Guide
Digital Multimeter
©
2015-2017
HYCON Technology Corp
www.hycontek.com
UG-HY12S65-V05_EN
page2
Table of Contents
1. READING GUIDANCE..............................................................................................................................6
1.1. About This User Guide..........................................................................................................................6
1.2. Terms and Definition .............................................................................................................................7
2. CPU...........................................................................................................................................................9
2.1. CPU Core..............................................................................................................................................9
2.2. Memory...............................................................................................................................................10
3. OSCILLATOR, CLOCK SOURCES AND POWER MANAGED MODES ..............................................24
3.1. Oscillator.............................................................................................................................................24
3.2. CPU and Peripheral Circuit Clock Sources ........................................................................................26
3.3. Register Description-Operating Clock Source Controller ...................................................................30
3.4. Power Managed and Operation Mode................................................................................................33
4. RESET.....................................................................................................................................................36
4.1. Reset Events Description....................................................................................................................37
4.2. Status Registers..................................................................................................................................38
5. INTERRUPT............................................................................................................................................41
5.1. Register Description-Interrupt.............................................................................................................42
6. HARDWARE MULTIPLIER.....................................................................................................................48
7. INPUT/OUTPUT PORT, I/O ....................................................................................................................49
7.1. PORT Related Register Introduction ..................................................................................................50
7.2. Buzzer.................................................................................................................................................51
7.3. Input/Output Port 1, I/O Port1.............................................................................................................52
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HY12S65 User’s Guide
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HYCON Technology Corp
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7.4. Input/Output Port 2, I/O Port2.............................................................................................................54
7.5. Input/Output Port 3 , I/O Port3............................................................................................................56
8. WATCH DOG TIMER, WDT....................................................................................................................58
8.1. WDT Manual.......................................................................................................................................58
8.2. Register Description-WDT ..................................................................................................................60
9. TIMER-A..................................................................................................................................................61
9.1. TMA Manual........................................................................................................................................62
9.2. Register Description -TMA..................................................................................................................63
10.TIMER-C..................................................................................................................................................64
10.1. Timer-C Manual...................................................................................................................................65
10.2. Register Description -TMC..................................................................................................................66
11. FREQUENCY GENERATOR, PWM/PFD...............................................................................................68
11.1. PFD Mode Manual..............................................................................................................................69
11.2. PWM Mode Manual.............................................................................................................................70
11.3. Register Description-PFD/PWM .........................................................................................................74
12. FREQUENCY COUNTER, CNT AND CMP PIN.....................................................................................75
12.1. Example of Calculation .......................................................................................................................76
12.2. Register Description- Frequency Counter...........................................................................................77
13. LCD .........................................................................................................................................................78
13.1. LCD Manual........................................................................................................................................79
13.2. LCD Output Waveform........................................................................................................................82
13.3. Register Description -LCD ..................................................................................................................87
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HY12S65 User’s Guide
Digital Multimeter
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HYCON Technology Corp
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14. ENHANCED UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER........................................89
14.1. EUART Manual ...................................................................................................................................90
14.2. Baud Rate Generator, BRG................................................................................................................91
14.3. Hardware Parity Check.......................................................................................................................94
14.4.EUART Asynchronous Mode ..............................................................................................................94
14.5. Register Description-EUART ............................................................................................................102
15. MULTI-FUNCTION COMPARATOR .....................................................................................................107
15.1. Scan Key Description........................................................................................................................108
15.2.Example Program .............................................................................................................................108
15.3. Register Description- Multi-function Comparator..............................................................................109
15.4. Low Power Voltage Detection Description........................................................................................ 110
16. CHARGE PUMP REGULATOR AND VDDA LDO ............................................................................... 111
16.1. Register Description- Charge Pump Regulator ................................................................................112
16.2. Power on Example Program.............................................................................................................112
17. AUTO RANGE DMM MULTI-FUNCTION NETWORK .........................................................................113
17.1. Voltage Reference Generator (VRG)................................................................................................ 114
17.2. Power System...................................................................................................................................117
17.3. AGND for Different Applications........................................................................................................117
17.4. Example Program ............................................................................................................................. 118
17.5. Analog Switch Network..................................................................................................................... 118
17.6. DMM Comparator Network ...............................................................................................................126
17.7. Pre-Filter, ADC Input MUX and Temperature Sensor .......................................................................128
18. ΣΔADC, LOW PASS FILTER, RMS CONVERTER AND PEAK HOLD...............................................131
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HY12S65 User’s Guide
Digital Multimeter
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18.1. Register Data Synchronization .........................................................................................................132
18.2. ΣΔADC..............................................................................................................................................132
18.3. Suggested Configurations for DMM Application...............................................................................135
18.4. Peak Hold..........................................................................................................................................138
18.5. Low Pass Filter & RMS Converter....................................................................................................138
19. DMM RANGE APPLICATION EXAMPLE ............................................................................................140
19.1. DC mV...............................................................................................................................................140
19.2. AC mV...............................................................................................................................................141
19.3. DCV...................................................................................................................................................142
19.4. ACV...................................................................................................................................................143
19.5. 500~50Kohm.....................................................................................................................................144
19.6. 500K~50Mohm..................................................................................................................................145
19.7. 5nF~500nF........................................................................................................................................146
19.8. 5uF~500uF........................................................................................................................................147
20. BUILD-IN EPROM.................................................................................................................................148
20.1. BIE instruction...................................................................................................................................149
20.2. Register Description-BIE...................................................................................................................152
21. REVISION RECORD.............................................................................................................................153
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HY12S65 User’s Guide
Digital Multimeter
©
2015-2017
HYCON Technology Corp
www.hycontek.com
UG-HY12S65-V05_EN
page6
1. Reading Guidance
1.1. About This User Guide
Attention:
1、HYCON Technology Corp. reserves the right to change the content of this datasheet
without further notice. For most up-to-date information, please constantly visit our
website: http://www.hycontek.com .
2、HYCON Technology Corp. is not responsible for problems caused by figures or
application circuits narrated herein whose related industrial properties belong to third
parties.
3、Specifications of any HYCON Technology Corp. products detailed or contained herein
stipulate the performance, characteristics, and functions of the specified products in the
independent state. We does not guarantee of the performance, characteristics, and
functions of the specified products as placed in the customer’s products or equipment.
Constant and sufficient verification and evaluation is highly advised.
4、Please note the operating conditions of input voltage, output voltage and load current
and ensure the IC internal power consumption does not exceed that of package
tolerance. HYCON Technology Corp. assumes no responsibility for equipment failures
that resulted from using products at values that exceed, even momentarily, rated values
listed in products specifications of HYCON products specified herein.
5、Notwithstanding this product has built-in ESD protection circuit, please do not exert
excessive static electricity to protection circuit.
6、Products specified or contained herein cannot be employed in applications which
require extremely high levels of reliability, such as device or equipment affecting the
human body, health/medical equipments, security systems, or any apparatus installed in
aircrafts and other vehicles.
7、Despite the fact that HYCON Technology Corp. endeavors to enhance product quality
as well as reliability in every possible way, failure or malfunction of semiconductor
products may happen. Hence, users are strongly recommended to comply with safety
design including redundancy and fire-precaution equipments to prevent any accidents
and fires that may follow.
8、Use of the information described herein for other purposes and/or reproduction or
copying without the permission of HYCON Technology Corp. is strictly prohibited.
.

HY12S65 User’s Guide
Digital Multimeter
©
2015-2017
HYCON Technology Corp
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UG-HY12S65-V05_EN
page7
1.2. Terms and Definition
1.2.1. Glossary
1KB 1KiloByte
ADC Analog to Digital Converter
Bit Bit
BOR Brown-Out Reset
BSR Bank Select Register
Byte Byte
CPU Central Processing Unit
DM Data Memory
FSR File Select Register
GPR General Purpose Register
HAO High Accuracy Oscillator
LNOP Low Noise OP AMP
LPO Low Power Oscillator
LSB Least Significant Bit
MEM Memory
MPM Main Program Memory
MSB Most Significant Bit
OTP One Time Program-EPROM
PC Program Counter
PPF PWM and PFD
SD18 Sigma-Delta ADC
SR Special Register
SRAM Static Random Access Memory
STK Stack
WDT Watch Dog Timer
WREG Work Register
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HY12S65 User’s Guide
Digital Multimeter
©
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HYCON Technology Corp
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UG-HY12S65-V05_EN
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1.2.2. Register Related Glossary
[ ] Register length
< > Register value
ABC[7:0] ABC register had 0 to 7bit
ABC<111> ABC register had 3bit and value had 111 of binary
ABC<11x> x：can be neglected, it can be set as 1 or 0
rw Read/Write
r Read only
r0 Read as 0
r1 Read as 1
w Write only
w0 Write as 0
w1 Write as 1
h0 cleared by Hardware
h1 set by Hardware
u0 cleared by User
u1 set by User
- Not use
! users are forbidden to change
u unchanged
x unknown
d depends on condition
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HY12S65 User’s Guide
Digital Multimeter
©
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HYCON Technology Corp
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2. CPU
2.1. CPU Core
CPU Core (H08A) adopts Harvard architecture concept in order to enhance execution
efficiency. Separate program memory and data memory incorporated in program memory
address increases user convenience of program writing.
CPU features include：
Isolated design frame of program memory and data memory upgrades instruction
execution speed and CPU efficiency.
Maximum address ability: 8KW for program memory and 256KB for data memory.
At most 67 instructions including 16-bit look-up-table, 8x8 hardware multiplier and
program memory block switch and stack control.
One instruction accomplished data movement from register A to register B without
changing work register data.
One instruction accomplished utmost 16-bit FSR register data movement and
address 8KW program memory look-up-table instruction.
Data memory operation includes Program Counter (PC), Status Register (Status)
and Stack Register (Stack) data movement.
Processor core is H08A core.
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HY12S65 User’s Guide
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2.2. Memory
Memory is composed by program memory (OTP) and data memory (SRAM). Memory
size differs from diverse part number; hence product data sheets should be read with extra
caution.
Program Memory：
Main Program Memory (MPM)
Program Counter (PC)
Stack (STK)
Data Memory：
Special Register (SR)
General Purpose Register (GPR)
Memory Related Registers：(x：Means it constitutes several registers).
PC[12:0] PCHSR[4:0],PCLATH[4:0],PCLATL[7:0]
TOS[12:0] TOSH[4:0],TOSL[7:0]
FSRx[8:0] FSRxH[8],FSRxL[7:0]
INDFx INDF0[7:0],INDF1[7:0]
POINCx POINC0[7:0], POINC1[7:0]
PODECx PODEC0[7:0], PODEC1[7:0]
PRINCx PRINC0[7:0], PRINC1[7:0]
PLUSWx PLUSW0[7:0], PLUSW1[7:0]
STKCN STKFL[0],STKOV[0],STKUN[0],STKPRT[2:0]
PSTATUS SKERR[0]
BSRCN BSR[0]
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HY12S65 User’s Guide
Digital Multimeter
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2.2.1. Program Memory
13
Program Counter
PC[10:0] ~ PC[12:0]
Stack
6 Level
Interrupt Vector
Blank read as “1”
Data Protect read as “0”
0004h
0005h
1FFFh
4KB：
6KB：
PC[11:0]
PC[12:0]
Main Program Memory
Program Memory Size
Table
Reset Vector 0000h
0001h
0003h
8KB：PC[12:0]
Figure 2-1 Program Memory Flame
2.2.1.1. Main Program Memory, MPM
The frame of main program memory is as follows：
Interrupt Vector
Reset Vector
Maximum Address ability starting from 0x00000h to 0x1FFFh, the entire capacity is
8191 characters and it will vary with different part numbers.
Before the IC being written, data type of all bits is 1. After programming, the bit will
show 1 or 0 according to the written data type. Please be noticed that if the emulation
software (HYIDE) compiling option has been configured the programming protection
function, all data type will only be read as 0.
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HY12S65 User’s Guide
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2.2.1.2. Program Counter, PC
Program Counter (PC) includes shift register PCSR and buffer register PCLAT,
as Figure 2-2 implicated.
Program Counter
PC[12:0]
PCSRH[4:0] PCLATL[7:0]
PCLATH[4:0]
Instruction
with PCL as
Destination
Data latch
4KB：PC[11:0]
PCLATL[7:0]
PCLATH[3:0]
6KB：PC[12:0]
PCLATL[7:0]
PCLATH[4:0]
8KB：PC[12:0]
PCLATL[7:0]
PCLATH[4:0]
Figure 2-2 Program Counter Frame
PC [12:0]1
To read PC[12:0], PCLATL[7:0] must be read first then to read PCLATH[4:0] in order to
obtain correct data.Any reverse order may result in incorrect data.
of the ICE equips with 13 bit data length and is composed by two
registers: PCSRH [4:0] and PCLATL [7:0]. PCLATL [7:0] and PCLATH [4:0] can be
directly read/written but PCSRH [4:0] cannot. Buffer register, PCLATH [4:0] must be
applied to carry out indirect read and write.
To write PC[12:0], PCLATH[4:0] must be written first then to write PCLATL[7:0]. Any
reverse order may result in incorrect data.
1Program memory address ability varies from every product scheme. Common capacities are 4KB (0xFFFh), 6KB (0x17FFh, HY12P65
emulation IC capacity).
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HY12S65 User’s Guide
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Example 2-1 Read/Write PCLAT Example Program
ORG 0000
JMP START
ORG 0004H
RETI
...
START: ;jump to 0109h
MVFF PCLATL,B1
INF PCLATH,F,ACCE
MVL 2
ADDF B1,W,ACCE
MVF PCLATL,F,ACCE
...
ORG 0109H
NOP ...
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HY12S65 User’s Guide
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2.2.1.3. Stack, STK
Stack, STK is mainly composed by Stack Index Control Register (STKCN),
Top-of-Stack Register (TOSx), Stack Layer Register (STKn2
Figure 2-3
), Stack Error Flag Bit (SKERR)
and Stack Error Reset Controller (SKRST[0]).As presented in .
Stack under flow TOS[12:0]=0,PC[12:0]=0x00000h
Stack null level STK0[12:0]=0
Stack 1 level STK1[12:0]
Stack 2 level STK2[12:0]
Stack n level STKn[12:0]
Stack over flow TOS[12:0]=X,PC[12:0]=X
STKPRT[2:0]
TOSL[7:0]
TOSH[4:0]
STKPRT=0
STKPRT=1
STKPRT=2
STKPRT=n
STKPRT=n,0≦n≦6
‘X’:unknown
TOSU[x:0]
4KB：TOS[11:0]
TOSL[7:0]
TOSH[3:0]
Program memory Size
TOS
Databus[7:0]
PC[12:0]
CALLx
INT RETx
STKUN[0]
STKOV[0]
STKFL[0]
STKERR[0]
STKRST[0]
Reset Chip
.
.
.
8KB：TOS[12:0]
TOSL[7:0]
TOSH[4:0]
Figure 2-3
Top-Of-Stack register, TOS[12:0] is 13 bit wide and is constituted by two registers,
TOSH[4:0] and TOSL [7:0]. When STKPRT[2:0]=<0>,TOS[12:0]=<0> null. When program
executes CALL instruction or an interrupt (INT) is acknowledged, stack pointer STKPRT[2:0]
will add 1 and write the PC address into current register, TOS[12:0]. When program
executes instruction RETx, STKPRT[2:0] will subtract 1. Before subtracting 1, TOS[12:0]
data will be written to PC[12:0]. After completion, STKPRT[2:0] will subtract 1 and change
current TOS[12:0] value.
Stack architecture diagram
There is no special regulation of reading register, TOS[12:0]. It can be read directly.
CALL instruction or interrupt (INT) can be utilized to write PC[12:0] data to register, TOS[12:0]. POP
instruction can discard current TOS[12:0] data and may result in 1 decrement of STKPRT[2:0] and may
load in new TOS[12:0] data.
STKFL[0] (Stack full), STKOV[0](Stack overflow) or STKUN[0](Stack underflow) may
happen during stack operation processes. Stack full is the early warning flag of stack
overflow, executes POP instruction this time can discard current TOS[12:0] data and
STKPRT[2:0] may subtract 1 and rewrite the newly appointed stack layer data into
TOS[12:0]. Users must be aware that when STKPRT[2:0]=<0>, executes POP instruction
may not lead to stack underflow, STKPRT[4:0] data can still be <0>. Therefore, users must
determine if it is blank stack.
Stack overflow and stack underflow may result in unexpected result of program
execution. If there is a necessary, it is suggested to restart the IC. In the processes of
2Stack layer register, STKn：Every stack layer has the same length data register as that of top-of-stack register, TOS. When stack index
STKPRT being designated, the content of data register will be sent to TOS.
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program development, stack reset control bit, SKRST[0]3
Stack Full: Configure STKFL[0] as <1>, PC[12:0] is not influenced.
can be configured as <1> through
software. When stack overflow or stack underflow take place, reset signal will be generated
and SKERR[0] will be set as <1> to restart the IC.
Stack Underflow: Configure STKUN[0] as <1>, PC[12:0] moves to 0x00000h, STKPRT
points to 0 Level. If SKRST[0] is set as <1>, reset signal will be aroused after stack
underflow and SKERR[0] may be configured as <1>, STKUN[0] will be <0> after reset.
Stack Overflow: Configure STKOV[0] as <1>, PC[12:0] is not influenced but STKPRT
remains at the last layer and new values may be written in. That is to say, the latest
written-in data may be saved after stack full. If SKRST[0] is configured as <1>, reset
signal may be generated after stack overflow and SKERR[0] may be set as <1>.
STKOV[0] will be set as <0> after reset.
Error: Configure SKERR[0] as <1>, stack error occurred. If SKRST[0] is configured <1>,
reset signal will be generated after stack overflow and SKERR[0] will be placed <1>.
STKUN[0] and STKOV[0] will be configured as <0> after reset.
If stack overflow that resulted from ignorance of stack full situation and stack underflow
that caused by continuously execute POP instruction happened, STKFL[0], STKOV[0]
and STKOV[0] must be configured as <1> in the same time. It is recommended to
implement flag clearance action in order to prevent program misjudgment.
To ignore the known stack overflow status when writing program, it is
suggested to use POP instruction to erase stack overflow flag, then to continue
implementing program. Otherwise, the Interrupt/Call instruction that generated from
stack overflow may cape current TOS[12:0] data.
3SKRST[0] is the generated reset signal control bit of stack error. Instead of direct read or write, it only can be set by developing
software at the program development stage. That is to say, whether to generate stack error reset signal must be determined at
program developing stage. If reset is chosen, after IC on powered, SKRST [0] is set as 1, the opposite situation is set as 0.
.

HY12S65 User’s Guide
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2.2.1.4. Register Description-Program Memory Controller
Address File Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 A-RESET i-RESET R/W
16H TOSH TOS[12] TOS[11] TOS[10] TOS[9] TOS[8]
...0 0000 ...0 0000 -,-,*,* *,*,*,*
17H TOSL
0000 0000 0000 0000 *,*,*,* *,*,*,*
18H STKPTR STKFL STKUN STKOV STKPRT[2] STKPRT[1] STKPRT[0]
000. .000 000. .000 r,rw0,rw0,- -,r,r,r
1AH PCLATH PC[12] PC[11] PC[10] PC[9] PC[8]
...0 0000 ...0 0000 -,-,*,* *,*,*,*
1BH PCLATL
0000 0000 0000 0000 *,*,*,* *,*,*,*
2CH PSTATUS PD TO IDLEB BOR SKERR 000d .0.. uduu .d.. rw0,rw0,rw0,rw0 -,rw0,-,-
PC Low Byte for PC<7:0>
“-”no use,“*”read/write,“w”write,“r”read,“r0”only read 0,“r1”only read 1,“w0”only write 0,“w1”omly write 1
“.”unimplemented bit,“x”unknown,“u”unchanged,“d”depends on condition
Top-of-Stack Low Byte (TOS<7:0>)
Table 2-1 Program Memory Control Register
TOSU/TOSH/TOSL：Top-Of-Stack Register
TOSH：TOS[12:8]
TOSL：TOS[7:0]
STKPTR：Stack Controller
STKFL：Stack full flag
1：Happened
0：Not happened
STKUN：Stack underflow flag
1：Happened
0：Not happened
STKOV：Stack overflow flag
1：Happened
0：Not happened
STKPRT[2:0]：Stack pointer register
110：the 6th
101：the 5
layer
th
layer
000：the 0 layer, TOS[12:0]=0x0000h
PCLATU/PCLATH/PCLATL：Program Counter, PC[12:0]
PCLATH：PC[12:8]
PCLATL：PC[7:0]
PSTATUS：Status Register
SKERR：Stack error generated reset flag
1：Happened
0：Not happened
.

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2.2.2. Data Memory, DM
Data Memory comprises Special Register (SR) and General Purpose Register (GPR),
every 256byte is a segment. Segment 0 is particular; include 128byte SR and 128byte GPR
respectively. Other segments only contain GPR, as illustrated in Figure 2-4.
General purpose RAM
128 byte
Special Register I
128 byte
000h
07Fh
080h
0FFh
General purpose RAM
128 byte
100h
17Fh
Unused
B
a
n
k
0
B
S
R
C
N
<
0
>
B
a
n
k
1
B
S
R
C
N
<
1
>180h
1FFh
Figure 2-4 Data Memory architecture diagram
.

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2.2.2.1. Memory and Instruction
H08A instruction set is quite flexible in their memory application, such as address
ability, hardware multiplier, look-up-table instruction, assistant function and arguments
definition. Only definition of instruction memory arguments is illustrated in this chapter.
Detail description of instruction arguments is depicted in Instruction chapter.
Instructions that contain address operation function of the instruction set have three
arguments, namely “f”, “d” and “a”.
“f” is Data or Data Memory Address
“d” is data storage place after operation. d=0 is saved in WREG register, d=1
is saved in Data Memory Register.
“a” is the designated memory operation segment；a=0 is operated in
segment 0, a=1 is operated in designated segment of BSRCN[0].
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2.2.2.2. Segment Select Control Register
Every 256 byte of data memory is set to be one segment (000h～0FFh). To read or
write address 0FFh register data, it is necessary to set correct segment control register
BSRCN [0] and instruction argument “a”. Description is as follows:
When a = 0, no matter register BSRCN [0] appoints to which segment, data memory
read/write instruction will only show in segment 0.
When a = 1, read/write instruction of H08A CPU Core to data memory will be in
compliance with the assigned segment of BSRCN[0].
General purpose RAM
128 byte
Special Register I
128 byte
000h
07Fh
080h
0FFh
General purpose RAM
128 byte
100h
17Fh
Unused
B
a
n
k
0
B
S
R
C
N
<
0
>
B
a
n
k
1
B
S
R
C
N
<
1
>
180h
1FFh
Example 2-2 Relation between Segment Selector Example Program And Data Memory
Ex：BSR[0]=0
V1 equ 081h ;
MVL 0AAh ; Put 0AAh into W
MVF V1,1,0 ; Write W value into
the 0x081h address of segment 0.
Ex：BSRCN[0]=1
V1 equ 07Fh
MVL 0AAh ; Put 0AAh into W
MVF V1,1,1 ; Write W value into
17 Fh address of Bank 1.
MVF f,d,a
‘a’=access
.

HY12S65 User’s Guide
Digital Multimeter
©
2015-2017
HYCON Technology Corp
www.hycontek.com
UG-HY12S65-V05_EN
page20
2.2.2.3. Special Register
Special register comprises CPU Core and peripheral function related registers, mainly
are control function registers and data returned registers. Undefined address or address bit
of data register will show 0 while reading and writing.
There are several instruction collocation registers contained in special register, only
two common types, working register (WREG) and indirect address register (FSR) are
introduced herein. Other special registers will be illustrated in depth in other chapter.
2.2.2.3.1. Working Register, WREG
Working register is abbreviated as W, which acts as the most frequently used register
for data movement, operation and diagnosis.
2.2.2.3.2. Indirect Address Register, FSR and INDF
File select register, FSR includes instruction register FSR0 [8:0], FSR1 [8:0] and index
register, INDF0 [7:0] and INDF1 [7:0]. Because of function similarity, only FSR0 is
explained in this chapter.
FSR0[8:0] can be separated into two registers, FSR0H[0] and FSR0L[7:0]. There is no
need to set up BSR [0] to address different segments. Through special instruction, only
applying one instruction can write 16-bit data.
NDF0[7:0] is index register that can read FSR0[8:0] appointed address data of data
memory.
H08A instruction set supports enhanced index register, the functions are characterized
as follows：
POINC0[7:0]：Events that ensued by read/write POINC0 [7:0] register by instruction.
The address value that FSR0 [8:0] pointed to will be sent back first.
Then pointer register, FSR0[8:0] value will add 1 and points to the next instruction.
PODEC0[7:0]：Events that followed by read/write PODEC0 [7:0] register by instruction.
The address value that FSR0 [8:0] pointed to will be sent back first.
Then pointer register, FSR0[8:0] value will subtract 1 and points to the last address.
PRINC0[7:0]：Events that followed by read/write PRINC0[7:0] register by instruction.
Pointer register FSR0[8:0] value will add 1 and points to the next address.
Current value of FSR0[8:0] appointed to address will be sent back.
PLUSW0 [7:0]：Events that ensued by read/write PLUSW0 [7:0] register by instruction.
Add pointer register, FSR0[8:0] value together with working register, W value.
Send back current FSR0[8:0] appointed address value. The register W value will be±128d.
2.2.2.3.3. General Purpose Register, GPR
General purpose register, GPR is the free area for users to conduct data storage,
operation, flag bit setup…etc.
.