Hynix Semiconductor GMS90C320 series User manual

HYNIX SEMICONDUCTOR INC.
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS90C320
User’s Manual (Ver. 1.2)
查询GMS90C320供应商 捷多邦，专业PCB打样工厂，24小时加急出货

Version 1.2
Published by
MCU Application Team
Copy right
 
2001 Hynix semiconductor, All right reserved.
Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Repre-
sentatives listed at address directory.
Hynix semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconductor is in no
way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
REVISION HISTORY
VERSION 1.2 (Oct. 2000) This book
Correct the pin number of 44-MQFP package type on page 6.
VERSION 1.1 (Oct. 1999) Before version

GMS90C320
OCT. 2000 Ver 1.2
Device Naming Structure
H(G)MS90X320 Frequency
Package Type
Blank: 24MHz
Blank:
PL:
Q:
40PDIP
44PLCC
44MQFP
Enhanced ROM-less version
Operating Voltage
C:
L: Normal voltage Low voltage
Hynix semiconductor MCU
XXXX
MCU Series
40: 40MHz
50: 50MHz

GMS90C320
OCT. 2000 Ver 1.2
GMS90C320 ordering information
Operating
Voltage (V) Device Name ROM size (bytes) RAM size (bytes) Operating max. Frequency (MHz) Package Type
4.25~5.5
GMS90C320 40
GMS90C320 PL40
GMS90C320 Q40 ROM-less 256 40 40PDIP
44PLCC
44MQFP
GMS90C320 50
GMS90C320 PL50
GMS90C320 Q50 ROM-less 256 50 40PDIP
44PLCC
44MQFP
2.7~5.5 GMS90L320 GMS90L320 PL
GMS90L320 Q ROM-less 256 24 40PDIP
44PLCC
44MQFP

GMS90C320
OCT. 2000 Ver 1.2 1
GMS90C320/L320
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
ROM-less Version for 90C52
Features
• Fully compatible to standard MCS-51 microcontroller
• Versions for 40/50 MHz operating frequency
• Low voltage version for 24MHz operating frequency
• 256 bytes of on-chip data RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Three 16-bit Timers/Counters (Timer 2 with up/down counter feature)
•USART
• Six interrupt sources, two priority levels
• Power saving Idle and power down mode
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
The GMS90C320 described in this document is compatible with the standard 80C32 can be used for all present standard
80C32 applications.
Operating Voltage (V) Device Name ROM RAM Operating
Frequency (MHz)
4.25~5.5 GMS90C320 ROM-less 256 ×
××
×8bit 40/50
2.7~5.5 GMS90L320 ROM-less 256 ×
××
×8bit 24
RAM
256 x 8
T0
T1
ROM-less
CPU 8-BIT
USART
PORT0
PORT3
PORT1
PORT2
T2
I/O
I/O
I/O
I/O

GMS90C320
2OCT. 2000 Ver 1.2
44-PLCC Pin Configuration
(top view)
(P-LCC-44)
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
N.C.
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.4
P1.3
P1.2 P1.1/T2EX P1.0/T2 N.C. V
CC
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3
WR/P3.6
RD/P3.7
XTAL2 XTAL1
V
SS
N.C.
P2.0/A8 P2.1/A9
P2.2/A10 P2.3/A11 P2.4/A12
P1.5
P1.6
P1.7
RESET
RxD/P3.0
N.C.
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2 1
44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28

GMS90C320
OCT. 2000 Ver 1.2 3
40-PDIP Pin Configuration
(top view)
(P-DIP-40)
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE
PSEN
P1.6
P1.7
RESET
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
1
2
3
4
5
6
XTAL2
XTAL1
V
SS
18
19
20
V
CC
40
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
28
27
26
25
24
23
22
21

GMS90C320
4OCT. 2000 Ver 1.2
44-PLCC Pin Configuration
(top view)
(P-MQFP-44)
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
N.C.
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.4
P1.3
P1.2 P1.1/T2EX P1.0/T2 N.C. V
CC
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3
WR/P3.6
RD/P3.7
XTAL2 XTAL1
V
SS
N.C.
P2.0/A8 P2.1/A9
P2.2/A10 P2.3/A11 P2.4/A12
P1.5
P1.6
P1.7
RESET
RxD/P3.0
N.C.
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
44 43 42 41 40 39
38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22

GMS90C320
OCT. 2000 Ver 1.2 5
Logic Symbol
Port 0
XTAL1
XTAL2
RESET
EA
ALE
PSEN
8-bit Digital I/O
Port 1
8-bit Digital I/O
Port 2
8-bit Digital I/O
Port 3
8-bit Digital I/O
V
CC
V
SS

GMS90C320
6OCT. 2000 Ver 1.2
Pin Definitions and functions
Symbol Pin Number Input/
Output Function
P-LCC-44 P-DIP-40 P-MQFP-
44
P1.0-P1.7 2-9 1-8 40-44,
1-3 I/O Port1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-up
resistors and can be used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of the pulls-ups
(I
IL
, in the DC characteristics). Pins P1.0 and P1.1 also. Port 1
also receives the low-order address byte during program memory
verification. Port1 also serves alternate functions of Timer 2.
2
31 240 41 P1.0/T2: Timer/counter 2 external count input P1.1/T2EX: Timer/counter 2 trigger input
P3.0-P3.7 11,13-
19 10-17 5, 7- 13 I/O Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state they can be used as inputs. As inputs,
port 3 pins being externally pulled low will source current (I
IL
,in
the DC characteristics) because of internal pulls-up resistors. Port
3 also serves the special features of the 80C51 family, as listed
below.
11 10 5 P3.0/RxD receiver data input (asynchronous) or data input
output (synchronous) of the serial interface 0
13 11 7 P3.1 / TxD transmitter data output (asynchronous) or clock
output (synchronous) of the serial interface 0
14 12 8 P3.2 / INT0 interrupt 0 input /timer0gatecontrol
15 13 9 P3.3 / INT1 interrupt 1 input /timer1gatecontrol
16 14 10 P3.4 / T0 counter 0 input
17 15 11 P3.5 / T1 counter 1 input
18 16 12 P3.6 / WR the write control signal latches the data byte from
port 0 into the external data memory
19 17 13 P3.7 / RD the read control signal enables the external data
memory to port 0
XTAL2 20 18 14 O XTAL2
Output of the inverting oscillator amplifier
XTAL1 21 19 15 I XTAL1
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
To drive the device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are no require-
ments on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is divided down by a divide-
by-two flip-flop. Minimum and maximum high and low times as
well as rise fall times specified in the AC characteristics must be
observed.

GMS90C320
OCT. 2000 Ver 1.2 7
P2.0-P2.7 24-31 21-28 18-25 I/O Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal
pull-up resistors and can be used as inputs. As inputs, port 2 pins
that are externally pulled low will source current because of the
pulls-ups (I
IL
, in the DC characteristics). Port 2 emits the high-
order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it uses strong
internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @Ri), port 2 emits
the contents of the P2 special function register.
PSEN 32 29 26 O The Program Store Enable
The read strobe to external program memory when the device is
executing code from the external program memory. PSEN is acti-
vated twice each machine cycle, except that two PSEN activation
are skipped during each access to external data memory. PSEN
is not activated during fetches from internal program memory.
RESET 10 9 4 I RESET
A high level on this pin for two machine cycles while the oscillator
is running resets the device. An internal diffused resistor to V
SS
permits power-on reset using only an external capacitor to V
CC
.
ALE 33 30 27 O The Address Latch Enable
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted
at a constant rate of 1/6 the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory.
EA 35 31 29 I External Access Enable
EA must be external held low to enable the device to fetch code
from external program memory locations 0000
H
to FFFF
H
.IfEAis
held high, the device executes from internal program memory
unless the program counter contains an address greater than its
internal memory size.
P0.0-P0.7 43-36 39-32 37-30 I/O Port 0
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high-impedance
inputs. Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s.
Port 0 also outputs the code bytes during program verification in
the GMS97C5x. External pull-up resistors are required during
program verification.
V
SS
22 20 16 - Circuit ground potential
V
CC
44 40 38 - Supply terminal for all operating modes
N.C. 1,12,
23,34 -6,17, 28,39 -No connection
Symbol Pin Number Input/
Output Function
P-LCC-44 P-DIP-40 P-MQFP-
44

GMS90C320
8OCT. 2000 Ver 1.2
Function Description
The GMS90 series is fully compatible to the standard 8051 microcontroller family.
It is compatible with the standard 80C32. While maintaining all architectural and operational characteristics of the standard
80C32, the GMS90C320 incorporates some enhancements in the Timer 2 unit.
Figure 1 shows a block diagram of the GMS90C320
Figure 1 Block Diagram of the GMS90C320
RAM
256 x 8
Port 0 Port 0
8-bit Digital I/O
Port 1 Port 1
8-bit Digital I/O
Port 2 Port 2
8-bit Digital I/O
Port 3 Port 3
8-bit Digital I/O
CPU
Timer 0
Timer 1
Timer 2
Interrupt Unit
Serial Channel
OSC & Timing
XTAL1
XTAL2
RESET
EA
ALE
PSEN

GMS90C320
OCT. 2000 Ver 1.2 9
CPU
The GMS90C320 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD
arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set con-
sisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are
executed in 1.0µs.
Special Function Register PSW
Reset value of PSW is 00
H.
Bit Function
CY Carry Flag
AC Auxiliary Carry Flag (for BCD operation)
F0 General Purpose Flag
RS1
0
0
1
1
RS0
0
1
0
1
Register Bank select control bits
Bank 0 selected, data address 00
H
-07
H
Bank 1 selected, data address 08
H
-0F
H
Bank 2 selected, data address 10
H
-17
H
Bank 3 selected, data address 18
H
-1F
H
OV Overflow Flag
F1 General Purpose Flag
P Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/
even number of “one” bits in the accumulator, i.e. even parity.
MSB LSB
BitNo.76543210
Addr. D0
H
CY AC F0 RS1 RS2 OV F1 P PSW

GMS90C320
10 OCT. 2000 Ver 1.2
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the special function register
area.
The 27 special function registers (SFR) include pointers and registers that provide an interface between the CPUand the other
on-chip peripherals. There are also 128 directly addressable bits within the SFR area.
All SFRs are listed in Table 1,Table 2,andTable 3.
In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the
functional blocks of the GMS90C320. Table 3 illustrates the contents of the SFRs.
Table 1
Special Function Registers in Numeric Order of their Addresses
Address Register Contents after
Reset Address Register Contents after Reset
80
H
81
H
82
H
83
H
84
H
85
H
86
H
87
H
P01)
SP
DPL
DPH
reserved
reserved
reserved
PCON
1) : Bit-addressable Special Function Register
FF
H
07
H
00
H
00
H
XX
H
2)
XX
H
2)
XX
H
2)
0XXX0000
B
2)
2) : X means that the value is indeterminate and the location is reserved
A0
H
A1
H
A2
H
A3
H
A4
H
A5
H
A6
H
A7
H
P21)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FF
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
88
H
89
H
8A
H
8B
H
8C
H
8D
H
8E
H
8F
H
TCON1)
TMOD
TL0
TL1
TH0
TH1
reserved
reserved
00
H
00
H
00
H
00
H
00
H
00
H
XX
H
2)
XX
H
2)
A8
H
A9
H
AA
H
AB
H
AC
H
AD
H
AE
H
AF
H
IE1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0X000000
B
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
90
H
91
H
92
H
93
H
94
H
95
H
96
H
97
H
P11)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FF
H
00
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
B0
H
B1
H
B2
H
B3
H
B4
H
B5
H
B6
H
B7
H
P31)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FF
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
98
H
99
H
9A
H
9B
H
9C
H
9D
H
9E
H
9F
H
SCON1)
SBUF
reserved
reserved
reserved
reserved
reserved
reserved
00
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
B8
H
B9
H
BA
H
BB
H
BC
H
BD
H
BE
H
BF
H
IP1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX000000
B
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)

GMS90C320
OCT. 2000 Ver 1.2 11
Table 1
Special Function Registers in numeric order of their addresses (cont’d)
Address Register Contents after
Reset Address Register Contents after Reset
C0
H
C1
H
C2
H
C3
H
C4
H
C5
H
C6
H
C7
H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
E0
H
E1
H
E2
H
E3
H
E4
H
E5
H
E6
H
E7
H
ACC1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
C8
H
C9
H
CA
H
CB
H
CC
H
CD
H
CE
H
CF
H
T2CON1)
T2MOD
RC2L
RC2H
TL2
TH2
reserved
reserved
00
H
XXXXXXX0
B
2)
00
H
00
H
00
H
00
H
XX
H
2)
XX
H
2)
E8
H
E9
H
EA
H
EB
H
EC
H
ED
H
EE
H
EF
H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
D0
H
D1
H
D2
H
D3
H
D4
H
D5
H
D6
H
D7
H
PSW1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1) : Bit-addressable Special Function Register
00
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
2) : X means that the value is indeterminate and the location is reserved
F0
H
F1
H
F2
H
F3
H
F4
H
F5
H
F6
H
F7
H
B1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00
H
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
D8
H
D9
H
DA
H
DB
H
DC
H
DD
H
DE
H
DF
H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
F8
H
F9
H
FA
H
FB
H
FC
H
FD
H
FE
H
FF
H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)
XX
H
2)

GMS90C320
12 OCT. 2000 Ver 1.2
Table 2
Special Function Registers - Functional Blocks
Block Symbol Name Address Content
after Reset
CPU ACC
B
DPH
DPL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
E0
H
1)
F0
H
1)
83
H
82
H
D0
H
1)
81
H
1) Bit-addressable Special Function Registers
00
H
00
H
00
H
00
H
00
H
07
H
Interrupt System IE
IP Interrupt Enable Register Interrupt Priority Register A8
H
1)
B8
H
1) 0X000000
B
2)
XX000000
B
2)
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks
Ports P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
80
H
1)
90
H
1)
A0
H
1)
B0
H
1)
FF
H
FF
H
FF
H
FF
H
Serial Channels PCON
SBUF
SCON
Power Control Register
Serial Channel Buffer Register
Serial Channel 0 Control Register
87
H
99
H
98
H
1)
0XXX0000
B
2)
XX
H
3)
00
H
3) X means that the value is indeterminate and the location is reserved
Timer 0 / Timer 1 TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88
H
1)
8C
H
8D
H
8A
H
8B
H
89
H
00
H
00
H
00
H
00
H
00
H
00
H
Timer 2 T2CON
T2MOD
RC2H
RC2L
TH2
TL2
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload Capture Register, High Byte
Timer 2 Reload Capture Register, Low Byte
Timer 2, High Byte
Timer 2, Low Byte
C8
H
1)
C9
H
CB
H
CA
H
CD
H
CC
H
00
H
XXXXXXX0
B
2)
00
H
00
H
00
H
00
H
Power Saving
Modes PCON Power Control Register 87
H
0XXX0000
B
2)

GMS90C320
OCT. 2000 Ver 1.2 13
Table 3
Contents of SFRs, SFRs in Numeric Order
Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
80
H
P0
81
H
SP
82
H
DPL
83
H
DPH
87
H
PCON SMOD - - - GF1 GF0 PDE IDLE
88
H
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
89
H
TMOD GATE C/T M1 M0 GATE C/T M1 M0
8A
H
TL0
8B
H
TL1
8C
H
TH0
8D
H
TH1
90
H
P1
98
H
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI
99
H
SBUF
A0
H
P2
A8
H
IE EA - ET2 ES ET1 EX1 ET0 EX0
B0
H
P3
B8
H
IP - - PT2 PS PT1 PX1 PT0 PX0
C8
H
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
C9
H
T2MOD -------DCEN
SFR bit and byte addressable
SFR not bit addressable
-This bit location is reserved.

GMS90C320
14 OCT. 2000 Ver 1.2
Table 3
Contents of SFRs, SFRs in Numeric Order (cont’d)
Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CA
H
RC2L
CB
H
RC2H
CC
H
TL2
CD
H
TH2
D0
H
PSW CY AC F0 RS1 RS0 OV F1 P
E0
H
ACC
F0
H
B
SFR bit and byte addressable
SFR not bit addressable
-This bit location is reserved.

GMS90C320
OCT. 2000 Ver 1.2 15
Timer/Counter0and1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
In the “timer” function (C/T = “0”) the register is incremented every machine cycle. Therefore the count rate is .
In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin
(P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is . External inputs
INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements.
Figure 2 illustrates the input clock logic.
Figure 2 Timer/Counter 0 and 1 Input Clock Logic
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode Description TMOD Input Clock
GATE C/T M1 M0 Internal External
(Max.)
0 8-bit timer/counter with a
divide-by-32 prescaler XX00
1 16-bit timer/counter XX01
2 8-bit timer/counter with 8-bit
autoreload XX10
3 Timer/counter 0 used as one
8-bit timer/counter and one 8-
bit timer
Timer 1 stops
XX11
ƒOSC
12 32×
------------------- ƒOSC
24 32×
-------------------
ƒOSC
12
----------------ƒOSC
24
----------------
ƒOSC
12
----------------ƒOSC
24
----------------
ƒOSC
12
----------------ƒOSC
24
----------------
ƒOSC 12⁄
ƒOSC 24⁄
f
OSC
÷12
C/T
TMOD
0
1
GATE
TMOD
TR 0/1
TCON
P3.4/T0
P3.5/T1
max. f
OSC
/24
P3.2/INT0
P3.3/INT1
Timer 0/1
Input Clock
Control
ƒOSC 12⁄

GMS90C320
16 OCT. 2000 Ver 1.2
Timer 2
Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which
is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5.
1Note: ↓= falling edge
Table 5
Timer/Counter 2 Operating Modes
Mode
T2CON T2MO
D
DECN T2CON
EXEN P1.1 T2EX Remarks
Input Clock
RxCLK
or
TxCLK
CP/
RL2 TR2 Internal External
(P1.0/T2)
16-bit Auto-
reload 0 0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
X
X
X
↓
0
1
reload upon overflow
reload trigger (falling edge)
Down counting
Up counting
max.
16-bit
Capture 0
0
1
1
1
1
X
X
0
1
X
↓
16-bit Timer/Counter (only
up-counting)
capture
TH1, TL2 → RC2H, RC2L max.
Baud Rate
Generator 1
1
X
X
1
1
X
X
0
1
X
↓
no overflow interrupt request
(TF2)
extra external interrupt
(“Timer 2”)
max.
off X X 0 X X X Timer 2 stops - -
ƒOSC
12
----------------ƒOSC
24
----------------
ƒOSC
12
----------------ƒOSC
24
----------------
ƒOSC
12
----------------ƒOSC
24
----------------