Atmel AT43DK380 User manual

AT43DK380 USB Host/Function
Development Kit
.......................................................................................................
User Guide for Revision 1.0

AT43DK380 USB Host/Function Dev. Kit User Guide i
3485A–USB–7/04
Table of Contents
Section 1
Introduction ...........................................................................................1-1
1.1 Development Kit Packages and Features.................................................1-1
Section 2
Getting Started......................................................................................2-1
2.1 Electrostatic Warning ................................................................................2-1
2.2 Unpacking the System ..............................................................................2-1
2.3 System Requirements...............................................................................2-1
2.4 Connecting the Hardware .........................................................................2-2
2.5 Installing AT43DK380 and Starting Up the USB Clinic .............................2-2
2.6 Testing the Hardware................................................................................2-3
Section 3
Hardware Description ...........................................................................3-1
3.1 Description of the Main Development Platform.........................................3-1
3.1.1 AT43DK380 Processor Interface Connector ......................................3-2
3.1.2 Jumper Settings..................................................................................3-5
3.2 AT43DC380-PDC1 Processor Daughter Card..........................................3-7
3.2.1 PDC1 Jumper Settings .......................................................................3-7
3.3 AT43DC380-PDC2 Processor Daughter Card..........................................3-8
3.3.1 PDC2 Jumper Settings .......................................................................3-8
3.4 AT43DK380 Main Development Platform to PDC Connection .................3-9
Section 4
USB Clinic.............................................................................................4-1
4.1 Main Menu ................................................................................................4-1
4.2 Output Window .........................................................................................4-2
4.2.1 Command/Status Window ..................................................................4-2
4.2.2 User Program Output Window............................................................4-2
4.3 Connection................................................................................................4-2
4.3.1 Test Connectivity ................................................................................4-3
4.3.2 Check Device Enumerated.................................................................4-3
4.4 Download Code ........................................................................................4-3
4.5 Memory .....................................................................................................4-5
4.5.1 Fill Memory .........................................................................................4-5
4.5.2 Read Memory .....................................................................................4-5

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ii AT43DK380 USB Host/Function Dev. Kit User Guide
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4.6 Enumeration..............................................................................................4-5
4.6.1 Get Device Descriptor ........................................................................4-6
4.6.2 Get Configuration Descriptor ..............................................................4-6
4.6.3 Get String Descriptor..........................................................................4-7
4.6.4 Set Configuration................................................................................4-7
4.6.5 Set Interface .......................................................................................4-7
4.7 Data Transfer ............................................................................................4-8
4.7.1 Get ISO Data ......................................................................................4-8
4.7.2 Send ISO Data ...................................................................................4-8
4.7.3 Get Data .............................................................................................4-8
4.7.4 Send Data...........................................................................................4-8
4.7.5 Control Transfer..................................................................................4-9
4.7.6 Custom Transfer.................................................................................4-9
4.8 Port Features ..........................................................................................4-10
4.8.1 Set Port Feature ...............................................................................4-10
4.8.2 Clear Port Feature ............................................................................4-10
4.9 Device State Control ...............................................................................4-11
4.9.1 Reset Device ....................................................................................4-11
4.9.2 Suspend Device ...............................................................................4-11
4.9.3 Resume Device ................................................................................4-11
4.10 Miscellaneous Notes...............................................................................4-11
Section 5
Building Firmware for the AT43DK380 Development Kit...................... 5-1
5.1 Sample Directory and File Structure .........................................................5-1
5.1.1 USBP ARM Project Guide ..................................................................5-2
5.1.2 “Make” Project ....................................................................................5-4
5.2 ADS Settings.............................................................................................5-5
5.3 Modifying a Sample Application................................................................5-8
Section 6
Generating Hex Files for Flash Mode in the AT43USB380 Development
Platform with ADS................................................................................. 6-1
6.1 Introduction ...............................................................................................6-1
6.2 Procedure .................................................................................................6-1
Section 7
Converting Between FLASH and ICE Mode and Download Mode....... 7-1
7.1 Introduction ...............................................................................................7-1
7.2 Converting to Flash Mode from ICE Mode................................................7-1
7.3 Converting to Flash Mode from Download Mode......................................7-3
7.4 Converting to Download Mode from ICE Mode ........................................7-3

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AT43DK380 USB Host/Function Dev. Kit User Guide iii
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7.5 Converting to Download Mode from Flash Mode......................................7-4
7.6 Converting to ICE Mode from Flash Mode................................................7-4
7.7 Converting to ICE Mode from Download Mode.........................................7-4
7.8 Summary...................................................................................................7-4
Section 8
Technical Support.................................................................................8-1
Section 9
Appendices ...........................................................................................9-1
9.1 AT43DK380 Schematics...........................................................................9-1
9.1.1 AT43DK380 Main Development Platform Schematics .......................9-1
9.1.2 AT43DK380-PDC1 Schematic ...........................................................9-6
9.1.3 AT43DK380-PDC2 Schematic ...........................................................9-7
9.2 AT43DK380 Bill of Materials (BOM)..........................................................9-8
9.2.1 AT43DK380 Main Development Platform BOM .................................9-8
9.2.2 AT43DK380-PDC1 BOM ..................................................................9-11
9.2.3 AT43DK380-PDC2 BOM ..................................................................9-12
9.3 AT43DK380 Main Development Platform CPLD VHDL Code Ref..........9-13

Table of Contents
iv AT43DK380 USB Host/Function Dev. Kit User Guide
3485A–USB–7/04

AT43DK380 USB Host/Function Dev. Kit User Guide 1-1
3485A–USB–7/04
Section 1
Introduction
Congratulations on your purchase of the AT43DK380 Development Kit. The
AT43DK380 Main Development Platform is the AT43USB380 Host/Function/OTG Pro-
cessor Development Platform to be used with a user target processor board or the
AT43DK380 Processor Daughter Cards (PDCs). It is designed to allow real-time firm-
ware development and evaluation of the AT43USB380 USB Host/Function/OTG
Processor.
1.1 Development Kit
Packages and
Features
The AT43DK380 Development Kit comes in the following packages:
AT43DK380-BD1 AT43USB380 Development Kit bundled set 1:
– AT43DK380 Main Development Platform with pre-programmed flash set for
the PDC1 32-bit ARM7TDMI®Processor
– AT43DK380-PDC1 32-bit ARM7TDMI Processor Daughter Card
– Pre-compiled ANSI-C compliant USB Firmware Libraries including USB Host
Stack and Device Class Drivers for the PDC1 32-bit ARM7TDMI Processor
– USB Clinic In-Circuit Emulation tool
AT43DK380-BD2 AT43USB380 Development Kit bundled set 2:
– AT43DK380 Main Development Platform with pre-programmed flash set for
the PDC2 AT91R40008 16-bit ARM7TDMI Processor
– AT43DK380-PDC2 AT91R40008 16-bit ARM7TDMI Processor Daughter Card
– Pre-compiled ANSI-C compliant USB Firmware Libraries including USB Host
Stack and Device Class Drivers for the PDC2 AT91R40008 16-bit ARM7TDMI
Processor
– USB Clinic In-Circuit Emulation tool
AT43DK380-PDC1 32-bit ARM7TDMI Processor Daughter Card set:
– AT43DK380-PDC1 32-bit ARM7TDMI Processor Daughter Card
– Pre-programmed flash set for the PDC1 32-bit ARM7TDMI Processor
– Pre-compiled ANSI-C compliant USB Firmware Libraries including USB Host
Stack and Device Class Drivers for the PDC1 32-bit ARM7TDMI Processor
– USB Clinic In-Circuit Emulation tool

Introduction
1-2 AT43DK380 USB Host/Function Dev. Kit User Guide
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AT43DK380-PDC2 Atmel AT91R40008 16-bit ARM7TDMI Processor Daughter Card
set:
– AT43DK380-PDC2 AT91R40008 16-bit ARM7TDMI Processor Daughter Card
– Pre-programmed flash set for the PDC2 AT91R40008 16-bit ARM7TDMI
Processor
– Pre-compiled ANSI-C compliant USB Firmware Libraries including USB Host
Stack and Device Class Drivers for the PDC2 AT91R40008 16-bit ARM7TDMI
Processor
– USB Clinic In-Circuit Emulation tool
A complete development kit contains a Main Development Platform and a Daughter
Card. The pre-programmed flash set and the software tools are functional only for the
complete development kit. We recommend purchasing a bundled set for initial
development.
The AT43DK380 Main Development Platform consists of the following features:
– AT43USB380 USB Host/Function/OTG Processor
– 1M Bytes Flash ROM
– 2M Bytes Static RAM
– USB MINI - A/B ports
– 4-Ports USB Hub
– OTG Interface Charge Pump
– RS-232 Serial Port
– 8/16/32-bit System Processor Interface
– 64 I/Os CPLD
– EEPROM Connector
– Reset buttOn
– Power Indicator LEDs
– In-System Firmware Programming Capability
Please register at http://www.atmel.com/products/usb/forms/softwareg.asp to
access and be informed of the latest up-to-date information on new USB software, doc-
umentation releases and tool upgrades.

AT43DK380 USB Host/Function Dev. Kit User Guide 2-1
3485A–USB–7/04
Section 2
Getting Started
2.1 Electrostatic
Warning
The AT43DK380 Development Platform is shipped in protective anti-static packaging.
The board must not be subjected to high electrostatic potentials. A grounding strap or
similar protective device should be worn when handling the board. Avoid touching the
component pins or any other metallic elements.
2.2 Unpacking the
System
The bundled development kit is supplied with the following:
AT43DK380 Main Development Platform
AT43DK380 Processor Daughter Card
Female-female DB9 Null-modem Cable
2m Fully Rated USB Cable
5V regulated power supply
Atmel USB CD-ROM with Software and Documentation
CD-ROM of Atmel Products
Please contact your local Atmel distribution or E-mail [email protected] if any of the
aforementioned items is missing from the package.
2.3 System
Requirements
The minimum hardware and software requirements are:
486 Processor (Pentium®is recommended)
128 MB RAM
10 MB Free Hard Disk Space
Windows®98/2000/ME/XP
RS-232 Port (COM port)
In order to use the AT43DK380 Development Platform with the tools provided, one of
the Processor Daughter Cards (PDC) needs to be properly configured and plugged in.
The hardware test will only work if the PDC is plugged in.

Getting Started
2-2 AT43DK380 USB Host/Function Dev. Kit User Guide
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2.4 Connecting the
Hardware
Atmel has taken great care in creating a reliable demonstration kit for its customers. In
order to ensure proper operation, the supplied components in the kit must be used in the
setup as shown in Figure 2-1. Atmel does NOT recommend substitution of these
components.
Figure 2-1. Connection to the AT43DK380
Connect the AT43DK380 Evaluation Board as follows:
1. Connect the serial cable from J5 on the evaluation board to a COM port on the
PC.
2. Connect the AC input connector of the power supply to an AC wall outlet
(110 VAC).
3. Connect the DC output connector of the power supply to J1 on the evaluation
board.
2.5 Installing
AT43DK380 and
Starting Up the
USB Clinic
To install the AT43DK380:
1. Insert the “Atmel AT43DK380” CD into the CD-ROM drive of the PC or notebook,
double-click on the MSI file and follow the instructions.
2. After installation, the AT43USB380 documents, firmware, and software should
be installed on the C:\Program Files\ATMEL USB\AT43DK380_Date, if the
default installation directory is used. One of the software programs installed is
the USB Clinic. It is an integrated diagnostic and debugging tool that provides
communication between the AT43DK380 and the PC. Please refer to Section 4
of this User's Guide for detailed description of this tool.
3. To invoke the USB Clinic program from desktop go to Start >Programs > Atmel
USB Clinic >Atmel USB Clinic. The screen in Figure 2-2 will appear.
J1 J5
Power Supply
(5VDC)
110VAC
Outlet
AT43USB380DK Evaluation Board
RS-232
Cable

Getting Started
AT43DK380 USB Host/Function Dev. Kit User Guide 2-3
3485A–USB–7/04
Figure 2-2. USB Clinic - Main Menu
2.6 Testing the
Hardware
From the USB Clinic Main Menu click Connection (Figure 2-3 and Figure 2-4 will
appear). The Connection button allows testing of the RS-232 serial port and the
AT43DK380 Development Platform connection. Prior to going to the Connection menu,
please make sure that the AT43DK380 is physically connected to the PC with the sup-
plied serial cable or any standard serial cable.
Figure 2-3. USB Clinic - Connection

Getting Started
2-4 AT43DK380 USB Host/Function Dev. Kit User Guide
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Figure 2-4. COM Port Availability
The USB Clinic automatically detects and displays the availability of COM ports from
COM1 to COM4 in the Connection window. Users can use any available COM port by
simply selecting the desired COM port and then clicking the Connect to Target button
to open the selected COM port. To verify connectivity between the selected COM port
and the AT43DK380 Development Platform, click on Test Connectivity with Target
and look for Connection verified in the Output Window (see Figure 2-5). The Test
Connectivity with Target also checks the AT43DK380 firmware revision to see if it sup-
ports the current USB Clinic version.
Figure 2-5. Connection Verified Output Window
Once the connection is established, USB Clinic is ready for use. Please refer to Section
4 for more details.

AT43DK380 USB Host/Function Dev. Kit User Guide 3-1
3485A–USB–7/04
Section 3
Hardware Description
The AT43DK380 Development Platform comes pre-configured as a USB Host in Flash
(Standalone) mode. Alternative settings are available through jumper configurations.
This section gives the basic description about the hardware components and the jumper
settings of the AT43DK380 Development Platforms.
Section 9 contains the complete AT43DK380 schematics and bill of materials.
3.1 Description of
the Main
Development
Platform
The AT43DK380 Main Development Platform consists of the AT43USB380 Host/Func-
tion/OTG processor, 1 Mbytes of Flash ROM, 2 Mbytes of SRAM, 4 port USB Hub, USB
type MINI-A/B port, RS-232 serial port, and pre-programmed CPLD and glue logic for
configurable bus width interface. The AT43USB380 connects to the system processor
through the configurable bus width interface connectors. The RS-232 port provides
access to the system processor and the AT43USB380, and the In-System Programming
to SRAM.

Hardware Description
3-2 AT43DK380 USB Host/Function Dev. Kit User Guide
3485A–USB–7/04
Figure 3-1. AT43USB380 Main Development Platform Components Layout
3.1.1 AT43DK380
Processor Interface
Connector
The AT43DK380 Main Development Platform provides a generic processor interface to
allow a wide variety of processors to communicate with the on-board RAM, ROM and
the AT43USB380 USB Host. The pin assignments and descriptions for the connectors
are as follows:
Power
Connector
(5VDC)
Reset
Switch
USB-A
Connectors
USB Mini-A/B
Connector
=Pin 1
ROM 3
ROM 2
ROM 1
ROM 0
RS-232 (J5)
Processor Interface Connector (JP10)
CPLD
AT43USB380
R
A
M
3
R
A
M
2
R
A
M
1
R
A
M
0
EEPROM
Processor Interface Connector (JP9)
SW1
JP4
JP5
301
Hub
Ports
301
Hub
J1 SW2
JP1
JP3 JP2
J2
Table 3-1. J9: Processor Interface Connector 1
Pin # Pin Name Signal Source Pin Description
1, 2, 49, 50 VCC_3.3 Power: 3.3 VDC
3 D0 Bi-Direction Data Bit 0
4 D1 Bi-Direction Data Bit 1
5 D2 Bi-Direction Data Bit 2
6 D3 Bi-Direction Data Bit 3
7 D4 Bi-Direction Data Bit 4
8 D5 Bi-Direction Data Bit 5
9 D6 Bi-Direction Data Bit 6
10 D7 Bi-Direction Data Bit 7
13 D8 Bi-Direction Data Bit 8
14 D9 Bi-Direction Data Bit 9
15 D10 Bi-Direction Data Bit10
16 D11 Bi-Direction Data Bit 11
17 D12 Bi-Direction Data Bit 12
18 D13 Bi-Direction Data Bit 13

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AT43DK380 USB Host/Function Dev. Kit User Guide 3-3
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19 D14 Bi-Direction Data Bit 14
20 D15 Bi-Direction Data Bit 15
23 D16 Bi-Direction Data Bit 16
24 D17 Bi-Direction Data Bit 17
25 D18 Bi-Direction Data Bit 18
26 D19 Bi-Direction Data Bit 19
27 D20 Bi-Direction Data Bit 20
28 D21 Bi-Direction Data Bit 21
29 D22 Bi-Direction Data Bit 22
30 D23 Bi-Direction Data Bit 23
33 D24 Bi-Direction Data Bit 24
34 D25 Bi-Direction Data Bit 25
35 D26 Bi-Direction Data Bit 26
36 D27 Bi-Direction Data Bit 27
37 D28 Bi-Direction Data Bit 28
38 D29 Bi-Direction Data Bit 29
39 D30 Bi-Direction Data Bit 30
40 D31 Bi-Direction Data Bit 31
43 NDACK System Processor DMA Acknowledge
44 NDREQ AT43USB380 DMA Request
45 NWAIT AT43USB380
46 INTREQ AT43USB380 Interrupt Request
47 NRESET AT43DK380
(Main Development Platform and PDCs) System Reset, Active Low
48 NWAKEUP System Processor AT43USB380 Wake-Up request from Suspend Mode
11, 12, 21, 22,
31, 32, 41, 42 GND Power: Ground
Table 3-1. J9: Processor Interface Connector 1
Pin # Pin Name Signal Source Pin Description

Hardware Description
3-4 AT43DK380 USB Host/Function Dev. Kit User Guide
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Table 3-2. J10: Processor Interface Connector 2
Pin # Pin Name Signal Source Pin Description
1, 2, 49, 50 VCC_3.3 Power: 3.3 VDC
3 A0 System Processor Address Bit 0
4 A1 System Processor Address Bit 1
5 A2 System Processor Address Bit 2
6 A3 System Processor Address Bit 3
7 A4 System Processor Address Bit 4
8 A5 System Processor Address Bit 5
9 A6 System Processor Address Bit 6
10 A7 System Processor Address Bit 7
11 A8 System Processor Address Bit 8
12 A9 System Processor Address Bit 9
15 A10 System Processor Address Bit 10
16 A11 System Processor Address Bit 11
17 A12 System Processor Address Bit 12
18 A13 System Processor Address Bit 13
19 A14 System Processor Address Bit 14
20 A15 System Processor Address Bit 15
21 A16 System Processor Address Bit 16
22 A17 System Processor Address Bit 17
23 A18 System Processor Address Bit 18
24 A19 System Processor Address Bit 19
25 A20 System Processor Address Bit 20
26 EXTRA1 CPLD Additional signal to/from CPLD
29 NRD System Processor Read Enable. Active Low
30 EXTRA2 CPLD Unused signal to/from CPLD
31 nWBE0 System Processor Write Byte 0. Active Low
32 nWBE1 System Processor Write Byte 1. Active Low
33 nWBE2 System Processor Write Byte 2. Active Low
34 nWBE3 System Processor Write Byte 3. Active Low
35 nCS0 System Processor Chip Select 0. Active Low
36 nCS1 System Processor Chip Select 1. Active Low
37 nCS2 System Processor Chip Select 2. Active Low
38 nCS3 System Processor Chip Select 3. Active Low
41 PCLK System Processor Processor Clock
42 EXTRA3 CPLD Unused signal to/from CPLD
43 NC No Connect

Hardware Description
AT43DK380 USB Host/Function Dev. Kit User Guide 3-5
3485A–USB–7/04
Section 9 of the User's guide contains the bus interface CPLD VHDL code.
3.1.2 Jumper Settings The AT43DK380 Main Development Platform supports two modes of operation, Host
Mode or On-The-Go (OTG) Mode. Host Mode is the default setting. In Host Mode, the
AT43USB380 USB root port is directly connected to a 4-Port USB Hub (AT43301).
Thus, allowing the AT43USB380 to communicate to multiple USB devices. Downstream
USB devices are connected through J3 and J4. In OTG Mode, the AT43USB380 sup-
ports all requirements specified in the USB On-The-Go Supplement. Depending on the
state of the ID signal through cable connection, the AT43USB380 is either configured as
an USB Host or Device. Table 3-3 shows the configuration settings for mode selection.
Configuration options to the AT43USB380 are selected through SW1. SW1 determines
the bus sizing of the system processor, and the source of the AT43USB380 binary code.
Other switch settings are for debugging purposes only and it is NOT intended for the
end user. Switch settings for SW1 is illustrated in Table 3-4.
44 NC No Connect
45 UTXD0
46 URXD0
47 UDTR0
48 UDSR0
13, 14, 28,
28, 39, 40 GND Power: Ground
Table 3-2. J10: Processor Interface Connector 2
Pin # Pin Name Signal Source Pin Description
Table 3-3. AT43DK380 Mode Configuration
Host Mode with 4-Port USB Hub OTG Mode (Single Port)
JP4 Close: 1-3, 2-4 Close: 3-5, 4-6
Table 3-4. AT43USB380 SW1 Configuration
Default Setting Description
SW1.1 ON Test Point 0 (Test Mode Only)
SW1.2 ON Test Point 2 (Test Mode Only)
SW1.3 ON AT43USB380 binary code source
OFF: Upload from EEPROM
ON : Download through System Processor
SW1.4 ON Test Point 4 (Test Mode Only)
SW1.5
SW1.6
Depending on the
bundled Processor
Daughter Card bus width
interface
AT43USB380 Bus Width Selection
SW1.5 SW1.6
OFF don't care : 32 Bit interface
ON OFF : 16 Bit interface
ON ON : 8 Bit interface
SW1.7 ON Clock Select (Test Mode Only)
SW1.8 OFF TRESET (Test Mode Only)

Hardware Description
3-6 AT43DK380 USB Host/Function Dev. Kit User Guide
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The AT43DK380 Main Development Platform supports various addressing schemes to
the AT43USB380. Depending on the system processor used, JP5 can be configured to
match the address requirements of the system processor and that of the AT43USB380.
AT43USB380's addressing scheme is on the byte boundary. For most processors with
byte boundary addressing, the default setting is used. For some processors with internal
hardware address shifting to word or long word boundary, either use software to shift
the address back to byte boundary, or use JP5 for hardware shifting scheme. Do not
use both software and hardware shifting. Table 3-5 shows the jumper settings for byte,
word, and long word addressing schemes.
For an 8/16-bit mode interface, the AT43USB380's upper 16 data bits can be configured
through software to be high, low, or floating. For 32-bit mode, the upper 16 data bits are
connected to the system. The AT43DK380 Main Development Platform's JP2 and JP3
can be used to connect the upper 16 bits to the system or left floating to match the bus
width requirements of the system processor. Table x-x shows the jumper settings for dif-
ferent bus width interfaces.
The AT43DK380 Main Development Platform supports two modes of operation, the
default Flash (or Standalone) Mode and the ICE (In-circuit Emulator) mode. In Flash
Mode, the AT43DK380 Main Development Platform executes code from its on-board
flash ROM. While in ICE Mode, a In-Circuit Emulator for the system processor can be
connected through the JTAG connector of the Processor Daughter Card (PDC) to fur-
ther facilitate code development. For the jumper settings for the different modes, please
refer to the corresponding PDC section.
Table 3-5. AT43USB380 Address Configuration
Default: Byte
Addressing Word Addressing Long Word Addressing
JP5
Close: 2-4, 3-5, 6-8, 7-
9,10-12, 11-13, 14-16,
15-17
Close: 3-4, 5-6, 7-8, 9-
10,11-12, 13-14, 15-16,
17-18
Close: 4-6, 5-7, 8-10, 9-
11, 12-14, 13-15, 16-18,
17-19
Table 3-6. AT43USB380 D[31:16] Configuration
Default: 8/16
Bit Interface 32 Bit Interface
JP2 Open: all Close: 1-2, 3-4, 5-6, 7-8, 9-10, 11-12, 13-14, 15-16, 17-18, 19-20
JP3 Open: all Close: 1-2, 3-4, 5-6, 7-8, 9-10, 11-12, 13-14, 15-16, 17-18, 19-20

Hardware Description
AT43DK380 USB Host/Function Dev. Kit User Guide 3-7
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3.2 AT43DC380-
PDC1 Processor
Daughter Card
The AT43DC380-PDC1 Processor Daughter Card has a 32-bit bus interface connec-
tion. It comes pre-configured in Flash (Standalone) Mode. Alternative settings are
available through jumper configurations. Complete descriptions of the jumper settings
are explained in Section 3.2.1 on page 7.
Figure 3-2. AT43DC380-PDC1 Processor Daughter Card Layout
The AT43DK380-PDC1 Processor Daughter Card consists of a 32-bit ARM®processor
with JTAG accessibility (J2). Eight GPIO pins from the ARM processor are tied to a con-
nection header for interfacing with AT43DK380 Main Development Platform, and eight
other GPIOs are tied to JP6 for monitoring the ARM processor. In addition, the
AT43DC380-PDC1 Processor Daughter Card provides the footprint for a MII connector
(J2) if a network connection is required. Communication to the AT43DK380 Main Devel-
opment Platform is established through a proprietary interface. Section 9 of this User
Guide contains the complete AT43DK380-PDC1 schematics and bill of material.
3.2.1 PDC1 Jumper
Settings
The AT43DK380-PDC1 Processor Daughter Card supports two modes of operations,
the default Flash (or Standalone) Mode and the ICE (In-Circuit Emulator) Mode. In Flash
Mode, the AT43DK380-PDC1 Processor Daughter Card executes code from the Flash
ROM of the AT43DK380 Main Development Platform. While in ICE Mode, an In-Circuit
Emulator for the ARM processor can be connected through J2 to facilitate code develop-
ment. The corresponding jumper settings for the different modes are shown in Table 3-
7.
The ARM processor can operate at either 10 MHz or 50 MHz. Table x-x contains the
jumper settings for the clock selection for the ARM processor.
Processor Interface Connector (JP2)
Processor Interface Connector (JP1)
JTAG
Connector
ARM
Processor
JP3 JP5
J2
= pin 1
Table 3-7. AT43DK380-PDC1 Development Mode Selection
Flash Mode (Default) ICE Mode
JP3 Close: 1-2 Close: 2-3
JP5 Close: 3-5, 7-9 Close: 1-3, 5-7
Table 3-8. ARM Processor Clock Select
10 MHz 50 MHz
JP6 Open: 2-4 Close: 2-4

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3.3 AT43DC380-
PDC2 Processor
Daughter Card
The AT43DC380-PDC2 Processor Daughter Card has a 16-bit bus interface connec-
tion. It comes pre-configured in Flash (Standalone) Mode. Alternative settings are
available through jumper configurations. Complete descriptions of the jumper settings
are explained in Section 3.3.1 on page 8.
Figure 3-3. AT43DC380-PDC2 Processor Daughter Card Layout
The AT43DK380-PDC2 Processor Daughter Card consists of the AT91R40008, a 16-bit
ARM®processor, with JTAG accessibility (J1). Six GPIO pins from the AT91R40008
processor are tied to a connection header for interfacing with the AT43DK380 Main
Development Platform, and sixteen GPIO pins (with some overlap to the six GPIO pins
mentioned) are tied to JP4 for monitoring the AT91R40008 processor. Communication
to the AT43DK380 Main Development Platform is established through a proprietary
interface. Section 9 of this User Guide contains the complete AT43DK380-PDC2 sche-
matics and bill of materials.
3.3.1 PDC2 Jumper
Settings
The AT43DK380-PDC2 Processor Daughter Card supports two modes of operations,
the default Flash (or Standalone) Mode and the ICE (In-Circuit Emulator) Mode. In Flash
Mode, the AT43DK380-PDC2 Processor Daughter Card executes code from the Flash
ROM of the AT43DK380 Main Development Platform. While in ICE Mode, an In-Circuit
Emulator for the ARM processor can be connected through J1 to facilitate code develop-
ment. The corresponding jumper settings for the different modes are shown in Table 3-
9.
The External Interrupt signal can come from P9/IRQ0 or P12/FIRQ:
Processor Interface Connector (JP2)
Processor Interface Connector (JP1)
JTAG
Connector
AT91R40008
JP3
JP4
J1
= pin 1
Table 3-9. AT43DK380-PDC2 Development Mode Selection
Flash Mode (Default) ICE Mode
JP3 Close: 1-3, 5-7 Close: 3-5, 7-9
Table 3-10. AT43DK380-PDC2 External Interrupt Selection
P9/IRQ0 (Default) P12/FIRQ
JP3 Close: 4-6 Close: 2-4