PLX Technology PEX 8509RDK Quick user guide

PEX 8509RDK
Hardware Reference Manual

PEX 8509RDK
Hardware Reference Manual
Version 1.1
June 2007
Website: http://www.plxtech.com
Support: http://www.plxtech.com/support
Phone: [phone]
800 759-3735
Fax: [phone]

© 2007 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may
have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PEX 8509-RDK-HRM-P1-1.1
Printed in the USA, June 2007

PEX 8509RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. i
PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any
damage or loss caused by deletion of data as a result of malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PEX 8509RDK, a Rapid Development Kit, from a hardware perspective.
It contains a description of all major functional circuit blocks on the board and also is a reference for the
creation of software for this product. This manual also includes complete schematics and bill of materials.
REVISION HISTORY
Date Version Comments
April 2007 0.9 Hardware Reference Manual initial release.
May 2007 1.0 Incorporates feedback and minor updates.
June 2007 1.1 Changed C58 value in BOM and schematic.

PEX 8509RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. iii
CONTENTS
NOTICE...............................................................................................................................i
ABOUT THIS MANUAL...........................................................................................................i
REVISION HISTORY ..........................................................................................................i
1. General Information ................................................................................................. 1
1.1 PEX 8509 Features .......................................................................................... 2
1.2 PEX 8509RDK Features................................................................................... 2
1.3 RDK Port Expansion......................................................................................... 2
2. PEX 8509RDK Hardware Architecture .................................................................... 3
2.1 PEX 8509 PCI Express Switch ......................................................................... 3
2.2 PCI Express Card Edge P1 .............................................................................. 4
2.3 PCI Express Slot Connectors ........................................................................... 4
2.3.1 PCI Express Connector J1 ........................................................................ 4
2.3.2 PCI Express Connector J2 ........................................................................ 4
2.3.3 PCI Express Connector J3 ........................................................................ 4
2.3.4 PCI Express Connector J4 ........................................................................ 4
2.4 Reference Clock Circuitry ................................................................................. 4
2.5 Reset Circuitry .................................................................................................. 5
2.6 Hot Plug Circuitry.............................................................................................. 5
2.7 Serial EEPROM................................................................................................ 6
2.8 I2C Interface ..................................................................................................... 6
2.9 Power Distribution ............................................................................................ 6
2.9.1 Power Generation/Conversion .................................................................. 6
2.9.2 Power Sequencing .................................................................................... 7
2.10 LED Indicators .................................................................................................. 7
3. On-Board Connectors, Switches, and Jumpers....................................................... 9
3.1 DIP Switches .................................................................................................... 9
3.1.1 Upstream Port Selection (SW1) ................................................................ 9
3.1.2 PEX 8509 I2C Address Selection (SW2)................................................... 9
3.1.3 Port Configuration (SW3) ........................................................................ 10
3.1.4 J4 Slot control/Hot Plug Control (SW4) ................................................... 11
3.2 Push-Button Switches..................................................................................... 11
3.2.1 Hot Plug Attention Button# (SW5) ........................................................... 11
3.2.2 Manual Reset# (SW6) ............................................................................. 11
3.3 EEPROM Enable Jumper (JP5) ..................................................................... 11
3.4 JTAG Header (JP1) ........................................................................................ 12
3.5 PCI Express Fatal Error Indication (D9).......................................................... 12
3.6 PEX INTA# (D19) ........................................................................................... 12
3.7 Slots J1/J2/J3 Power Fault Indication (D20) ................................................... 12
4. Serial EEPROM Registers..................................................................................... 12
4.1 Serial EEPROM Contents............................................................................... 12
5. FAQ/Troubleshooting............................................................................................. 12
5.1 Frequently Asked Questions........................................................................... 12
6. Bill of Materials/ Schematics.................................................................................. 13

PEX 8509RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. iv
FIGURES
Figure 1-1. PEX 8509RDK Component Side View ..........................................................1
Figure 2-1. PEX 8509RDK Hardware Architecture ..........................................................3
Figure 2-2. PEX 8509RDK Reference Clock Circuit ........................................................5
Figure 2-3. I2C Connector Orientation for Aardvard I2C Controller .................................6
Figure 2-4. PEX 8509RDK Power Subsystem.................................................................7
Figure 3-1. Switch SW1 Default Settings.........................................................................9
Figure 3-2. Switch SW2 Default Settings.........................................................................9
Figure 3-3. Switch SW3 Default Settings.......................................................................10
Figure 3-4. Switch SW4 Default Settings.......................................................................11
TABLES
Table 2-1. PEX 8509RDK LED Indicator descriptions .....................................................7
Table 3-1. Switch SW1 Description .................................................................................9
Table 3-2. Switch SW2 Description ...............................................................................10
Table 3-3. Switch SW3 Description ...............................................................................10
Table 3-4. Switch SW4 Description ...............................................................................11
Table 3-5. Jumper JP2 settings .....................................................................................11

PEX 8509RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 1
1. General Information
The PLX PEX 8509RDK is a Rapid Development Kit based on the PEX 8509, a 8-lane, 8-port PCI
Express switch. The PEX 8509RDK provides a complete hardware and software development platform to
facilitate getting designs up and running quickly, lowering risk and reducing time-to-market. This RDK
allows the upstream port of the PEX 8509 to be directly plugged into a system board’s x16/x8/x4 PCI
Express connector, or plugged into an x1 PCI Express connector by using card edge adapters.
Figure 1-1. PEX 8509RDK Component Side View
PEX
8509
JTAG Header
Reference Clock Buffers
Reset Circuitry
3.3V-1V
Regulator
5V-3.3V DC/DC
converter
VTT Regulator
Manual PERST#
EEPROM
Socket
I2C
A1
U1
J1
J2
J4
J3
J5
Main Board Power
Indicators
HP BUTTON#
P1
Slots J1/J2/J3
Power Indicator
Lanes
0 1 2 3
4 5 6 7
Powered by J5
User Control DIP switches
U10
U11
U12
U13
SW6
U14
U2
JP3
JP4
JP1
SW5
U9
U8
SW1
SW3
SW4 SW2
JP2
JP5
Hot Plug Indicators
Lanes

PEX 8509RDK Hardware Reference Manual v1.1
2 © 2007, PLX Technology, Inc. All rights reserved.
1.1 PEX 8509 Features
•8-lane, 8-port (maximum) PCI Express switch
•PCI Express Base Specification revision 1.1 and PCI Standard Hot-Plug Controller and
Subsystem Specification, revision 1.0 compliance
•Eight PCI Express lanes provide 40 Gbps aggregate bandwidth
•Cut-thru Packet latency of 118ns (x4 to x1)
•Non-blocking internal crossbar architecture supports full wire speed
•Out of band communication/initialization interfaces (Serial EEPROM and I2C)
•Maximum Payload Size up to 1024 bytes
•Performance tuning
•Up to 8-ports (Up to 4 possible port configurations)
•PCI Express Standard Hot Plug Controller for three ports
•Assign x1, x2, or x4 lanes per port
•Allows any port to be designated as upstream port
•Configuration with strapping pins and/or EEPROM
•Sideband INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) signaling
•Lane reversal
1.2 PEX 8509RDK Features
•PLX PEX 8509 PCI Express switch in a 196-ball PBGA package
•Form factor based on PCI Express Card Electromechanical (CEM) Specification 1.1
•Four downstream PCI Express Slot connectors
•DIP switches for hardware configuration of PEX 8509 and on-board clock circuitry
•Support for Spread Spectrum Clocking (SSC).
•One Hot Plug controllable slot
•Socketable Serial EEPROM (3.3V)
•Standard 0.1” headers to connect up to I2C
•Manual push-button PERST# capability
•Lane Status indicator LEDs for visual inspection of link status
•Auxiliary ATX Hard disk connector for supporting additional power requirements for add-in cards
1.3 RDK Port Expansion
An RDK Port Expansion Kit may be purchased separately, which will transform the PEX 8509RDK into a
bench top platform that supports the full 8-port/8-lane configuration. When mated to the RDK Port
Expander, the upstream port is connected to a PCI Express x1 Cable connector. The Expansion Kit
includes a 1-meter cable and adapter card, which allows the PEX 8509’s upstream port to connect to any
standard PC. See the RDK Port Expansion Kit Hardware Reference Manual for more details.

PEX 8509RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 3
2. PEX 8509RDK Hardware Architecture
Figure 2-1. PEX 8509RDK Hardware Architecture
2.1 PEX 8509 PCI Express Switch
The PEX 8509 is a 8-lane, 8-port (maximum) PCI Express switch, which can be configured using strap
pins or EEPROM. The RDK’s onboard PEX 8509 is set up as a 5-port switch, with one x4 upstream port
(Port 0) and four x1 downstream ports (Ports 1 - 4). Port 0 connects to the card edge (P1), while Ports 1,
2, 3, and 4 connect to x16-sized slot connectors (J1, J2, J3, and J4 respectively).
Port 0
PEX 8509
Port 4 Port 2 Port 1
x16 Connector
x4 Card Edge
Hot Plug
Power Ctl.
EEPROM
I2C
DIP
switch
x4
82
4
Reset
Timer
PERST#
REFCLK
JTAG
connector
5
x16 Connector
x16 Connector
P1
J3
J2
J1
Port 3
x16 Connector
J4
RefClk
Buffer
RefClk
Buffer
x1 x1 x1 x1

PEX 8509RDK Hardware Reference Manual v1.1
4 © 2007, PLX Technology, Inc. All rights reserved.
2.2 PCI Express Card Edge P1
The RDK form factor is based on the PCI Express CEM 1.1 specification. The board can directly plug into
any PCI Express x4, x8, or x16 connector. All four lanes from the card edge connect to the PEX 8509’s
Port 0. The default configuration of the PEX 8509RDK sets Port 0 to be the upstream port. The card edge
provides the main source of +12V and +3.3V power, along with PERST# and REFCLK_P/N.
2.3 PCI Express Slot Connectors
The PEX 8509RDK contains four PCI Express slot connectors, which connect to the downstream ports of
the PEX 8509. All four connectors are x16 sized connectors, although the PEX 8509 connects less than
16-lanes to each of these four connectors. The PCI Express Card Electromechanical Specification 1.1
refers to this as down-shifting, and in general is not allowed to be implemented. The RDK does this for
testing purposes only; therefore, customers designing the PEX 8509 onto a platform board should size
the slot connector to match the link width of the port routing to that connector (For example, an x4 should
route to an x4 slot connector). Sizing all connectors to x16 allows any PCI Express CEM form factor card
(x16, x8, x4 or x1) to directly plug into the RDK without the use of adapters. The link between the PEX
8509 port and the plug-in card’s port will auto-negotiate to the highest common link width.
2.3.1 PCI Express Connector J1
Connector J1 is a straddle-mount (SMT), x16 PCI Express connector. Cards plugging into this slot will be
in-line with the RDK. Port 1 connects one lane (x1) to the lower four lanes of connector J1. The upper
fifteen lanes are unconnected. Power is provided to connector J1 from the ATX hard disk connector J5.
2.3.2 PCI Express Connector J2
Connector J2 is a vertical-mount (through-hole) x16 PCI Express connector. Cards plugging into this slot
will be perpendicular to the RDK. Port 2 connects one lane (x1) to connector J2. The upper fifteen lanes
are unconnected. Power is provided to connector J2 from the ATX hard disk connector J5.
2.3.3 PCI Express Connector J3
Connector J1 is a vertical-mount (through-hole) x16 PCI Express connector. Cards plugging into this slot
will be perpendicular to the RDK. Port 3 connects one lane (x1) to connector J3. The upper fifteen lanes
are unconnected. Power is provided to connector J3 from the ATX hard disk connector J5.
2.3.4 PCI Express Connector J4
Connector J4 is a vertical-mount (through-hole) x16 PCI Express connector. Cards plugging into this slot
will be perpendicular to the RDK. Port 4 connects one lane (x1) to connector J4. The upper fifteen lanes
are unconnected. Connector J4 is implemented as a Hot Plug controlled slot, via the PEX 8509 Hot Plug
controller and Texas Intruments power controller (see section 2.6 for more details). Power for this slot is
gated by two power FETs, which will only turn-on if a card is present in the slot (HP_PRSNT[3]# and
HP_MRL[3]# asserted).
2.4 Reference Clock Circuitry
Two Cypress CY28400-2 1-to-4 PCI Express clock buffers (U10 and U11) provide on-board REFCLK
distribution to the PEX 8509 and downstream slots (J1 – J4). The first CY28400-2 (U11) input is sourced
by the card edge P1. U11 provides two differential CML (current mode logic) clock outputs. One pair
drives the PEX 8509’s PEX_REFCLKP/N input. This pair is AC-coupled (C74 and C75). This is required
to block the DC information of the transmitter from the PEX 8509 clock receiver, which has on-chip
biasing and termination circuitry. The other pair drives the input of a second CY28400-2 (U10), which is
used for fan-out to the four downstream slots. The PEX 8509’s port 3 Hot Plug controller can be used to
control on the RefClk to slot J4.

PEX 8509RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 5
Figure 2-2. PEX 8509RDK Reference Clock Circuit
2.5 Reset Circuitry
The PEX 8509RDK reset circuitry includes a MAX6420 adjustable reset timer (U9) and manual reset
push-button switch (SW6). The reset timer accepts PERST# from the card edge (P1) and from SW6
(logical-OR via U8). The MAX6420 has the capability of adjusting the reset timeout period by changing
the value of C63 (0.001 µF ~= 3 ms).
2.6 Hot Plug Circuitry
Three PEX 8509 ports provide a 9-pin Hot Plug controller (HPC) interface. The RDK can be enabled (via
switch SW3 position 1) to allow Port 3’s HPC to provide full Hot Plug hardware functionality to slot J4.
Port 3’s HPC interfaces to an Texas Instruments TP2310 Hot Plug power controller (U3), which is used to
control and monitor +12V and +3.3V power to J4. The HPC provides an active-low power enable output
(HP_PWREN[3]#), which directly enables the TP2310 to begin ramping up the gates of Q1 and Q2 (+12V
and +3.3V respectively). After both power rails are stable, the TP2310 monitors the current being supplied
on both rails via R43 and R48. If either rail exceeds its programmable current threshold (5A for both +12V
and +3.3V) , the TP2310 will assert HP_PWRFLT[3]# to the PEX 8509’s HPC, enter current regulation
mode, and eventually drive the gates of Q1 and Q2 to 0V. HP_PWRFLT[3]# will remain asserted until
HP_PWREN[3]# is de-asserted via software. The de-assertion of HP_PWREN[3]# will reset the TP2310.
Attention and power indicators (D13 and D12 respectively) provide visual status regarding the state of slot
J4. The attention button (HP_BUTTON[3]#) is implemented as a push-button switch SW4. The manually-
operated retention latch (HP_MRL[3]#) is implemented as a DIP switch controlled input to the HPC (SW4).
PEX 8509
PEX_REFCLK
CY28400-2
CY28400-2
RefClk
RefClk
RefClk
RefClk
Card-Edge
RefClk

PEX 8509RDK Hardware Reference Manual v1.1
6 © 2007, PLX Technology, Inc. All rights reserved.
The PERST# signal supplied to J4 is directly controlled by the HPC (HP_PERST[3]#). By default, the Hot
Plug control over slot J4 in not enabled. The user can enable Hot Plug control of power and reset to J4,
by placing switch SW4, pin 1 to the OFF position.
2.7 Serial EEPROM
The PEX 8509RDK contains an 8-pin DIP socket for a serial EEPROM (U2). The board is populated with
a blank Atmel AT25080A 8-Kbit device. To use the serial EEPROM, place a shunt between pins 1 and 2
of JP2 (see section 3.4 for more details). The AT25080A device can directly interface to the PEX8509.
2.8 I2C Interface
The PEX 8509 implements an I2C slave interface, which allows an external I2C master to read and write
device registers through an out-of-band mechanism. The PEX 8509 I2C interface is accessible via a 7-bit
address, at data rates up to 400kbits/sec. The RDK provides two cascaded 2x2, 0.1” pitch headers (JP3
and JP4), which interface to the PEX 8509’s I2C port. This allows for cascading multiple RDKs together
using standard ribbon cable, or connecting various 3rd party I2C test equipment such as the Total Phase
Aardvark I2C controller.
Figure 2-3. I2C Connector Orientation for Aardvard I2C Controller
2.9 Power Distribution
2.9.1 Power Generation/Conversion
The PEX 8509RDK has two sources for DC power. The first source is the card edge connector (P1). The
x4 connector provides up to 2.1A at +12V and 3.0A at +3.3V. Card edge power is intended to power only
RDK board components and slot J4. Slots J1, J2 and J3 receive power via a 4-pin ATX hard disk
connector (J5). Add-in cards that require more that 25W of power (such as graphics cards) should use
slots J1, J2 and/or J3. These slots are power limited only by the ATX power supply that is used.
PEX8509 core and SerDes +1.0V supply is derived from the +3.3V rail through a Micrel MIC49150 LDO
regulator (U13). The PEX 8509’s +3.3V I/O supply receives power directly from the +3.3V card edge
power rail. The VTT supply for the PEX8509 PCI Express transmitters, is regulated from the +3.3V card
edge power via a Maxim MAX1806 adjustable LDO regulator (U14). The regulator output voltage is
normally set to +1.50V, but can be adjusted by changing the values of R98 and R102.
The ATX 4-pin connector provides +12V and +5V DC power. The +5V is converted down to +3.3V for
slots J1, J2 and J3 through a Bel S7AH-08B330/-08E1A0 non-isolated DC/DC converter (U12). The +12V
power rail is used directly.
12
1
2
3
3
4
4
JP3
JP4

PEX 8509RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 7
Figure 2-4. PEX 8509RDK Power Subsystem
2.9.2 Power Sequencing
The PEX 8509 device requires that the 1.0V power rails are supplied before the 1.5V and 3.3V rails are
powered. This power sequencing is accomplished via three bipolar transistors (Q3, Q4, Q6), biasing
resistors and one power MOSFET (Q5).
2.10 LED Indicators
The PEX 8509RDK provides a number of LED indicators including power-on indication, PEX 8509 lane
status indication, and Hot Plug status indication. Table 2-1 provides a quick explanation of the various
board indicators.
Table 2-1. PEX 8509RDK LED Indicator descriptions
Indicator
Type Locations LED On LED Off
Board Power
indication D16, D15, D17, D18 1.0V, 1.5V, 12V, 3.3V power on 1.0V, 1.5V, 12V,
3.3V power off
Slot J1/J2/J3
Power Fault D14
+12V or +3.3V power to slots J1/J2/J3
had dropped below -15% on either
supply.
+12V and +3.3V
power to slots
J1/J2/J3 is good.
J5 Power
indication D20 ATX Hard disk connector is currently
supplying power
ATX hard disk
connector is not
supplying power
PCI Express Slot Connector PCI Express Slot Connector
+12V +3.3V +3.3Vaux
PCI Express Card Edge
3.3V-to-1V
LDO Regulator
3.3V-to-
1.5V LDO
Pwr
Seq.
PEX_VTT
VDD10/VDD10S/VDD10A
VDD33/VDD33A
PEX 8509
ATX HD Conn.
5V-to-3.3V
DC/DC
+12V +5V
Hot Plug
Pwr. Ctl.
PCI Express Straddle Mount Connector
PCI Express Slot Connector

PEX 8509RDK Hardware Reference Manual v1.1
8 © 2007, PLX Technology, Inc. All rights reserved.
Indicator
Type Locations LED On LED Off
Slot J4 Power
indication D10, D11 Slot J4 +12V and +3.3V power on Slot J4 +12V and
+3.3V power off
PEX 8509 Port
0 Lane Status D1, D4, D5, D8 Port 0 link is up and lane n is active If all LEDs off, Port
0 link is down
PEX 8509 Port
1 Lane Status D2 Port 1 link is up If LED is off, Port 1
link is down
PEX 8509 Port
2 Lane Status D6 Port 2 link is up If LED is off, Port 2
link is down
PEX 8509 Port
3 Lane Status D3 Port 3 link is up If LED is off, Port 3 link is down
PEX 8509 Port
4 Lane Status D7 Port 4 link is up If LED is off, Port 4
link is down
PEX 8509
Fatal Error
Indication
D9 PEX 8509 detected a fatal error. No fatal errors
reported
PEX 8509
INTA# D19 PEX 8509 has asserted sideband interrupt
Interrupt is not
asserted
Hot Plug
Attention
indication
D13
On: Operation problem
Blinking: Slot is being identified at
user’s request
Normal operation
Hot Plug
Power
indication
D12
On: Slot is powered on
Blinking: Slot is being powered up or
powered down
Slot power
indication is off

PEX 8509RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 9
3. On-Board Connectors, Switches, and Jumpers
3.1 DIP Switches
The PEX 8509RDK contains four user controllable DIP switches (SW1, SW2, SW3 and SW4) for
selecting various functionality. Each DIP switch position can be either ON (0b) or OFF (1b). The gray
squares in Figures 3-1 through 3-4 indicate which way the switch position is connected.
3.1.1 Upstream Port Selection (SW1)
Figure 3-1. Switch SW1 Default Settings
Table 3-1. Switch SW1 Description
SW1 Functional Description Switch Position Settings
STRAP_UPSTRM_PORTSEL [2:0]
Selects the PEX 8509 Upstream Port.
Default setting is 000b.
1: STRAP_UPSTRM_PORTSEL[0]
2: STRAP_UPSTRM_PORTSEL[1]
3: STRAP_UPSTRM_PORTSEL[2]
Bus Encodings [2:0] Upstream Port
000b 0
001b 1
010b 2
011b 3
100b 4
101b 5
110b 6
111b 7
3.1.2 PEX 8509 I2C Address Selection (SW2)
Switch SW2 is used to select the lower three address bits of the PEX 8509’s I2C slave address.
Figure 3-2. Switch SW2 Default Settings
SW1 ON
UP_PORT0
HIGH LOW
1
1
2
ON
2
3
3
UP_PORT1
UP_PORT2
SW2 ON
I2C_ADDR0
HIGH LOW
1
1
2
ON
2
3
3
I2C_ADDR1
I2C_ADDR2

PEX 8509RDK Hardware Reference Manual v1.1
10 © 2007, PLX Technology, Inc. All rights reserved.
Table 3-2. Switch SW2 Description
SW2 Functional Description Switch Position Settings
PEX 8509 I2C Address bits[2:0].
Default setting is 111b.
1: I2C_ADDR[0]
2: I2C_ADDR[1]
3: I2C_ADDR[2]
Bus Encodings [1:0] PEX 8509 I2C Slave Address
000b 38h
001b 39h
010b 3Ah
011b 3Bh
100b 3Ch
101b 3Dh
110b 3Eh
111b 3Fh
3.1.3 Port Configuration (SW3)
Figure 3-3. Switch SW3 Default Settings
Table 3-3. Switch SW3 Description
SW3 Functional Description Switch Position Settings
STRAP_PORTCFG[3:0]
Selects PEX 8509 Port Configuration
Default Setting is 11b.
NOTE: When the RDK Plugs into the RDK
Port Expansion Kit, SW3 setting should
be 00b.
1: STRAP_STN_PORTCFG[0]
2: STRAP_STN_PORTCFG[1]
Bus Encodings [1:0] Port Configuration
00b x1,x1,x1,x1,x1,x1,x1,x1
01b x2,x1,x1,x1,x1,x1,x1
10b x2,x2,x1,x1,x1,x1
11b x4,x1,x1,x1,x1
SW3 ON
PORTCFG0
PORTCFG1
LOW
1
1
2
ON
2
HIGH

PEX 8509RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved. 11
3.1.4 J4 Slot control/Hot Plug Control (SW4)
Figure 3-4. Switch SW4 Default Settings
Table 3-4. Switch SW4 Description
SW4 Functional Description Switch Position Settings
Slot J4 Hot Plug Control. Allows the user to
select whether slot J4 is controlled via the PEX
8509 Hot Plug controller or normal board
power-up sequencing.
Default Setting is 0b.
1: J4CTL
Value Function
0b J4 is not Hot Plug
controlled.
1b J4 is controlled via
Hot Plug
Hot Plug MRL[3]#. Used to simulate MRL
sensor behavior.
Default setting is 0b.
2: HP_MRL[3]#
Value Function
0b Latch closed
1b Latch open
3.2 Push-Button Switches
3.2.1 Hot Plug Attention Button# (SW5)
Switch SW5 provides a push-button switch control for the PEX 8509 Hot Plug Controller’s
HP_BUTTON[3]# input pin. The PEX 8509 contains internal debounce circuitry for this input.
3.2.2 Manual Reset# (SW6)
The PEX 8509 RDK provides a manual PERST# capability. Note that manual PERST# will only apply
warm reset to the PEX 8509, and slots J1, J2, J3, and J4 (not P1).
3.3 EEPROM Enable Jumper (JP5)
JP5 is used to enable an EEPROM presence detection to the PEX 8509. Install a shunt between pins 1 -
2 to indicate a Serial EEPROM is present. Un-install the shunt to indicate a Serial EEPROM is not present.
Table 3-5. Jumper JP2 settings
JP5 Setting EEPROM Status
Shunt installed (Default) Serial EEPROM present
Shunt not installed Serial EEPROM not present
SW4 ON
J4CTL
MRL#
HIGH LOW
1
1
2
ON
2

PEX 8509RDK Hardware Reference Manual v1.1
12 © 2007, PLX Technology, Inc. All rights reserved.
3.4 JTAG Header (JP1)
Header JP1 provides a direct connection to the PEX 8509 JTAG interface. The 10-pin connector is
designed to allow a direct interface to 3rd party JTAG controllers, such as the Corelis USB-1149.1/E
controller.
3.5 PCI Express Fatal Error Indication (D9)
The PEX 8509 provides an output status pin (FATAL_ERR#), which reports the event of a PCI Express
fatal error condition. The RDK connects this output to D9, which is lit when a fatal error is detected.
Examples of fatal error conditions are data link layer protocol errors, receiver overflow, malformed TLPs,
etc… The PCI Express Base specification provides a complete listing of fatal error conditions.
3.6 PEX INTA# (D19)
PEX 8509 provides a side-band interrupt pin for signaling various programmable events.
3.7 Slots J1/J2/J3 Power Fault Indication (D20)
Slots J1, J2, and J3 are power by the ATX 4-pin hard disk connector and a DC/DC converter (U12). No
circuitry is provided to current limit the power consumed by those three slots; however, a voltage
supervisor is provided to monitor under-voltage conditions on the +12V and +3.3V supply rails going to
those slots. If either rail drops below 15% of its nominal supply voltage, the power good signal from U3 is
used to clear a D-flip flop (U15), which will in turn light a red indicator LED (D14). Once the LED is lit, it
remains lit until board power is cycled.
4. Serial EEPROM Registers
4.1 Serial EEPROM Contents
The PEX 8509RDK is shipped with a programmed AT25080A EEPROM. PLX Technology provides the
necessary binary image files and software tools required to program the EEPROM. Install a jumper
between JP2 pins 1 and 2, before applying power to the RDK.
5. FAQ/Troubleshooting
5.1 Frequently Asked Questions
Q1) I have purchased an RDK Port Expansion Kit to enable my PEX 8509RDK to work as an 8-
port/8-lane switch. What steps must I take to get my RDK working behind the RDK Port Expander?
A1) The RDK Port Expansion Kit has a separate Hardware Reference Manual, which provides of a list of
steps that should be taken prior to plugging the RDK into the RDK Port Expander. In general, since the
RDK Port Expansion Kit is intended to operate as a bench-top platform, the PCI Express bracket should
be removed, nylon stand-offs must be mounted onto to RDK, the PEX 8509’s Port Configuration should
be changed from x4x1x1x1x1 to x1x1x1x1x1x1x1x1 by changing SW3 from 11b to 00b.
Q2) Since the RDK Port Expansion Kit may use a different power than my host PC, is there a
power-up ordering requirement?
A2) Yes. The RDK Port Expander/PEX 8509RDK must have power applied before the PC is powered on.
This will ensure than the PC BIOS enumeration will see the PEX 8509 and it’s downstream components.