Hyundai GMS800 User manual

NOV. 1996 Rev. 1.0
8-BIT SINGLE-CHIP MICROCOMPUTERS
GMS800 Series
Instruction Manual

Revision 1.0
Published by
MCU Application Team in HYUNDAI MicroElectronics Co., Ltd.
© HYUNDAI MicroElectronics Co., Ltd. 1996. All Right Reserved.
Additional information of this manual may be served by HYUNDAI MicroElectonics Offices in Korea or
Distributors and Representatives listed at address directory.
HYUNDAI MicroElectonics reserves the right to make changes to any Information here in at any time
without notice.
The information, diagrams, and other data in this manual are correct and reliable; however, HYUNDAI
MicroElectonics Co., Ltd. is in no way responsible for any violations of patents or other rights of the third
party generated by the use of this manual.

Table of Contents
1. ADDRESSING MODE..............................................................................................................1
1.1. Inherent Addressing Mode....................................................................................................................................2
1.2. Immediate Addressing Mode  #imm................................................................................................................3
1.3. Direct Page Addressing Mode  dp...................................................................................................................4
1.4. Absolute Addressing Mode  !abs...................................................................................................................5
1.5. Indexed Addressing Mode....................................................................................................................................6
1.6. Indirect Addressing Mode.....................................................................................................................................8
1.7. Relative Addressing Mode.................................................................................................................................. 11
1.8. Bit Manipulation Mode.......................................................................................................................................13
1.9. 16 Bit Operation Mode  dp.......................................................................................................................... 14
1.10. Etc.................................................................................................................................................................... 15
2. INSTRUCTION SET ..............................................................................................................17
3. APPENDIX..............................................................................................................................65
3.1. Instruction Map.................................................................................................................................................. 65
3.2. Alphabetic Order Table of Instruction.................................................................................................................66
3.3. Instruction Table by Function ............................................................................................................................. 71

Addressing Mode
1
1. ADDRESSING MODE
Addressing refers to the specification, within an instruction, of the location of the operand on which the
instruction will operate. Because G8MC core has no 16-bit register, other than the program counter, which
can be used to specify an address, it is necessary that G8MC core user understand the various addressing
modes. This gives the experienced programmer flexibility for writing programs that are more sufficient in the
number of instructions and the execution time.
This core has 10 addressing modes as shown bellows.

Inherent Addressing Mode

Immediate Addressing Mode

Direct Page Addressing Mode

Absolute Addressing Mode

Indexed Addressing Mode

Indirect Addressing Mode

Relative Addressing Mode

Bit Manipulation Mode

16-Bit Operation Mode

Etc.

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1.1. Inherent Addressing Mode
This is a mode that needs no address field at all. The operand is specified implicitly in the definition of the
operation code. This mode is used to instructions which operate on registers(A,X,Y,PSW,SP). This mode
has an important advantage that executes faster than any two- or three-byte instruction.
OP CODE
Register Instructions
A ASL DAA DAS DEC INC LSR PUSH POP ROL
ROR XCN
X INC PUSH POP
Y INC PUSH POP
A,X TAX TXA XAX
A,Y TAY TYA XAY MUL
X,Y XYX
X,SP TSPX TXSP
A,X,Y DIV
PSW CLRC CLRG CLRV DI EI PUSH POP SETC SETG
ETC. BRK NOP RET RETI STOP

Addressing Mode
3
1.2. Immediate Addressing Mode

#imm
The operand is specified in the instruction itself. In other word, an immediate mode instruction has an
operand field rather than an address field. Immediate mode instructions are useful for Initializing registers to
a constant value. Immediate data must be 8-bit data.
 Register ( A,X,Y )
OP CODE #imm
Operand Instructions
A ADC AND CMP OR SBC EOR LDA
X CMPX LDX
Y CMPY LDY
Example)
04 35 ADC #35H
 Memory(dp)
OP CODE #imm dp
Operand Instructions
Memory LDM
Example) (G=1)
E4 55 35 LDM 35H,#55H
Op code ( 04 )
Operand ( 35 )
MEMORY
A ←A+35h+C
Operand( 55 )
Opcode ( E4 )
data
Operand ( 35 )
MEMORY
data ←55h
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page
immediate data

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1.3. Direct Page Addressing Mode

dp
The address field of the instruction gives the address of the operand in memory. The 2nd byte of instruction
is the offset from the start address of direct page. Direct Page(dp) is determined by G-flag.
G=0 0-Page ( !0000H ~ !00FFH) G=1 1-Page ( !0100H ~ !01FFH)
OP CODE dp
Operand Instructions
A ADC AND CMP LDA EOR OR SBC
X LDX CMPX
Y LDY CMPY
Memory ASL COM DEC INC LSR ROL ROR TST
Example) ( G=1 )
05 35 ADC 35H
Example) ( G=1 )
89 35 INC 35H
Op code ( 05 )
data
Operand ( 35 )
MEMORY
A ←A+data+C
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page
Op code ( 89 )
data
Operand ( 35 )
MEMORY
data ←data + 1
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page

Addressing Mode
5
1.4. Absolute Addressing Mode

!abs
The address field of the instruction gives the address of the operand in memory. 2nd byte instruction is the
lower address and 3rd byte is the upper address. The disadvantage of absolute addressing mode is to
require 3-byte instruction.
OP CODE Low Address Upper Address
Operand Instructions
A ADC AND CMP LDA EOR OR SBC STA
X CMPX LDX STX
Y CMPY LDY STY
PSW JMP CALL
Memory ASL BIT DEC INC LSR ROL ROR TCLR1 TSET1
Example)
07 35 D0 ADC !0D035H
Example) ( G=1 )
98 35 01 INC !0135H
Op code ( 07 )
Operand( 35 )
data
Operand( D0 )
MEMORY
A ←A+data+C
D035h
Op code ( 98 )
data
Operand ( 35 )
Operand ( 01 )
MEMORY
data ←data + 1
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page

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X-Register
Y-Register
1.5. Indexed Addressing Mode
In the indexed addressing mode the contents of an index register(X,Y) is added to the address part of the
instruction to obtain the effective address. The index register contains an index value. The address field of
the instruction defines the beginning address of a data array in memory. Each operand in the array is stored
in memory relative to the beginning address. The distance between the beginning address and the address
of the operand is index value stored in the register.
 X-register Indexed Addressing Mode in direct page(dp)  dp+X
The effective address is determined by adding the address of operand and the contents of X-register. it is
specified to direct page of memory.
OP CODE dp
Operand Instructions
A,Memory ADC AND CMP LDA EOR OR SBC STA ASL
DEC INC LSR ROL ROR XMA
Y,Memory LDY STY
Example) ( G=0, X=F5h)
06 45 ADC 45H+X
 Y-register Indexed Addressing Mode in direct page  dp+Y
The effective address is determined by adding the address of operand and the contents of Y-register. it is
specified to direct page of memory.
OP CODE dp
Operand Instructions
X,Memory LDX STX
= 1 3A
+
Op code ( 06 )
Operand ( 45 )
data
X ( F5 )
MEMORY
A ←A+data+C
000h
0FFh
100h
03Ah
1FFh
0 Page
1 Page

Addressing Mode
7
 Y-register Indexed Addressing Mode in absolute address  !abs+Y
The effective address is determined by adding the address of operand and the contents of Y-register. it is
specified to all space of memory.
OP CODE Low Address Low Address
Operand Instructions
X,Memory ADC AND CMP EOR LDA OR SBC STA
Example) ( Y=55h)
15 35 D0 ADC !0D035H+Y
+ D035h
Op code ( 15 )
Operand

data
Operand

Y( 55 )
MEMORY
A ←A+data+C
=D08Ah
D08Ah

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1.6. Indirect Addressing Mode
The address field of the instruction gives the address where the effective address is stored in memory.
 X-register Indirect Addressing Mode in direct page ( no offset )  { X }
The contents of X-register is the effective address to access in direct page(dp) .
OP CODE
Operand Instructions
A,Memory ADC AND CMP LDA EOR OR SBC STA XMA
Example) ( G=1, X=35h)
14 ADC { X }
 X-register Indirect Addressing Mode in direct page, auto increment  { X }+
The addressing method of this mode is the same as X Register indirect addressing mode except auto-
increment of x register.
OP CODE
Operand Instructions
A,Memory LDA STA
Example) ( G=1, X=35h)
14 LDA { X }+
Op code ( 14 )
data
X ( 35 )
MEMORY
A ←data
X = 36H
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page
Op code ( 14 )
data
X ( 35 )
MEMORY
A ←A+data+C
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page

Addressing Mode
9
 dp Indirect Addressing Mode  [ dp ]
The effective address is the contents of memory pair((dp+1)(dp)) in direct page.
OP CODE [dp]
Operand Instructions
Memory JMP CALL
Example) ( G=0 )
3F 35 JMP [35H]
 X-register Indexed Indirect Addressing Mode  [ dp+X ]
The effective address is the contents of memory pair((dp+X+1)(dp+X)) in direct page, which is determined
by adding the address of operand and the contents of X-register.
OP CODE [dp+X]
Operand Instructions
A,Memory ADC AND CMP EOR LDA OR SBC STA
Example) ( G=0, X=10h)
16 25 ADC [25H+X]
0FFh
0FFh
PC  C005h
Op code ( 3F )
Operand ( 35 )
MEMORY 000h
100h
data1 ( 05 ) 035h
C005h
0 Page
1 Page
data2 ( C0 )
NEXT
036h
+
0FFh
0FFh
C005h
A  A + data + C Opcode ( 16 )
Operand ( 25 )
MEMORY 000h
100h
C005h
data1 ( 05 ) 035h
= 35h
0 Page
1 Page
data2 ( C0 )
Data
036h
X ( 10 )

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 dp Indirected Y-register Indexed Addressing Mode

[ dp ] + Y
The effective address is determined by adding contents of ((dp+1)(dp)) and contents of Y-register.
OP CODE [dp]
Operand Instructions
A,Memory ADC AND CMP EOR LDA OR SBC STA
Example)
17 25 ADC [25H]+Y
 Absolute Indirect Addressing Mode

[ !abs ]
The effective address is contents of ((!abs+1)(!abs)).
OP CODE Lower Address Upper Address
Operand Instructions
PSW JMP
Example) ( G=0, Y=10h)
1F 25 C0 JMP [!0C025H]
+0FFh
0FFh
C015h=
A  A + data + C
Op code ( 17 )
Operand ( 25 )
MEMORY 000h
100h
C015h
data1 ( 05 ) 025h
0 Page
1 Page
data2 ( C0 )
Data
026h
Y ( 10 )
C026h
D005h=
Op code ( 1F )
Operand( 25 )
Operand( C0 )
MEMORY
D005h
data1 ( 05 ) C025h
data2 ( D0 )
NEXT

Addressing Mode
11
1.7. Relative Addressing Mode
In this addressing mode, the effective address is calculated current address(the contents of PC) and the
contents of address part of instruction. The address part of the instruction is considered as a signed number
which can be either positive or negative. When this number is added to the contents of PC, the result
produces effective address whose position in memory is relative to the address of the next instruction in the
program.
Relative addressing mode is used in branch instructions when the branch address is in the area surrounding
the instruction word itself. It results in a shorter address field in the instruction format since the relatives
address can be specified with a smaller number of bits than the number of bits required to designate the
entire memory address. The relative address from the current address is in the range of -128 ~+127 byte.
 PSW Relative

rel
The branch operation is determined by the bit of PSW specified by instruction. The branch address is
obtained by adding the contents of operand to the contents of program counter.
OP CODE rel
Operand Instructions
PSW BCC BCS BEQ BMI BNE BPL BVC BVS
Unconditioned BRA
 Notes : BRA 0FEH  endless Loop ( Recursive Branch )
Example)
50 30 BCC [30H]
 A.bit Relative  A.bit,rel
The branch operation is determined by the bit of accumulator specified by bit7,6,5 of op code. The branch
address is obtained by adding the contents of operand to the contents of program counter.
OP CODE rel
Operand Instructions
A BBC BBS


+1

+2
PC+30h
Op code ( 50 )
Operand ( 30 )
MEMORY
( IF C=0,) ( IF C=1,)

+2+30
NEXT

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Example) ( A=55h)
F2 30 BBC A.7,30H
 dp.bit Relative  dp.bit,rel
The branch operation is determined by the bit in memory specified by bit7,6,5 of op code. The branch
address is obtained by adding the contents of operand to the contents of program counter.
OP CODE dp rel
Operand Instructions
Memory BBC BBS
Example) ( G=0, ( 0035h)=55h)
33 35 30 BBC 35H.1,30H
 Etc.
Mixing instruction ( BNE rel after CMP or DEC operation )
CBNE dp,rel  CMP dp , BNE rel
CBNE dp+X,rel  CMP dp+X, BNE rel
DBNE dp,rel  DEC dp , BNE rel
DBNE Y,rel  DEC Y , BNE rel
10 10 10 10
00 11 3h
0035h
Op code

+2

+3
PC+30h
Op code ( 33 )
Operand ( 35 )
Operand ( 30 )
MEMORY

( IF M1=1,)

+3+30
NEXT

+1
035h
Data (55)

+2

+1
PC+30h
Op code ( F2 )
Operand ( 30 )
MEMORY

( IF A7=1,)

+2+30
NEXT
10 10 10 10
11 11 2h
Accumulator
Op code

Addressing Mode
13
1.8. Bit Manipulation Mode
Operation is performed by 1bit instruction manipulation.
 Accumulator Bit Operation  A.bit
Bit position of accumulator is determined by the upper 3 bits of operand.
OP CODE operand
Operand Instructions
ACLRA1 SETA1
Example) ( A=00h)
0B C0 SETA1 A.6
 Direct Page Memory Bit Operation  dp.bit
Bit position of memory in direct page is determined by the upper 3 bits of op code.
OP CODE operand
Operand Instructions
Memory CLR1 SET1
Example) ( G=0, (035h)=00h)
C1 35 SET1 35H.6

+1
10 00 00 00
11 00 0h
Accumulator
A6=?
 A6=1
Operand

+2
Op code( 0B )
Operand ( C0 )
MEMORY

NEXT
1- -- -- --
0035h
M6=?  M
6=1
11 00 1h
Op code Op code ( C1 )
Operand ( 35 )
MEMORY
NEXT
035h
Data

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
12-bit Address Space Memory Bit Operation

M.bit
Operand composes the lower 8bit of 12bits address, the lower 4bits of operand indicate the upper 4bits of
12bits address, also bit position of memory is determined by upper 3 bits of operand 2, bit4 of operand
indicates reversal. The addressing memory space is 4k bytes in 000h~FFFh.
OP CODE Lower Address Upper Address
Operand Instructions
C,Memory AND1 AND1B EOR1 EOR1B LDC LDCB OR1 OR1B STC
Memory NOT1
Example) ( C=1, (135h)=00h)
8B 35 51 AND1B 135H.2
1.9. 16 Bit Operation Mode
 dp
2nd byte of instruction(operand) is offset address in direct page, the contents of memory pair in its page is
determined to data. Direct page is selected by G-flag (G-flag is changeable by SETG, CLRG).
OP CODE dp
Operand Instructions
YA,Memory ADDW CMPW LDYA STYA SUBW
Memory DECW INCW
Example) ( G=1 )
1D 35 ADDW 35H
C
←C 
“1”“0”
reverse
10 10 1h
Operand 2
Op code( 8B )
Operand( 35 )
MEMORY
Operand( 51 )
135h
Data ( 00 )
00 00 00 00
0135h
Data2 ( AA ) 136h
Op code ( 1D )
Operand ( 35 )
MEMORY
YA
←YA+ AA55h
0 Page
000h
0FFh
100h
Data1 ( 55 ) 135h
1FFh
0 Page
1 Page

Addressing Mode
15
1.10. Etc.

U-page Addressing Mode
 upage
The operand becomes offset address in U-page(FF00h~FFFFh). The program is jumped to the specified
address in U-page.
OP CODE upage
Example)
4F 35 PCALL 35H

Table CALL
 n
The vector table of TCALL is determined by the upper 4bits of op code. The domain of TCALL vector is in
address FFC0H~FFDFH.
OP CODE
Example)
4A TCALL 4
Op code ( 4F )
Operand ( 35 )
MEMORY
FF00h
NEXT FF35h
FFFFh
U Page
Op code( 4A )
MEMORY
FF00h
T/vector1 ( 25 )
FFFFh
U Page
T/vector2 ( D1 )
FFD6h
FFD7h
NEXT D125h
10 00 Ah
Op code
reverse
PC
Fh
Fh
11 11 11 11 11 10 10 01
6h
Dh

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