Hyundai PD421 User manual

Hyundai
Plasma Display
PD421 Svc Manual

--1--
Plasma Display PD421
. Circuit Service Methods
1. W hite Ba lance Adjustment
l Refer to adjustment specifications for information on makin g adjustments
m When white alance has to e adjusted during service
- If the module is replaced, it must e readjusted u sing VG -828 equipment,
according to the adjustment specifications
- When making progra m upgrades [ ROM (UM04) replacement] or replaci ng A/V
B/D, the values stored i n A/V B /D’ s EPROM (UM12) should e written down
and re-ente
The method of white Balane Adjustment efore ROM or B/D IS Replaced
red into the new new Rom or A/V Board.
efore Rom or B/D is
Replaced
select the Video Mode
Select "Device" from
the menu
Select AD9883
R.G.B-Gain value
R.G.B-Gain value
Factory Mode Exit
Select the pc mode
Enter into the Factory
mode
Select the Device
Select AD9883
R.G.B-Gain value
R.G.B-Gain valye
Enter the Menu+42+
Mute key
Select "White" from the
menu
R.G.B-Gain value
R.G.B-Blas value
Select "Device"
Select FLI2300
Brightness and
Contrast values
Factory Mode Exit
Select the DTV mode
Enter into the Factory
mode
Enter into the
Factory Mode
Separate Record(a)
Separate Record(c)
Separate Record(d)
Separate Record( )

--2--
After ROM or B/D
replaced
Select the Video mode
After selecting AD9883
enter(c) Data recorded
in R,G and B-Gain and
Bi as values separately
After exiting from the
Factory select the
PC mode
Enter the Facrory to
select the PC mode
Enter(a) Data recorded
in R.G and B-Gain and
Bias values separately
After selecting AD9883
enter(c) Data recorded in
R.G and B-Gain and Bias
values separately
Completed adjustments of
the White alance
Enter in to the Factory
mode
After selecting "Whte"
enter (a) Data recorded
in Bias values
Separately
After selecting
FLI2300, enter( ) Data
recorded in Brightness
and Contrast values
separately
After exiting from
Factory, select the
DTV mode
After entering into
Factory to select
White enter(a) Data
recorded tn R,G and
B-Gain and Bias
values separately
:When ROM and AV B/D are
replaced without additional
equipment, this is how to
adjust the white alance

--3--
Plasma Display PD421
2. A/V Circuit BLOCK Diagram
1) PC Mode
PC inputs, R, G, B , H, and V signals, are entered through D-S u 15pin
(DSUB1). They are entered into the DTV/PC sele ction switch, B A7657
(UA01). When PC is selected in M CU, the signals are entered into the AD
converter, AD 9883 (UA02).
In AD9883, the signals are c onverted into 24 its and entered into scaler
ASI500.
BA7657 selects PC when pin16 is high and selects DT V when pin 16 is low.
AD9883 is controlled using the SDA/SCL line of pin 57/56.
PC input resolution is fh: 30~70k a nd fv: 50~85Hz, and the maximum
resolution is 1080x768 at 85Hz.
If the resolution is a ove the specifications, an out of range m essage is
displayed on the upper left hand corner of the screen. However, even if the
resolution is within the specified range, if the input timing is different from
the timing indicated on the manual, a ‘not found vesa o r out of range’
message can e displayed. Please check the timing to identify the cause of
the ‘out of range’ message.
PC input sync can rece ive H/V composite or separate, ut if DPMS ON is
selected in the PDP menu, DPMS cannot o perate in composite and c an
operate only in separate sync.
The Auto Adjust function, which is used to adjust the picture position and
size, should e carried out in the Windows desktop screen or full cross hatch.
The D TV signals, 480p, 720p, and 1080i, from the set-top ox with a D-Su
out port, can e received through the D-Su port and displayed in the PC
mode.
DVI Mode
Signals entering through the DVI port (D V101) are converted to 24 its in
the TMDS Receiver, SIL161B (UT02 ), and entered in scalar ASI500.
SIL161B is an output port and is activated when pin num er 2 is high.
DTV signa ls 480p, 720p, and 1080i can e displayed through the DVI port .
However, PD421 cannot only display 60Hz DTV signals. It is una le to
display 50Hz DTV signals. PC can support oth 50Hz and 60Hz signals.
The resolution of DVI Mode is the same as the PC Mode.

--4--
2) DTV Mode
DTV signals are entered as Y, P (C ), and Pr(Cr) component signals,
separated into Y, C , Cr, H, and V sync on (xan51AcuxA01) and entered to BA7 657.
If pin 16 is low, DTV signals are entered into ADC9883.
In the AD9883, like the PC signals, the DTV signals are converted to 24 its
and entered into scalar ASI500.
DTV signa l is composed of 480p (50/60Hz) for SD, 720p (50/60Hz) for HD,
and 1080i (50/ 60Hz). If the video signal, 480i component (DVD component
output), is entered, the screen will not display properly. Also,
ecause synchronization signal
if the connections are incorrect, it will not operate properly
is in Y singal color Data is in Cr/C
3) DVD Mode
DVD signals entered as Y, P , and Pr components are applied when entered
as 480i (NT or PAL). 480p DVD signals should e entered through the DTV
component port.
Y, P , and P r signals entered through the DVD component port are entered
into the video decoders, Main VPC3230 (UDM01) and Su VPC3230 (U DS01),
where they are converted to Y (8 its) and UV (8 its) digital sig nals and sent
to the deinterlacer IC, F LI2310 (UF L1).
UV digital signal means P (C ), and Pr(Cr) signals that have een converted
to digital signals.
The v ideo decoder, VPC3230, automatically detects NTSC and PAL/S ECAM,
identifies them as roadcast signals, converts the interlacer signal into the
progressive signal (fh : 15.7Khz-> 31Khz) in t he deinterlacer IC, FL I2310
(UF L1), and sends to the scalar ASI500.
When the PD 421’s main screen is in PC, DVI or DTV mode, the su -screen
of the PIP or POP function is processed in the Main VI DEO DECODER
(UDM01) and the MODE can e DVD, S-VHS, Video, or Scart.
PIP or POP etween video modes is ena led y main video decoder (U DS01),
su video decoder (UDS01), and F IFO memory, MS81V04160 (UF M01). If the
main screen is DVD, then the su - screen will e S-VHS, Vid eo, or Scart.
Please refer to the ta le in the ack for more information on PIP or POP.
4) S-Video
S-Video signals are entered as Y/ C signals, which is composed of Luminance

--5--
Plasma Display PD421
color signals. The NT SC and PAL/SECAM are automatically detected y the
video decoders, main VPC3230 and su VPC3230, and converted to Y (8 its)
and UV (8 its) and sent to the deinterla cer IC, FLI2310, as 16 it digital
signal.
S-Video input and composite video input share a single audio jack.
Therefore, while the pictures for the two inputs can e viewed at the same
time, only one of the sounds can e heard. PIP/POP operati ons are the same
as descri ed for the DVD mode.
5) Video
Video signal is a composite signal that com ines the Luminance (Y) and color
(CHROMA) .
It is entered through the main VPC3230 and su VPC3230 when selected in
the input selection switch, TA8851 (UMX01).
If the signal is NTSC, it is first entered into the 3D Com Filter (fi lter that
separates the composite to Y/C signal), UPD 64083 (UCF 01) and separated into
Luminance signal Y and color signal, C. The separated signals then enter the
mux switch, TA8851, sent to TA8851 pin44 LU MA IN and pin43 CROMA IN,
and finally sent to Main VPC3230.
When the video input is displayed on the main screen, it passes through the
3D com filter, ut if it is displayed on the su - screen (when using PIP or
POP), the video input does not pass through the 3D com filter a nd i s
displayed using the composite signal.
PAL/SECAM signal cannot e processed y the 3D com filter. It i s sent as
composite signal to the main VPC3230 and su VPC3230.
If the signal is NTSC, the video input switch, BF 7654 (UDM02), which is
located in front of the main VPC3230, select the 3D Com -Y to send the
signal as a Y signal to the VPC 3230. If the signal is Pa l, it selects CVB S to
send the signal as a composite signal to the VPC3230.
Signals entered into VPC3230 are converted to 16 it digital signal (Y (8 its)
and UV (8 its)) and sent to the scalar through the deinterlacer IC, F L I2310.
6) Scart Mode
Scart only supports CV BS signals, which are processed in the same way as
video signals. The RF signal is not supported, and therefore, the Scart pin8
ID signal is ignored.

--6--
Plasma Display PD421
7) PIP/POP Support Mode Map
Su
Main PC DTV DVD S-VHS Video Scart DVI
PC X
X
X O X
DTV X X O X
DVD O O O OOO
O
O
O
O
OOO
OO
O
OOO
OOO
OO
S-VHS X O O O
Video X O O
Scart X O
DVI X X O O O O X
X: Not supported, O: Supported
Note: When displaying NTSC or P AL signals to PIP or POP , if the signals are displayed
as Main: NT SC, Su : P AL or in reverse, the picture can e seen, ut the size scaling for
the su -scr een will not display properly. This is ecause the signal is meant for the
main screen. Main screen use s 50Hz PAL or 60Hz NTSC and su scre en uses 60Hz
NTSC or 50Hz .
8) Scaler Output
Scaler output signals, R, G, and B (each 8 its), are outputted as 24 it TTL
signal, converted into LVDS signal in the LVDS converter, DS90C3 85
(ULV01), and sent to the logic B/D in the PDP module. Output timing:
fh : 29.1Khz
fv : PAL 50Hz
NTSC 60Hz
DCLK : a out 27Mhz
9) Audio part
Audio input port for each mode:
Input Port Remark
PC/DVI RCA L/R 1E A Shared
DTV RCA L/R 1E A
DVD RCA L /R 1E A
CVBS/S-Video RCA L/R 1E A Shared
Scart cart Jack L/R
S

--7--
Plasma Display PD421
Audio input signal for PC/DVI, DT V, and DV D modes is entered into the
audio processor IC, MSP3450G , and audio input signal for VID E O/S-VIDEO,
and SCART modes is first selected in MUX 8851 a nd entered into the audio
processor.
As in other chips, the audio processor (MSP34 50G) uses the SCL and SDA
line to control volume, and left/right alance and mono/stereo.
The L/R audio signal sent y MSP3450 is a mplified in the amplifier, TA2 024
(UAU1) and sent to the speaker.
TA2024B support 10W( ased on impedance 8Y ) of output for each L/R.
3. Trou le shooting
1) Diagnosing defective module
If the power does not come on or if the module operates a normally, check
module defect. To do this, remove the rear cover and A/V B/D to reveal the
module’s logic B /D. The following figure represents the s/w on the logic B/D.
SW 2001
Signal 1 2 Remark
External up up up Forwarding
Criteria
Internal up down
If the switch is set to internal signals, it will operate without external signals,
ut the screen will e displayed in full white.
Therefore the module operation can e checked without the A/V oard.
Here, e aware that the pin 8 and pin 9 of the power B /D’s CN802(11p),
which is located a ove the module’s logic B /D, must e shorted and the A/C
power supplied in order for the module to operate normally. Pin 8 is marked
as PS-ON elow the connector (CN802).
If module itself is tested and it does not power on or the picture is a normal,
the module is defective.
When reconnecting the A/V B /D, make sure to change the switch to external
signals.
- The most common module defect is the appearance of a lack or right
vertical line.
1 2 3 4
4
down
down
up
3

--8--
- Bar
This occ urs when the FPC wire, which connects the address line elow the
module, is damaged. Because the wi re is on the ottom, it can e e asily
damaged when the module is lifted and assem led or from external shock. Use
caution when handling the module and use the handle on the ottom of the
module to lift or move.
If the vertical ar appears at the same location for all modes, the F PC wire is
damaged.
FPC wire cannot e replaced. The entire module needs to e replaced.
- If the module does not power on, it is mostly likely due to an open fuse on the
power B/D. Check the lack and round fuse on the power B/D.
2) Diagnosis y Pro lem Ty pe
- Power comes on, ut the picture does display
Check the AV B/D ’s communication lines, SDL and SDA lines.
ICs c ontrolled y the SDA and SCL line are ADC9883, F LI2310, MSP 3450G,
VPC3230, 3D com filter, and TA8851. If after powering on, the SDA and SCL
line’s Vp- p is less than 4V and checks elow 2.5V, the communication line is
loaded at some point. Open and check each IC’s communication line.
- Can also occur when the connection etween the graphic B/D and video B/D is
ad.
- If the picture turns off or the volume is muted while viewing through the set-
top ox, please check the status of the set-top ox first.
- For a normal picture when using P IP/POP function, refer to the s ection on
Video Mode in the manual
- If the OSD screen cracks or displays a normally:
May e caused y ad connection etween the graphic B/D’s sc aler a nd
SDRAM, K4S643232C (UF B 01, UFB02). Use the clea ner to clean the around
the scaler and the UFB01/02.
OSD is processed y the scaler (ASI 500).
- If the power is on and the input signals and connections are normal, ut the
picture does not display:

--9--
Plasma Display PD421
B
AIN
B
OUTA
MIDSCV
SYNC
PROCESSING
AND CLOCK
GENERATION
HSYNC
COAST
CLAMP
FILT
DTACK
HSOUT
VSOUT
SOGOUT
REF REF
BYPASS
SERIAL REGISTER
AND
POWER MANAGEMENT
SCL
SDA
A
0
AD9883
CLAMP 8
A/D
GENERAL DESCRIPTION
The AD9883 is a complete 8- it, 110 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 110 MSPS encode
rate capa ility and full-power analog andwidth of 300 MHz
supports resolutions up to SXGA (1280X 1024 at 60Hz).
The AD9883 includes a 110 MHz triple ADC with internal
1.25 V reference, a PLL, and programma le gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and HSYNC and COAST signals. Three- state
CMOS outputs may e powered from 2.5 V to 3.3 V.
The AD9883’s on-chip PLL generates a pixel clock from HSYNC
and COAST inputs. Pixel clock output freque ncies range from
12 MHz to 110 MHz. PLL clock jitter is 500 ps p-p typical at
10 MSPS. When the COAST signal is presented, the PLL
maintains its output frequency in the a sence of HSYNC. A
sampling phase adjustment is provided. Data, HSYNC and
Clock output phase relationships are maintained. The AD9883
also offers full sync processing for composite sync and sync-on-
green applications.
A clamp signal is generated internally or may e provided y the
user through the CLAMP input pin. This interface is fully pro-
gramma le via a two-wire serial interface.
Fa ricated in an advanced CMOS process, the AD9883 is
provided in a space-saving 80-lead LQFP surface mount plastic
ackage and is specified over th e 0 C to 70 C temperature range.
Sync Detect fo Hot ugg ng
Midscale Clamping
Power-Down Mode
Low Power : 500mW tYPICAL
Composite Sync Applications Require an External Coast
MC68HC705BD7B
AD9883
Critical Parts Specification

--10--
AD9883–SPECIFICATIONS
(V
D
= 3.3 V, V
DD = 3.3 V, ADC Clock = Maximum Conversion Rate)
Analog Interface
Test AD9883KST-110
Parameter Temp Level Min Typ Max Unit
RESOLUTION 8 Bits
DC ACCURACY
Differential Nonlinearity 25 C I 0.5 +1.25/–1.0 LSB
Full VI +1.35/–1.0 LSB
Integral Nonlinearity 25 C I 0.5 1.85 LSB
Full VI 2.0 LSB
No Missing Codes Full VI Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum Full VI 0.5 V p–p
Maximum Full VI 1.0 V p–p
Gain Tempco 25 C V 100 ppm/C
Input Bias Current 25 C I V 1 A
Full IV 1 A
Input Offset Voltage Full VI 7 50 mV
Input Full-Scale Matching Full VI 6.0 % FS
Offset Adjustment Range Full VI 46 49 52 % FS
REFERENCE OUTPUT
Output Voltage Full VI 1.20 1.25 1.32 V
Temperature Coefficient Full V 50 ppm/C
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 110 MSPS
Minimum Conversion Rate Full IV 10 MSPS
Data to Clock Skew Full IV –0.5 +2.0 ns
t
BUFF
Full VI 4.7 s
t
STAH
Full VI 4.0 s
t
DHO
Full VI 0 s
t
DAL
Full VI 4.7 s
t
DAH
Full VI 4.0 s
t
DSU
Full VI 250 s
t
STASU
Full VI 4.7 s
t
STOSU
Full VI 4.0 s
HSYNC Input Frequency Full IV 15 110 kHz
Maximum PLL Clock Rate Full VI 110 MHz
Minimum PLL Clock Rate Full IV 12 MHz
PLL Jitter 25 C IV 400 700
1
ps p-p
Full IV 1000
1
ps p-p
Sampling Phase Tempco Full IV 15 ps/
C
DIGITAL INPUTS
Input Voltage, High (V
IH
) Full VI 2.5 V
Input Voltage, Low (V
IL
) Full VI 0.8 V
Input Voltage, High (V
IH
) Full V –1.0 A
Input Voltage, Low (V
IL
) Full V 1.0 A
Input Capacitance 25 C V 3 pF
DIGITAL OUTPUTS
Output Voltage, High (V
OH
) Full VI V
D
– 0.1 V
Output Voltage, Low (V
OL
) Full VI 0.1 V
Duty Cycle DATACK Full IV 45 50 55 %
Output Coding Binary

--11--
Plasma Display PD421
Test AD9883KST-110
Parameter Temp Level Min Typ Max Unit
POWER SUPPLY
V
D
Supply Voltage Full IV 3.0 3.3 3.6 V
V
DD
Supply Voltage Full IV 2.2 3.3 3.6 V
P
VD
Supply Voltage Full IV 3.0 3.3 3.6 V
I
D
Supply Current (V )
D
5 C V 132 mA
I
DD
Supply Current (V
DD
)
2
25 C V 19 mA
IP
VD
Supply Current (P )
VD
5C V 8 mA
Total Power Dissipation Full VI 525 650 mW
Power-Down Supply Current Full VI 5 10 mA
Power-Down Dissipation Full VI 16.5 33 mW
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power 25 C V 300 MHz
Transient Response 25 C V 2 ns
Overvoltage Recovery Time 25 C V 1.5 ns
Signal-to-Noise Ratio (SNR) 25 C V 44 dB
(Without Harmonics) Full V 43 dB
f
IN
= 40.7 MHz
Crosstalk Full V 55 dBc
THERMAL CHARACTERISTICS
JC
Junction-to-Case
Thermal Resistance V 16 C/W
JA
Junction-to-Am ient
Thermal Resistance V 35 C/W
NOTES
1
VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.
2
DATACK Load = 15 pF, Data Load = 5 pF.
Specifications su ject to change without notice.
2
2

--12--
MC68HC705BD7B
CXA2151Q
Description
The CXA2151Q is a ipolar IC developed for multi
scan TVs, and incorporates a four system video
switch (including HV sync signal processing) and a
YC Cr output matrix circuit.
Features
•Supports the I
2C us
•Supports multi scan
•Four system video switch (of which two systems support D3 pins)
•Matrix circuit
•Each YC Cr output can e switched etween 0dB, 6dB (gain adjusta le) and mute.
•Sync signal automatic identification circuit (with fixed mode)
•Sync separation circuit (supports HD)
•HD Tri-level sync identification circuit
•Sync signal frequency counter ( oth H and V)
•Dummy sync output
Applications
Multi scan TVs
Structure
Bipolar silicon monolithic IC
A solute Maximum Ratings(Ta = 25°C, GND1, 2, 3 = 0V)
•Supply voltage VCC1, 2, 3 –0.3 to +5.5 V
•Operating temperature Topr –20 to +75 °C
•Storage temperature Tstg –65 to +150 °C
•Allowa le power dissipation PD1400 mW
(when mounted on a 50mm 50mm oard)
•Voltage at each pin –0.3 to VCC1, 2, 3 + 0.3 V
Recommended Operating Conditions
Supply voltage VCC1, 2, 3 5 ±0.25 V
48 pin QFP (Plastic)

--13--
Plasma Display PD421
Block Diagram
30
SCL
31
SDA
32
ADDRESS
27 SEL Y_OUT 26 SELCB_OUT 25 SELCR_OUT 20 EXTCLK/XTAL 18 IREF 40 Vcc1 48 GND1 28 Vcc2 24 GND2 12 Vcc3
6GND3
22 SELH_OUT
33
IN1_1
34
IN1_2
35
IN1_3
36
IN1_H/L1
37
IN1_V/L2
38
IN1_L3
39
IN1_SW
6dB
YP PrJ/YC Cr
MATRIX SELECTOR
6dB AMP.
YP PrU/YC Cr
GBR/YC Cr
41
IN2_1
42
IN2_2
43
IN2_3
44
IN2_H/L1
45
IN2_V/L2
46
IN2_L3
47
IN2_SW
1
IN3_1
2
IN3_2
3
IN3_3
4
IN3_H
5
IN3_V
7
IN4_1
8
IN4_2
9
IN4_3
10
IN4_H
11
15 16 13 14
IN4_V
I2C BUS
DEC.
IN1 to IN4 SELECTOR
SELSTB_1 SELSTB_2 DECL1_1 DECL2_1 DECL3_1 DECSW_1 DECL1_2 DECL2_2 DECL3_2 DECSW_2
1, 2, 3
HYSW
INPUT_SEL
MAT_OUT
GAIN_SEL
YGAIN CBGAIN CRGAIN
Y C Cr
EXISTENCE DISTINCTION
INTELLIGENT SYNC SEP .
3-STATE SYNC DET.
HSEP_SEL HD_TC V_TC
HS_MASK FIX_SYNC
PRIORITY RANKING HV > CS > SYNC ON Y/G
3S TATE MACRO
3 H V
H_WIDTH
H SYNC WIDTH
MACRO VISION
23 SEL V_OUT
DUMMY SYNC
CLOCK GEN.
SYNC COUNTER
H-NUMBER V-NUMBER
CLK_SEL
SELDUM
H_PH
YG_IN
YG_OUT
V_PH

--14--
General Description
The DS90C385 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams. A phase-locked transmit clock is transmit-
ted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. At a transmit clock frequency of 85
MHz, 24 bits of RGB data and 3 bits of LCD timing and
control data (FPLINE, FPFRAME, DRDY) are transmitted at
a rate of 595 Mbps per LVDS data channel. Using a 85 MHz
clock, the data throughput is 297.5 Mbytes/sec. Also avail-
able is the DS90C365 that converts 21 bits of LVCMOS/
LVTTL data into three LVDS (Low Voltage Differential Sig-
naling) data streams. Both transmitters can be programmed
for Rising edge strobe or Falling edge strobe through a
dedicated pin. A Rising edge or Falling edge strobe transmit-
ter will interoperate with a Falling edge strobe Receiver
(DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package which provides a 44 %
reduction in PCB footprint compared to the TSSOP package.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL interfaces.
Features
-20 to 85 MHz shift clock support
-Best±in±Class Set & Hold Times on TxINPUTs
-Tx power consumption <130 mW (typ) @85MHz
Grayscale
-Tx Power-down mode <200W (max)
-Supports VGA, SVGA, XGA and Single/Dual Pixel
SXGA.
-Narrow bus reduces cable size and cost
-Up to 2.38 Gbps throughput
-Up to 297.5 Megabytes/sec bandwidth
-345 mV (typ) swing LVDS devices for low EMI
-PLL requires no external components
-Compatible with TIA/EIA-644 LVDS standard
-Low profile 56-lead or 48-lead TSSOP package
-DS90C385 also available in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package
Block Diagrams
DS90C385
DS100868-1
Order Number DS90C385MTD or DS90C385SLC
See NS Package Number MTD56 or SLC64A
DS90C365
DS100868-29
Order Number DS90C365MTD
See NS Package Number MTD48
DS90C385

--15--
Plasma Display PD421
A solute MaximumRatings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distri utors for availa ility and specifications.
SupplyVoltage(V
CC
) -0.3V to +4V
CMOS/TTL InputVoltage -0.5V to (V
CC
+ 0.3V)
LVDS DriverOutputVoltage -0.3V to (V
CC
+ 0.3V)
LVDS OutputShort Circuit
Duration Continuous
JunctionTemperature +150 C
Storage Temperature -65 C to +150 C
Lead Temperature
(Soldering,4 sec) +260 C
Solder reflowTemperature
(20 sec forFBGA) +220 C
MaximumPackage Power Dissipation Capacity@25 C
MTD56(TSSOP) Package:
DS90C385MTD 1.63W
MTD48(TSSOP) Package:
DS90C365MTD 1.98W
SLC64 (FBGA) Package:
DS90C385SLC 2.0 W
Package Derating:
DS90C385MTD 12.5mW/ C a ove +25 C
Package Derating:
DS90C365MTD 16 mW/ C a ove +25 C
DS90C385SLC 10.2mW/ C a ove +25 C
ESD Rating
(HBM, 1.5kW, 100pF) >7kV
(EIAJ, 0W, 200pF) >500V
Latch Up Tolerance@25 C >+/-300mA
Recommended Operating
Conditions
Min Nom Max Units
SupplyVoltage(V
CC
) 3.0 3.3 3.6 V
Operating Free Air
Temperature(T
A
) -10 +25 +70 C
SupplyNoise Voltage(V
CC
) 100 mV
PP
TxCLKIN frequency 20 85 MHz
Electrical Characteristics
Over recommendedoperatingsupplyand temperatureranges unlessotherwisespecified.
Sym ol Parameter Conditions Min Typ Max Units
LVCMOS/LVTTL DC SPECIFICATIONS
V
IH
HighLevel InputVoltage 2.0 V
CC
V
V
IL
Low Level InputVoltage GND 0.8 V
V
CL
InputClamp Voltage I
CL
= -18 mA -0.79 -1.5 V
I
IN
InputCurrent V
IN
= 0.4V,2.5V or V
CC
+1.8 +10 A
V
IN
= GND -10 0 A
LVDS DC SPECIFICATIONS
V
OD
DifferentialOutputVoltage R
L
= 100W 250 345 450 mV
DV
OD
Change in V
OD
etween
complimentary outputstates
35 mV
V
OS
OffsetVoltage(Note 4) 1.125 1.25 1.375 V
DV
OS
Change in V
OS
etween
complimentary outputstates
35 mV
I
OS
OutputShort Circuit Current V
OUT
= 0V, R
L
= 100W -3.5 -5 mA
I
OZ
OutputTRI-STATE Current Power Down= 0V,
V
OUT
=0VorV
CC
+/-1+/-10 A
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter SupplyCurrent
Worst Case
DS90C385
R
L
= 100W,
C
L
= 5 pF,
Worst Case Pattern
(Figures 1, 4)
f = 32.5MHz 31 45 mA
f = 40 MHz 32 50 mA
f = 65 MHz 37 55 mA
f = 85 MHz 42 60 mA
ICCTG Transmitter SupplyCurrent
16 Grayscale
DS90C385
R
L
= 100W,
C
L
= 5 pF,
16 Grayscale Pattern
(Figures 2, 4)
f = 32.5MHz 29 38 mA
f = 40 MHz 30 40 mA
f = 65 MHz 35 45 mA
f = 85 MHz 39 50 mA
ICCTW TransmitterSupply Current
Worst Case
DS90C365
R
L
= 100 W,
C
L
= 5 pF,
Worst Case Pattern
(Figures 1, 4)
f = 32.5MHz 28 42 mA
f = 40 MHz 29 47 mA
f = 65 MHz 34 52 mA
f = 85 MHz 39 57 mA
o
o
o
o
o
o
o
o
o
o

--16--
Electrical Characteristics(Continued)
Over recommended operating supply and temperature ranges unlessotherwise specified.
Over recommended operating supply and temperature ranges unlessotherwise specified.
Over recommended operating supply and temperature ranges unlessotherwise specified.
Sym ol Parameter Conditions Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
ICCTG TransmitterSupply Current
16 Grayscale
DS90C365
R
L
= 100W,
C
L
= 5 pF,
16 Grayscale Pattern
(Figures 3, 4)
f = 32.5MHz 26 35 mA
f = 40 MHz 27 37 mA
f = 65 MHz 32 42 mA
f = 85 MHz 36 47 mA
ICCTZ TransmitterSupply Current
Power Down
Power Down= Low
DriverOutputsin TRI-STATE under
Power DownMode
10 55 A
Note 1: ™A solute Maximum Ratings"are those values eyondwhichthe safetyof the device cannot e guaranteed.They are notmeantto implythatthe device
should e operatedat these limits.The ta lesof ™Electrical Characteristics" specify conditions for deviceoperation.
Note 2: Typicalvalues are givenforVCC = 3.3V and TA= +25C.
Note 3: Currentinto device pins is definedas positive.Currentout of device pins is definedas negative.Voltagesare referencedto groundunless otherwise
specified(exceptVOD and DVOD).
Note 4: VOS previously referredas VCM.
Recommended Transmitter Input Characteristics
Sym ol Parameter Min Typ Max Units
TCIT TxCLK IN TransitionTime
(Figure 6) 1.0 6.0 ns
TCIP TxCLK IN Period
(Figure 7) 11.76 T 50 ns
TCIH TxCLK IN High Time
(Figure 7) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time
(Figure 7) 0.35T 0.5T 0.65T ns
TXIT TxIN TransitionTime 1.5 6.0 ns
Transmitter Switching Characteristics
Sym ol Parameter Min Typ Max Units
LLHT LVDS Low-to-HighTransitionTime
(Figure 5) 0.75 1.5 ns
LHLT LVDS High-to-LowTransitionTime
(Figure 5) 0.75 1.5 ns
TPPos0 TransmitterOutputPulse PositionforBit 0
(Figures 13, 14)
(Note 5)
f = 40 MHz -0.25 0 0.25 ns
TPPos1 TransmitterOutputPulse PositionforBit 1 3.32 3.57 3.82 ns
TPPos2 TransmitterOutputPulse PositionforBit 2 6.89 7.14 7.39 ns
TPPos3 TransmitterOutputPulse PositionforBit 3 10.46 10.71 10.96 ns
TPPos4 TransmitterOutputPulse PositionforBit 4 14.04 14.29 14.54 ns
TPPos5 TransmitterOutputPulse PositionforBit 5 17.61 17.86 18.11 ns
TPPos6 TransmitterOutputPulse PositionforBit 6 21.18 21.43 21.68 ns
TPPos0 TransmitterOutputPulse PositionforBit 0
(Figures 13, 14)
(Note 5)
f = 65 MHz -0.20 0 0.20 ns
TPPos1 TransmitterOutputPulse PositionforBit 1 2.00 2.20 2.40 ns
TPPos2 TransmitterOutputPulse PositionforBit 2 4.20 4.40 4.60 ns
TPPos3 TransmitterOutputPulse PositionforBit 3 6.39 6.59 6.79 ns
TPPos4 TransmitterOutputPulse PositionforBit 4 8.59 8.79 8.99 ns
TPPos5 TransmitterOutputPulse PositionforBit 5 10.79 10.99 11.19 ns
TPPos6 TransmitterOutputPulse PositionforBit 6 12.99 13.19 13.39 ns

--17--
Plasma Display PD421
Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unlessotherwise specified
Sym ol Parameter Min Typ Max Units
TPPos0 TransmitterOutputPulse PositionforBit 0
(Figures 13, 14)
(Note 5)
f = 85 MHz -0.20 0 0.20 ns
TPPos1 TransmitterOutput Pulse Position forBit 1
TransmitterOutput Pulse Position forBit 2
TransmitterOutput Pulse Position forBit 3
TransmitterOutput Pulse Position forBit 4
TransmitterOutput Pulse Position forBit 5
TransmitterOutput Pulse Position forBit 6
1.48 1.68 1.88 ns
TPPos2 3.16 3.36 3.56 ns
TPPos3 4.84 5.04 5.24 ns
TPPos4 6.52 6.72 6.92 ns
TPPos5 8.20 8.40 8.60 ns
TPPos6 9.88 10.08 10.28 ns
TSTC TxIN Setup to TxCLK IN
(Figure 7) 2.5 ns
THTC TxIN Holdto TxCLK IN
(Figure 7)
TCCD TxCLK IN to TxCLK OUT Delay
(Figure 8) T
A
= 25 C, V
CC
= 3.3V
3.8
0
6.3 ns
ns
TxCLK IN to TxCLK OUT Delay
(Figure 8) 2.8 7.1 ns
TJCC TransmitterJitter Cycle-to-Cycle
(Figures 15, 16) (Note 6) f = 85 MHz 110 150 ps
f = 65 MHz 210 230 ps
f = 40 MHz 350 370 ps
TPLLS Transmitter Phase Lock Loop Set
(Figure 9) 10 ms
TPDD Transmitter Power DownDelay
(Figure 12) 100 ns
Note 5: The Minimumand MaximumLimits are ased on statisticalanalysis of the device performanceover process, voltage,and temperatureranges. This
parameteris functionality testedonly on AutomaticTest Equipment(ATE).
Note 6: The limitsare ased on ench characterization of the device'sjitterresponseover the powersupplyvoltagerange.Outputclock jitteris measured with a
cycle-to-cyclejitterof +/˛3nsappliedto the inputclocksignalwhiledata inputsare switching(See Figures15 and 16).A jitterevent of 3ns,represents worsecase
jumpin theclockedge frommostgraphicscontroller VGA chipscurrently availa le.Thisparameteris usedwhencalculatingsystemmarginas descri ed in AN-1059.
AC Timing Diagrams
DS100868-4
FIGURE 1. ™Worst Case∫Test Pattern (Note 7)

--18--
DESCRIPTION
The P89C51RB2/RC2/RD2 device contains a non-volatile
16kB/32kB/64kB Flash program memory that is both parallel
programmable and serial In-System and In-Application
Programmable. In-System Programming (ISP) allows the user to
download new code while the microcontroller sits in the application.
In-Application Programming (IAP) means that the microcontroller
fetches new program code and reprograms itself while in the
system. This allows for remote programming over a modem link.
A default serial loader (boot loader) program in ROM allows serial
In-System programming of the Flash memory via the UART without
the need for a loader in the Flash code. For In-Application
Programming, the user program erases and reprograms the Flash
memory by use of standard routines contained in ROM.
This device executes one machine cycle in 6 clock cycles, hence
providing twice the speed of a conventional 80C51. An OTP
configuration bit lets the user select conventional 12 clock timing
if desired.
This device is a Single-Chip 8-Bit Microcontroller manufactured in
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The instruction set is 100% compatible with
the 80C51 instruction set.
The device also has four 8-bit I/O ports, three 16-bit timer/event
counters, a multi-source, four-priority-level, nested interrupt structure,
an enhanced UART and on-chip oscillator and timing circuits.
The added features of the P89C51RB2/RC2/RD2 makes it a
powerful microcontroller for applications that require pulse width
modulation, high-speed I/O and up/down counting capabilities such
as motor control.
FEATURES
-80C51 Central Processing Unit
-On-chip Flash Program Memory with In-System Programming
(ISP) and In-Application Programming (IAP) capability
-Boot ROM contains low level Flash programming routines for
downloading via the UART
-Can be programmed by the end-user application (IAP)
-6 clocks per machine cycle operation (standard)
-12 clocks per machine cycle operation (optional)
-Speed up to 20 MHz with 6 clock cycles per machine cycle
(40 MHz equivalent performance); up to 33 MHz with 12 clocks
per machine cycle
-Fully static operation
-RAM expandable externally to 64 kB
-4 level priority interrupt
-7 interrupt sources
-Four 8-bit I/O ports
-Full-duplex enhanced UART
±Framing error detection
±Automatic address recognition
-Power control modes
±Clock can be stopped and resumed
±Idle mode
±Power down mode
-Programmable clock out
-Second DPTR register
-Asynchronous port reset
-Low EMI (inhibit ALE)
-Programmable Counter Array (PCA)
±PWM
±Capture/compare
P89C51 D2BA

--19--
Plasma Display PD421
ORDERING INFORMATION
PHILIPS
(EXCEPT NORTH
AMER
I
CA)
PHILIPS NORTH
AMER
I
CA
MEMORY
TEMPERA TURE
VOLTAGE
FREQUENCY (MHz)
AMER CA)
PART ORDER
NUMBER
PART MARKING
AMER CA
PART ORDER
NUMBER
FLASH RAM RANGE (5C)
AND PACKAGE
VOLTAGE
RANGE 6 CLOCK
MODE
12 CLOCK
MODE
DWG #
1P89C51RB2HBA P89C51RB2BA 16 kB 512 B 0 to +70, PLCC 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
2P89C51RB2HBBD P89C51RB2BBD 16 kB 512 B 0 to +70, LQFP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
3P89C51RC2HBP P89C51RC2BP 32 kB 512 B 0 to +70, PDIP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1
4P89C51RC2HBA P89C51RC2BA 32 kB 512 B 0 to +70, PLCC 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
5P89C51RC2HFA P89C51RC2FA 32 kB 512 B ±40 to +85, PLCC 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
6P89C51RC2HBBD P89C51RC2BBD 32 kB 512 B 0 to +70, LQFP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
7P89C51RC2HFBD P89C51RC2FBD 32 kB 512 B ±40 to +85, LQFP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
8P89C51RD2HBP P89C51RD2BP 64 kB 1 kB 0 to +70, PDIP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1
9P89C51RD2HBA P89C51RD2BA 64 kB 1 kB 0 to +70, PLCC 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
10 P89C51RD2HBBD P89C51RD2BBD 64 kB 1 kB 0 to +70, LQFP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1