IDT 8A3 Series Operating instructions

1©2018 Integrated Device Technology, Inc September 12, 2018
How to Use this Document
The 8A3xxxx Family Programming Guide contains information on how to access internal registers and what those registers do in detail for all
devices in the 8A3xxxx family. Not all devices in the family support all the same features or quantities of logic blocks, however the register
blocks all behave and are addressed at the same locations in all device. Some devices will not make use of all register blocks since the
associated feature or block of circuitry may not be available in that particular device. A Programming Guide Addendum for each specific device
will indicate which register modules are support in that device.
In addition, there are several other pieces of documentation that describe specific functions or details for the family or individual devices.
Table 1 shows related documents.
Table 1: Related Documentation for Devices in the 8A3xxx Family
Document Title Document Description
<device name> Datasheet Contains a functional overview of the device and hardware-design related details
including pinouts, AC & DC specifications and applications information related to
power filtering and terminations.
<device name>-<dash code> Datasheet Addendum Indicates pre-programmed power-up / reset configurations of this specific ‘dash
code’ part number
8A3xxxx Family Programming Guide (v4.7) Contains detailed register descriptions and address maps for all members of the
family of devices. Please check the <device name> datasheet to check the version
used by that device. All devices that use this version number use some subset of
this register map, as indicated in their device-specific Programming Guide
Addendum document..
Evaluation Board Reference Manual Describes the Evaluation Board. Evaluation boards are available for the 8A34001
(144BGA) or 8A34002 (72QFN) devices. These devices contain a superset of the
functionality available in all other members of the 8A3xxxx Family. So they can
serve as evaluation tools for any of the less fully-featured family members.
Timing Commander Personality User Manual Detailed description of how to use IDT’s Timing Commander configuration tool. At
this time, a personality file is only available for 8A34001. This personality contains a
superset of the functionality available in all other members of the 8A3xxxx family.
Since all members of the 8A3xxxx family share register locations and resource
numbering, configurations generated using the 8A34001 personality can be used in
any member of the 8A3xxxx family. Functionality that is not available on the other
family members will of course not respond to any configuration of it that is made.
This document discusses the registers supported by a particular version of the Firmware (FW) running on the
internal micro-controller within the 8A3xxxx family of devices. Register maps may change between major releases
of the FW, so please check the Revision History section of this document to ensure this document aligns with the
FW revision being used on the device. FW version numbering follows the format:
v<major release number>.<minor release number>.<hotfix number>
8A3xxxx
v4.7
8A3xxxx Family Programming Guide

2©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
This document is broken into several sections:
▪Introduction (this section) - describes documentation structure for the 8A3xxxx
▪Serial Port Overview - repeating selected information from the 8A3xxxx Datasheet to discuss how the serial ports function, overall device
memory map and register addresses
▪I2C Slave Operation - discusses register accessing topics related to I2C operation on a serial port
▪SPI Operation - discusses register accessing topics related to SPI operation on a serial port
▪Register Table Overview - discusses register table format and abbreviations
▪Register Set Descriptions - describes a set of registers that is made available for users to quickly and simply access the commonly-used
features of the 8A3xxxx.
▪Revision History
▪IDT Contact information

3©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
Serial Port Overview
The 8A3xxxx family supports up to 3 serial ports. One is a dedicated I2CMaster port used for loading configuration data at reset and the other
two are configurable slave I2Cor SPI ports that can be used at any time after the reset sequence is complete to monitor and/or configure the
device. In some variants of the device, the I2C Master port share pins with an I2C slave port.
Operation of the I2C Master Port is only used by the device to access an external serial EEPROM and so won’t be discussed here.
Two slave ports have been provided to allow independent access to any of the device’s internal registers. This allows high priority accesses
not to be queued behind lower priority ones on a shared external serial interface. Note that internal to the device, both slave serial ports
access a single instance of each register over a shared internal bus. The device ensures that a burst access on one bus will complete
atomically once begun, before the other port can gain access to the shared internal bus or registers. However it does not guarantee the order
in which the two serial ports will be granted access to any shared resource.
Please refer to the appropriate section below for details on the operation of the slave I2C or SPI ports.
Either slave port can be reconfigured over either serial port at any time by accessing the appropriate registers. This includes both configuration
options with each protocol or switching between protocols (I2C to SPI or vice versa). However it is recommended that the full operating mode
configuration, including page sizes for registers, for each serial port be set in the initial configuration data read from OTP or external EEPROM
(see Device Initial Configuration in the 8A3xxxx Datasheet for details).
Addressing Registers within a Device
The address space that is externally accessible within the device is 64kbytes in size and so needs 16-bits of address offset information to be
provided during slave serial port accesses. Of that 64kbytes, only the upper 32kbytes contains user accessible registers.
The user may choose to operate either serial port providing the full offset address within each burst or to operate in a paged mode where part
of the address offset is provided in each transaction and part comes from an internal page register in each serial port. The decision may be
made independently on each slave serial port and each slave serial port has its own page register to avoid conflicts. Figure 1 shows how page
register and offset bytes from each serial transaction interact to address a register within the 8A3xxxx.
Figure 1: Register Addressing Modes via Serial Port
I2C Slave Operation
The I2C slave protocol of the 8A3xxx family complies with Version 2.1 of the I2C specification. Figure 2 shows the sequence of states on the
I2C SDATA signal for the supported modes of operation.

4©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
Figure 2: I2C Slave Sequencing Diagram
The Dev Addr shown in the figure represents the base address of the 8A3xxxx device. This 7-bit value can be set in an internal register which
can have a user-defined value loaded at reset from internal OTP memory or an external EEPROM. The default value if those methods are not
used is 0000000 (binary). Note that the levels on the S_A0 and S_A1 inputs can be used to control Bit 0 and Bit 1 (respectively) of this address.
These pins are available independently for each serial port. In I2C operation these inputs are expected to remain static. They have different
functions when the part is in SPI mode. The resulting base address is the I2C bus address that this device will respond to. The default address
may be over-written at any time.
When I2C operation is selected for either slave serial port, selection of 1-byte (1B) or 2-byte (2B) offset addressing must also be selected
independently for each slave serial port. These offsets are used in conjunction with the page register for each serial port to access registers
internal to the device. Because the I2C protocol already includes a read/write bit with the Dev Addr, all bits of the 1B or 2B offset field can be
used to address internal registers.
▪In 1B mode, the lower 8-bits of the register offset address come from the Offset Addr byte and the upper 8-bits come from the page register
(see Table 2 for description of the 8-bit I2C Page Register).
The page register can be accessed at any time, no matter what page the serial port is currently on, using an offset byte value of FCh. This
4-byte register must be written in a single burst write transaction. The page register is replicated on every register page to always be
accessible.
▪In 2B mode, the full 16-bit register address can be obtained from the Offset Addr bytes, so the page register only needs to be set once after
reset using a 3-byte burst access starting from address FFFDh (see Table 3 for description of the 16-bit I2C Page Register).
Table 2: I2C 1B Mode Page Register Bit Field Locations and Descriptions
Offset
Address
(Hex)
I2C 1B Mode Page Register Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
FC PAGE_ADDR[7:0]
FD PAGE_ADDR[15:8]
FE PAGE_ADDR[23:16]
FF PAGE_ADDR[31:24]
Sequential 16-bit Read
SDev Addr + W AData X AData X+1 A A Data X+n A
Offset Addr X
MSB ASr Dev Addr + R A
Sequential 16-bit Write
SDev Addr + W AData X PA Data X+1 A A Data X+n A
from master to slave
from slave to master
Offset Addr X
MSB A
S = start
Sr = repeated start
A = acknowledge
A= non-acknowledge
P = stop
Sequential 8-bit Read
SDev Addr + W AData X AData X+1 A A Data X+n A POffset Addr X ASr Dev Addr + R A
Sequential 8-bit Write
SDev Addr + W AData X PA Data X+1 A A Data X+n A
Offset Addr X A
Offset Addr X
LSB A
Offset Addr X
LSB A

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8A3xxxx Family Programming Guide
I2C burst mode operation is required to ensure data integrity of multi-byte registers. When accessing a multi-byte register, all data bytes must
be written or read in a single I2C burst access. Bursts may be of greater length if desired, but must not extend beyond the end of the register
page (Offset Addr FFh in 1B mode, no limit in 2B mode). An internal address pointer is incremented automatically as each data byte is written
or read.
2C 1-byte (1B) Addressing Examples
8A3xxxx I2C 7-bit I2C address is 0x5B with LSB=R/W
Example Write “0x50” to register 0xCBE4
B6* FC 00 CB 10 20 #Set Page Register, *I2C Address is left-shifted one bit.
B6 E4 50 #Write data 5B to CB E4
I2C 1B Mode Page Register Bit Field Descriptions
Bit Field Name FieldType Default Value Description
PAGE_ADDR[7:0] R/W 00h The values in this field are always replaced by the bits in I2C transaction itself
and so have no meaning.
PAGE_ADDR[15:8] R/W 00h Select which register page to access. Forms the upper 8-bits of the 16-bit
register address. Only values of 80h or higher should be used. Lower addresses
are not user-accessible
PAGE_ADDR[23:16] R/W 10h Must be set to 10h in all cases
PAGE_ADDR[31:24] R/W 20h Must be set to 20h in all cases
Table 3: I2C 2B Mode Page Register Bit Field Locations and Descriptions
Offset
Address
(Hex)
I2C 2B Mode Page Register Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
FFFD1PAGE_ADDR[15:8]
FFFE PAGE_ADDR[23:16]
FFFF PAGE_ADDR[31:24]
1. Burst access must begin at this non-aligned offset and all 3 bytes must be written in the same I2C burst access. A burst beginning at the
32-bit aligned address of FFFCh will not correctly set this register.
I2C 2B Mode Page Register Bit Field Descriptions
Bit Field Name FieldType Default Value Description
PAGE_ADDR[15:8] R/W 00h The values in this field are always replaced by the bits in I2C transaction itself
and so have no meaning.
PAGE_ADDR[23:16] R/W 10h Must be set to 10h in all cases
PAGE_ADDR[31:24] R/W 20h Must be set to 20h in all cases

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8A3xxxx Family Programming Guide
Example read from register 0xC024
B6* FC 00 C0 10 20 #Set Page Register, *I2C Address is left-shifted one bit.
B6 24* #Set I2C pointer to 0xC024, *I2C instruction should use “No Stop”
B7 <read back data> #Send address with Read bit set.
I2C 2-byte (2B) Addressing
8A3xxxx I2C 7-bit I2C address is 0x5B with LSB=R/W
Example Write “50” to register 0xCBE4
B6* FF FD 00 10 20 #Set Page Register, *I2C Address is left-shifted one bit.
B6 CB E4 50 #Write data to CB E4
Example read from register 0xC024:
B6* FF FD 00 10 20 #Set Page Register (*I2C Address is left-shifted one bit.)
B6 C0 24* #Set I2C pointer to 0xC024, *I2C instruction should use “No Stop”
B7 <read back data> #Send address with Read bit set.
SPI Operation
The 8A3xxxx Family devices support SPI operation on their main and alternate serial ports. Figure 3 shows the sequencing of address and
data on the serial port in SPI mode.
Figure 3: SPI Sequencing Diagram
Each serial port can be independently configured for the following settings. These settings can come from register defaults or from an internal
OTP or external EEPROM configuration loaded at reset:
— 1-byte (1B) or 2-byte (2B) offset addressing (see Figure 1)
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Hi-Z
CS
SCLK
SDI
(4-wire)
SDIO
(4-wire)
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14R/W
CS
SCLK
SDI
(4-wire)
SDIO
(4-wire)
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Hi-Z
SPI Read Sequence*
SPI Write Sequence*
XX (SDI unused while data being read)
A14-A7 are omitted in 7b SPI Addressing Mode Data byte from Address provided Data byte from Address + 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
A14-A7 are omitted in 7b SPI Addressing Mode Data byte from Address provided Data byte from Address + 1
* refer to timing diagrams for exact timing relationships
* refer to timing diagrams for exact timing relationships
SDIO
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13R/W
SDIO
(3-wire) D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDIO driven by Master SDIO driven by Slave

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8A3xxxx Family Programming Guide
– In 1B operation, the 16-bit register address is formed by using the 7-bits of address supplied in the SPI access and taking the upper
9-bits from the page register.The page register is accessed, no matter what page the serial port is currently on, using an Offset Address
of 7Ch - 7Fh. It must be accessed in a single 4-byte burst write transaction. The page register is replicated on every register page to
always be accessible.
– In 2B operation, the 16-bit register address is formed by using the 15-bits of address supplied in the SPI access and taking the upper
1-bit from the page register. Note that this bit will always be ‘1’ for register accesses, so the page register only needs to be set once
in 2B operation. The page register can be accessed, no matter what page the serial port is currently on, using an Offset Address of
7FFDh - 7FFFh. It should be accessed in a single 3-byte burst write transaction to set it. The page register is replicated on every
register page to always be accessible.
— Data sampling on falling or rising edge of SCLK
— Output (read) data positioning relative to active SCLK edge
— 4-wire (SCLK, SCSb, SDATA, SDO) or 3-wire (SCLK, SCSb, SDATA) operation
– In 3-wire mode, SDATA is a bi-directional data pin.
— Output signal protocol compatibility / drive strength and termination voltage
Table 4: SPI 1B Mode Page Register Bit Field Locations and Descriptions
Offset
Address
(Hex)
SPI 1B Mode Page Register Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
7C PAGE_ADDR
[7]
PAGE_ADDR[6:0]
7D PAGE_ADDR[15:8]
7E PAGE_ADDR[23:16]
7F PAGE_ADDR[31:24]
SPI 1BMode Page Register Bit Field Descriptions
Bit Field Name FieldType Default Value Description
PAGE_ADDR[6:0] R/W - The values in this field are always replaced by the bits in SPI transaction itself
and so have no meaning.
PAGE_ADDR[15:7] R/W 000000000b Select which register page to access. Forms the upper 9-bits of the 16-bit
register address. Only values of 100000000b or higher should be used. Lower
addresses are not user-accessible
PAGE_ADDR[23:16] R/W 10h Must be set to 10h in all cases
PAGE_ADDR[31:24] R/W 20h Must be set to 20h in all cases

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8A3xxxx Family Programming Guide
SPI burst mode operation is required to ensure data integrity of multi-byte registers. When accessing a multi-byte register, all data bytes must
be written or read in a single SPI burst access. Bursts may be of greater length if desired, but must not extend beyond the end of the register
page. An internal address pointer is incremented automatically as each data byte is written or read.
SPI 1-byte (1B) Addressing Example
Example Write to “50” to register 0xCBE4
7C 80 CB 10 20 #Set Page register
64* 50 #*MSB is 0 for write transactions
Example Read from 0xC024:
7C 00 C0 10 20 #Set Page register
A4* 00 #*MSB is set, so this is a read command
SPI 2-byte (2B) Addressing Example
Example Write to “50” to register 0xCBE4
7F FD 80 10 20 #Set Page register
4B E4* 50 #*MSB is 0 for write transactions
Example Read from 0xC024:
7F FD 80 10 20 #Set Page register
C0* 24 00 #*MSB is set, so this is a read command
Table 5: SPI 2B Mode Page Register Bit Field Locations and Descriptions
Offset
Address
(Hex)
SPI 2B Mode Page Register Bit Field Locations
D7 D6 D5 D4 D3 D2 D1 D0
7FFD1PAGE_ADDR
[15]
PAGE_ADDR[14:8]
7FFE PAGE_ADDR[23:16]
7FFF PAGE_ADDR[31:24]
1. Burst access must begin at this non-aligned offset and all 3 bytes must be written in the same SPI burst access. A burst beginning at the
32-bit aligned address of 7FFCh will not correctly set this register.
SPI 2B Mode Page Register Bit Field Descriptions
Bit Field Name FieldType Default Value Description
PAGE_ADDR[14:8] R/W 0000000b The values in this field are always replaced by the bits in SPI transaction itself
and so have no meaning.
PAGE_ADDR[15] R/W 0b Select which register page to access. Forms the most-significant bit of the 16-bit
register address. Only a value of 1b should be used. Lower addresses are not
user-accessible
PAGE_ADDR[23:16] R/W 10h Must be set to 10h in all cases
PAGE_ADDR[31:24] R/W 20h Must be set to 20h in all cases

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8A3xxxx Family Programming Guide
Register Table Overview
When programming an 8A3xxxx family device, it is necessary to read or write values to one or more ‘bit-fields’ within the device. A bit-field
provides status and/or control information on a single aspect of a single feature. A bit field may be as small as a single-bit or many bytes in
length. A bit-field should be treated as an indivisible entity and all bytes of each bit-field should be read or written in a single serial port burst.
Access to bit-fields is performed using byte-oriented addressing. A bit-field may take up multiple byte address and/or multiple bit-fields may
occupy a single byte. When there are multiple bit-fields within a single byte, all bit fields are read from or written to during an access to that
byte address over the serial port. When a bit-field spans multiple byte addresses, all bytes should be read or written in the same serial port
burst transaction to ensure consistency. For bit-fields spanning multiple bytes, the least-significant bits of that bit-field are contained in the byte
with the lowest address.
Bit-fields are grouped into registers and registers are in turn grouped into modules. In the documentation that follows, bit-fields are shown
mapped into register bytes in a table called a Bit-Field Location table. The function of each bit-field is shown in an associated Bit-Field
Description table. One or more bit-fields are grouped into a register. Registers show an address offset for each byte within that register.

10©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
A number of registers are grouped together into a module. In general a module contains all the registers needed to interact with a functional
block within the device. Each module in the standard register set is listed in a Register Module Index table showing its module base address,
a brief description of the module’s function and a link to that module’s location in the document. In each module’s sub-section is a similar table
listing all the registers within that module, a brief description of the register and a link to that register’s detailed description. This is shown in
Figure 4
Figure 4: Finding a Register’s Detailed Description in this Document.
Many register modules include a trigger register at the end of the module that must be written to for any other
register changes within that module to take effect. This allows multiple parameters to be setup then all to take
effect at the same time for a particular function within the device. Where present, the trigger register is always the
last register in the module to allow a burst write to be used, triggering on the last write of the burst. Users must
ensure that the trigger register is written to, even if its contents don’t change to trigger the module update.

11©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
The device contains multiple copies of many functional blocks and each will have its own associated register module for status and control. To
keep the documentation clear and concise, only the first instance of a register module for a specific functional block will be shown in detail.
The module table will show all instantiations of the module with their unique base addresses, but the links will all point to the same descriptive
section (see blue arrows in Figure 5). Please ensure that when addressing a register that the base address of the correct instantiation of the
module is used (see red arrows in Figure 5). Note that the base address indicated in the table description is for the first instantiation of the
module only (see green arrow in Figure 5). For example, as shown below, to access the DPLL_MANUAL_HOLDOVER_VALUE bit-field for
DPLL4, take the base address of that instantiation (C480h) and add the register offset of that specific register (008h). Note that since this
bit-field is more than one byte, all bytes should be accessed in a single serial port burst transaction starting at C488h.
Figure 5: Determining the Address to Access a Specific Register.

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8A3xxxx Family Programming Guide
Terminology
The following terminology and abbreviations are used in the register tables.
If a bit-field has more than a single bit, the bit-field will be written as BIT_FIELD_NAME[msb:lsb] (e.g.
DPLL_MANUAL_HOLDOVER_VALUE[39:0]
Binary numbers will be written with a lowercase ‘b’ after them (e.g. 0101b )
Hexadecimal numbers will be written with a lowercase ‘h’ after them (e.g. C480h).
R/W indicates a register is readable and write-able by the user
R/O indicates that a register should only be read by the user. Writing to a R/O register has an undefined effect.
W/O indicates that a register should only be written to by the user. The read value is undefined and has no associated meaning.
RW1C indicates a register that can be read, but a ‘1’ needs to be written to the bit to clear it back to 0. This is generally used for ‘sticky’ status
bits that are latched high whenever a transient condition occurs. The user will need to write to clear the latched status.
N/A means Not Applicable. This is only used for Reserved bit-fields who’s behaviour is not defined.

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Register Set Descriptions
Table 6: Register Set Module Index
ModuleBaseAddress
(Hex) Link Module Description
8180h Module: HW_REVISION Hardware Revision ID register
C000h Module: RESET_CTRL General reset management.
C014h Module: GENERAL_STATUS Chip hardware status registers.
C03Ch Module: STATUS Live status of alarms and events.
C160h Module: GPIO_USER_CONTROL GPIO user control.
C164h Module: STICKY_STATUS_CLEAR Sticky status clear.
C16Ch Module:
GPIO_TOD_NOTIFICATION_CLEAR
Clear GPIO output Time of Day read notification.
C170h RESERVED This module must not be modified from the read value
C180h RESERVED This module must not be modified from the read value
C188h Module: ALERT_CFG Notification configuration.
C194h Module: SYS_DPLL_XO System DPLL XO configuration.
C19Ch Module: SYS_APLL System APLL configuration.
C1B0h Module: INPUT_0 Input 0 configuration.
C1C0h INPUT_1 Input 1 configuration.
Same as INPUT_0.
C1D0h INPUT_2 Input 2 configuration.
Same as INPUT_0.
C200h INPUT_3 Input 3 configuration.
Same as INPUT_0.
C210h INPUT_4 Input 4 configuration.
Same as INPUT_0.
C220h INPUT_5 Input 5 configuration.
Same as INPUT_0.
C230h INPUT_6 Input 6 configuration.
Same as INPUT_0.
C240h INPUT_7 Input 7 configuration.
Same as INPUT_0.
C250h INPUT_8 Input 8 configuration.
Same as INPUT_0.
C260h INPUT_9 Input 9 configuration.
Same as INPUT_0.
C280h INPUT_10 Input 10 configuration.
Same as INPUT_0.

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8A3xxxx Family Programming Guide
C290h INPUT_11 Input 11 configuration.
Same as INPUT_0.
C2A0h INPUT_12 Input 12 configuration.
Same as INPUT_0.
C2B0h INPUT_13 Input 13 configuration.
Same as INPUT_0.
C2C0h INPUT_14 Input 14 configuration.
Same as INPUT_0.
C2D0h INPUT_15 Input 15 configuration.
Same as INPUT_0.
C2E0h Module: REF_MON_0 Reference monitor 0.
C2ECh REF_MON_1 Reference monitor 1.
Same as REF_MON_0.
C300h REF_MON_2 Reference monitor 2.
Same as REF_MON_0.
C30Ch REF_MON_3 Reference monitor 3.
Same as REF_MON_0.
C318h REF_MON_4 Reference monitor 4.
Same as REF_MON_0.
C324h REF_MON_5 Reference monitor 5.
Same as REF_MON_0.
C330h REF_MON_6 Reference monitor 6.
Same as REF_MON_0.
C33Ch REF_MON_7 Reference monitor 7.
Same as REF_MON_0.
C348h REF_MON_8 Reference monitor 8.
Same as REF_MON_0.
C354h REF_MON_9 Reference monitor 9.
Same as REF_MON_0.
C360h REF_MON_10 Reference monitor 10.
Same as REF_MON_0.
C36Ch REF_MON_11 Reference monitor 11.
Same as REF_MON_0.
C380h REF_MON_12 Reference monitor 12.
Same as REF_MON_0.
C38Ch REF_MON_13 Reference monitor 13.
Same as REF_MON_0.
C398h REF_MON_14 Reference monitor 14.
Same as REF_MON_0.
Table 6: Register Set Module Index
ModuleBaseAddress
(Hex) Link Module Description

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C3A4h REF_MON_15 Reference monitor 15.
Same as REF_MON_0.
C3B0h Module: DPLL_0 DPLL 0 configuration registers.
C400h DPLL_1 DPLL 1 registers.
Same as DPLL_0.
C438h DPLL_2 DPLL 2 registers.
Same as DPLL_0.
C480h DPLL_3 DPLL 3 registers.
Same as DPLL_0.
C4B8h DPLL_4 DPLL 4 registers.
Same as DPLL_0.
C500h DPLL_5 DPLL 5 registers.
Same as DPLL_0.
C538h DPLL_6 DPLL 6 registers.
Same as DPLL_0.
C580h DPLL_7 DPLL 7 registers.
Same as DPLL_0.
C5B8h Module: SYS_DPLL System DPLL registers.
C600h Module: DPLL_CTRL_0 DPLL 0 control registers.
C63Ch DPLL_CTRL_1 DPLL 1 control registers.
Same as DPLL_CTRL_0.
C680h DPLL_CTRL_2 DPLL 2 control registers.
Same as DPLL_CTRL_0.
C6BCh DPLL_CTRL_3 DPLL 3 control registers.
Same as DPLL_CTRL_0.
C700h DPLL_CTRL_4 DPLL 4 control registers.
Same as DPLL_CTRL_0.
C73Ch DPLL_CTRL_5 DPLL 5 control registers.
Same as DPLL_CTRL_0.
C780h DPLL_CTRL_6 DPLL 6 control registers.
Same as DPLL_CTRL_0.
C7BCh DPLL_CTRL_7 DPLL 7 control registers.
Same as DPLL_CTRL_0.
C800h Module: SYS_DPLL_CTRL System DPLL control registers.
C818h Module: DPLL_PHASE_0 DPLL 0 write phase.
C81Ch DPLL_PHASE_1 DPLL 1 write phase.
Same as DPLL_PHASE_0.
Table 6: Register Set Module Index
ModuleBaseAddress
(Hex) Link Module Description

16©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
C820h DPLL_PHASE_2 DPLL 2 write phase.
Same as DPLL_PHASE_0.
C824h DPLL_PHASE_3 DPLL 3 write phase.
Same as DPLL_PHASE_0.
C828h DPLL_PHASE_4 DPLL 4 write phase.
Same as DPLL_PHASE_0.
C82Ch DPLL_PHASE_5 DPLL 5 write phase.
Same as DPLL_PHASE_0.
C830h DPLL_PHASE_6 DPLL 6 write phase.
Same as DPLL_PHASE_0.
C834h DPLL_PHASE_7 DPLL 7 write phase.
Same as DPLL_PHASE_0.
C838h Module: DPLL_FREQ_0 DPLL 0 write frequency.
C840h DPLL_FREQ_1 DPLL 1 write frequency.
Same as DPLL_FREQ_0.
C848h DPLL_FREQ_2 DPLL 2 write frequency.
Same as DPLL_FREQ_0.
C850h DPLL_FREQ_3 DPLL 3 write frequency.
Same as DPLL_FREQ_0.
C858h DPLL_FREQ_4 DPLL 4 write frequency.
Same as DPLL_FREQ_0.
C860h DPLL_FREQ_5 DPLL 5 write frequency.
Same as DPLL_FREQ_0.
C868h DPLL_FREQ_6 DPLL 6 write frequency.
Same as DPLL_FREQ_0.
C870h DPLL_FREQ_7 DPLL 7 write frequency.
Same as DPLL_FREQ_0.
C880h Module: DPLL_PHASE_PULL_IN_0 DPLL 0 phase pull-in control.
C888h DPLL_PHASE_PULL_IN_1 DPLL 1 phase pull-in control.
Same as DPLL_PHASE_PULL_IN_0.
C890h DPLL_PHASE_PULL_IN_2 DPLL 2 phase pull-in control.
Same as DPLL_PHASE_PULL_IN_0.
C898h DPLL_PHASE_PULL_IN_3 DPLL 3 phase pull-in control.
Same as DPLL_PHASE_PULL_IN_0.
C8A0h DPLL_PHASE_PULL_IN_4 DPLL 4 phase pull-in control.
Same as DPLL_PHASE_PULL_IN_0.
C8A8h DPLL_PHASE_PULL_IN_5 DPLL 5 phase pull-in control.
Same as DPLL_PHASE_PULL_IN_0.
Table 6: Register Set Module Index
ModuleBaseAddress
(Hex) Link Module Description

17©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
C8B0h DPLL_PHASE_PULL_IN_6 DPLL 6 phase pull-in control.
Same as DPLL_PHASE_PULL_IN_0.
C8B8h DPLL_PHASE_PULL_IN_7 DPLL 7 phase pull-in control.
Same as DPLL_PHASE_PULL_IN_0.
C8C0h Module: GPIO_CFG GPIO global configuration.
C8C2h Module: GPIO_0 GPIO 0 registers.
C8D4h GPIO_1 GPIO 1 registers.
Same as GPIO_0.
C8E6h GPIO_2 GPIO 2 registers.
Same as GPIO_0.
C900h GPIO_3 GPIO 3 registers.
Same as GPIO_0.
C912h GPIO_4 GPIO 4 registers.
Same as GPIO_0.
C924h GPIO_5 GPIO 5 registers.
Same as GPIO_0.
C936h GPIO_6 GPIO 6 registers.
Same as GPIO_0.
C948h GPIO_7 GPIO 7 registers.
Same as GPIO_0.
C95Ah GPIO_8 GPIO 8 registers.
Same as GPIO_0.
C980h GPIO_9 GPIO 9 registers.
Same as GPIO_0.
C992h GPIO_10 GPIO 10 registers.
Same as GPIO_0.
C9A4h GPIO_11 GPIO 11 registers.
Same as GPIO_0.
C9B6h GPIO_12 GPIO 12 registers.
Same as GPIO_0.
C9C8h GPIO_13 GPIO 13 registers.
Same as GPIO_0.
C9DAh GPIO_14 GPIO 14 registers.
Same as GPIO_0.
CA00h GPIO_15 GPIO 15 registers.
Same as GPIO_0.
CA12h Module: OUT_DIV_MUX Output divider multiplexers.
CA14h Module: OUTPUT_0 Output 0 registers.
Table 6: Register Set Module Index
ModuleBaseAddress
(Hex) Link Module Description

18©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
CA24h OUTPUT_1 Output 1 register.
Same as OUTPUT_0.
CA34h OUTPUT_2 Output 2 register.
Same as OUTPUT_0.
CA44h OUTPUT_3 Output 3 register.
Same as OUTPUT_0.
CA54h OUTPUT_4 Output 4 register.
Same as OUTPUT_0.
CA64h OUTPUT_5 Output 5 register.
Same as OUTPUT_0.
CA80h OUTPUT_6 Output 6 register.
Same as OUTPUT_0.
CA90h OUTPUT_7 Output 7 register.
Same as OUTPUT_0.
CAA0h OUTPUT_8 Output 8 register.
Same as OUTPUT_0.
CAB0h OUTPUT_9 Output 9 register.
Same as OUTPUT_0.
CAC0h OUTPUT_10 Output 10 register.
Same as OUTPUT_0.
CAD0h OUTPUT_11 Output 11 register.
Same as OUTPUT_0.
CAE0h Module: SERIAL Serial Interfaces registers.
CB00h Module: PWM_ENCODER_0 PWM 0 encoder registers.
CB08h PWM_ENCODER_1 PWM 1 encoder registers.
Same as PWM_ENCODER_0.
CB10h PWM_ENCODER_2 PWM 2 encoder registers.
Same as PWM_ENCODER_0.
CB18h PWM_ENCODER_3 PWM 3 encoder registers.
Same as PWM_ENCODER_0.
CB20h PWM_ENCODER_4 PWM 4 encoder registers.
Same as PWM_ENCODER_0.
CB28h PWM_ENCODER_5 PWM 5 encoder registers.
Same as PWM_ENCODER_0.
CB30h PWM_ENCODER_6 PWM 6 encoder registers.
Same as PWM_ENCODER_0.
CB38h PWM_ENCODER_7 PWM 7 encoder registers.
Same as PWM_ENCODER_0.
CB40h Module: PWM_DECODER_0 PWM 0 decoder registers.
Table 6: Register Set Module Index
ModuleBaseAddress
(Hex) Link Module Description

19©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
CB48h PWM_DECODER_1 PWM 1 decoder registers.
Same as PWM_DECODER_0.
CB50h PWM_DECODER_2 PWM 2 decoder registers.
Same as PWM_DECODER_0.
CB58h PWM_DECODER_3 PWM 3 decoder registers.
Same as PWM_DECODER_0.
CB60h PWM_DECODER_4 PWM 4 decoder registers.
Same as PWM_DECODER_0.
CB68h PWM_DECODER_5 PWM 5 decoder registers.
Same as PWM_DECODER_0.
CB70h PWM_DECODER_6 PWM 6 decoder registers.
Same as PWM_DECODER_0.
CB80h PWM_DECODER_7 PWM 7 decoder registers.
Same as PWM_DECODER_0.
CB88h PWM_DECODER_8 PWM 8 decoder registers.
Same as PWM_DECODER_0.
CB90h PWM_DECODER_9 PWM 9 decoder registers.
Same as PWM_DECODER_0.
CB98h PWM_DECODER_10 PWM 10 decoder registers.
Same as PWM_DECODER_0.
CBA0h PWM_DECODER_11 PWM 11 decoder registers.
Same as PWM_DECODER_0.
CBA8h PWM_DECODER_12 PWM 12 decoder registers.
Same as PWM_DECODER_0.
CBB0h PWM_DECODER_13 PWM 13 decoder registers.
Same as PWM_DECODER_0.
CBB8h PWM_DECODER_14 PWM 14 decoder registers.
Same as PWM_DECODER_0.
CBC0h PWM_DECODER_15 PWM 15 decoder registers.
Same as PWM_DECODER_0.
CBC8h Module: PWM_USER_DATA PWM user data registers.
CBCCh Module: TOD_0 TOD 0 registers.
CBCEh TOD_1 TOD 1 registers.
Same as TOD_0.
CBD0h TOD_2 TOD 2 registers.
Same as TOD_0.
CBD2h TOD_3 TOD 3 registers.
Same as TOD_0.
CC00h Module: TOD_WRITE_0 Write TOD 0 registers.
Table 6: Register Set Module Index
ModuleBaseAddress
(Hex) Link Module Description

20©2018 Integrated Device Technology, Inc September 12, 2018
8A3xxxx Family Programming Guide
CC10h TOD_WRITE_1 Write TOD 1 registers.
Same as TOD_WRITE_0.
CC20h TOD_WRITE_2 Write TOD 2 registers.
Same as TOD_WRITE_0.
CC30h TOD_WRITE_3 Write TOD 3 registers.
Same as TOD_WRITE_0.
CC40h Module: TOD_READ_PRIMARY_0 Read TOD 0 primary registers.
CC50h TOD_READ_PRIMARY_1 Read TOD 1 primary registers.
Same as TOD_READ_PRIMARY_0.
CC60h TOD_READ_PRIMARY_2 Read TOD 2 primary registers.
Same as TOD_READ_PRIMARY_0.
CC80h TOD_READ_PRIMARY_3 Read TOD 3 primary registers.
Same as TOD_READ_PRIMARY_0.
CC90h Module: TOD_READ_SECONDARY_0 Read TOD 0 secondary registers.
CCA0h TOD_READ_SECONDARY_1 Read TOD 1 secondary registers.
Same as TOD_READ_SECONDARY_0.
CCB0h TOD_READ_SECONDARY_2 Read TOD 2 secondary registers.
Same as TOD_READ_SECONDARY_0.
CCC0h TOD_READ_SECONDARY_3 Read TOD 3 secondary registers.
Same as TOD_READ_SECONDARY_0.
CCD0h Module: OUTPUT_TDC_CFG Output TDC global configuration.
CD00h Module: OUTPUT_TDC_0 Output TDC 0.
CD08h OUTPUT_TDC_1 Output TDC 1.
Same as OUTPUT_TDC_0.
CD10h OUTPUT_TDC_2 Output TDC 2.
Same as OUTPUT_TDC_0.
CD18h OUTPUT_TDC_3 Output TDC 3.
Same as OUTPUT_TDC_0.
CD20h Module: INPUT_TDC Input TDC
CF50h Module: SCRATCH User multipurpose registers.
CF60h RESERVED This module must not be modified from the read value
CF68h Module: EEPROM EEPROM.
CF70h Module: OTP OTP.
CF80h Module: BYTE OTP registers.
D000h RESERVED This module must not be modified from the read value
Table 6: Register Set Module Index
ModuleBaseAddress
(Hex) Link Module Description