IDT VersaClock 6E Series Operating instructions

1©2018 Integrated Device Technology, Inc. August 30, 2018
Register Descriptions
The register descriptions section describes the behavior and function of the customer-programmable non-volatile-memory registers in the
VersaClock 6E family of clock generators. Table 1 showcases the array of products under the VersaClock 6E family.
For details of product operation, refer to the product datasheet.
VersaClock 6E Family Register Set
The device contains volatile (RAM) 8-bit registers and non-volatile 8-bit registers (Figure 1). The non-volatile registers are One-Time
Programmable (OTP), and bit values can only be changed from 1 (unburned state) to 0.
The OTP registers include factory trim data and four user configuration tables (Figure 1,Table 3). This document does not describe the
format or methods for programming factory trim data, which is programmed by the factory before shipment.
Each configuration table contains all the information to set up the device's output frequencies. When these configuration tables are
programmed, the device will automatically load the RAM registers with the desired configuration on power-up. The device initializes in
either I2C mode or selection-pin mode, depending on the state of the OUT0/SELB_I2C pin on power-up, and remains in the selected
mode until power is toggled (Table 2). When powered up in I²C mode, the first configuration table, CFG0, is loaded. When powered up in
selection-pin mode, the SEL0 and SEL1 inputs are decoded to select one of the four configuration tables CFG0-CFG3.
The RAM registers (Table 4) include Status registers for read-back of the device's operating conditions in I2C mode.
Figure 1. Register Maps
Table 1. VersaClock 6E Family Products
Product Description Package
5P49V6965 5-Output VersaClock 6E 24 pins
5P49V6967 8-Output VersaClock 6E with 4 LP-HCSL Outputs 40 pins
5P49V6968 12-Output VersaClock 6E with 8 LP-HCSL Outputs 48 pins
5P49V6975 5-Output VersaClock 6E with Internal Crystal 24 pins
VersaClock®6E Family Register Descriptions
and Programming Guide

2©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock®6E Family Register Descriptions and Programming Guide
Contents
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
VersaClock 6E Family Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
User Configuration Table Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I2C Interface and Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
VersaClock 6E Family Power-Up Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
OTP Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
In-System VersaClock 6E OTP Non-Volatile Programming via I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Default Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OTP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Factory Reserved Registers for Internal Use Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Configuration Register Detail and Functionality Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Shutdown Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting Up a Low-Power Shutdown Mode through I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Crystal Load Capacitor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Short Example of Programming Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PLL Pre-Divider Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PLL Fractional Feedback Divider and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PLL Loop Filter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fractional Output Dividers and Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Example of FOD calculation for SSCE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Output Divider Control Settings (Table 47 through Table 50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Output Divider Integer Settings (Table 51 through Table 58) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Output Divider Fractional and Spread Settings (Table 59 through Table 94) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Output Divider Skew Integer and Fractional Part Registers Settings (Table 95 through Table 107) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Clock Output Configurations Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock®6E Family Register Descriptions and Programming Guide
User Configuration Table Selection
At power-up, the voltage at OUT0_SEL_I2CB pin 24 is latched by the part and used to select the state of SEL0/SCL pin 9 and SEL1/SDA
pin 8 (Table 2).
If a weak pull-up (10kΩ) is placed on OUT0_SEL_I2CB, the SEL0/SCL and SEL1/SDA pins will be configured as hardware select inputs,
SEL0 and SEL1. Connecting SEL0 and SEL1 to VDDD and/or GND selects one of 4 configuration register sets, CFG0 through CFG3,
which is then loaded into the non-volatile configuration registers to configure the clock synthesizer.
If a weak pull-down is placed on OUT0_SEL_I2CB (or if it is left floating to use internal pull-down), the pins SEL0 and SEL1 will be
configured as a I2C interface's SDA and SCL slave bus. Configuration register set CFG0 is always loaded into the non-volatile
configuration registers to configure the clock synthesizer. The host system can use the I2C bus to update the non-volatile configuration
registers to change the configuration, and to read status registers.
I2C Interface and Register Access
When powered up in I2C mode (Table 2), the device allows access to internal RAM registers (Table 4). The OTP registers (Table 3) are
programmed by loading the desired values into the RAM registers that shadow the target OTP registers (Table 4), and initiating the
internal programming sequence for the desired register range.
Users should not write to the Trim RAM in address range 0x01–0x0F, or the Test RAM in address range 0x6A–0x6F, and should only write
to the OTP Control in address range 0x70–0x7F when programming the OTP.
The RAM in address range 0x80–0x8F is not used by the device and may be used for any purpose.
Table 2. Power-Up Setting of Hardware Select Pin vs I2C Mode, and Default OTP Configuration Register
OUT0_SEL_I2CB Strap at
Power-Up SEL1/SDA pin SEL0/SCL pin Function
10kΩpull-up
0 0 OTP bank CFG0 used to initialize RAM configuration registers.
0 1 OTP bank CFG1 used to initialize RAM configuration registers.
1 0 OTP bank CFG2 used to initialize RAM configuration registers.
1 1 OTP bank CFG3 used to initialize RAM configuration registers.
10kΩpull-down or floating SDA SCL I2C bus enabled to access registers.
OTP bank CFG0 used to initialize RAM configuration registers.
Table 3. OTP Register Map Summary
Register Range OTP Register Block Name Register Block Description
0x000 OTP Control OTP burned status & I²C address setting.
0x001–0x00F Trim Presets Program default settings. See page 6.
0x010–0x069 CFG0 User configuration settings bank 0.
0x06A–0x0C3 CFG1 User configuration settings bank 1.
0x0C4–0x11D CFG2 User configuration settings bank 2.
0x11E–0x177 CFG3 User configuration settings bank 3.
0x178–0x1AF Factory Use Factory settings–do not over-program.

4©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock®6E Family Register Descriptions and Programming Guide
VersaClock 6E Family Power-Up Behavior
On power-up, the following RAM register loading sequence occurs:
1. The RAM registers always initialize to a hard-wired set of default values, which are also the 'Default register values' for OTP shown in
subsequent tables.
2. If OTP_ burned bit D7 = 0 in the OTP Control register (Table 7), this indicates that the both the Trim OTP tables and at least one of
the four OTP user configuration tables have been programmed.
• Factory programmed product is typically shipped in this condition. Device has factory trim performed and with required
customization written into OTP memory. IDT programs user customization at factory test. Please visit our website for device
customization request.
• Trim RAM data will be updated from the Trim OTP registers into the appropriate trim RAM registers, overwriting the initial default
values.
• Configuration data will be read from the one of the four OTP user configuration tables into the appropriate configuration RAM
registers, overwriting the initial default values. When powered up in I2C mode, the first configuration table, CFG0, is loaded. When
powered up in selection-pin mode, the SEL0 and SEL1 input pins are decoded to select one of the four configuration tables (Table
23).
• Initialization is now complete, and the part will operate per the configuration settings.
3. If OTP_ burned bit D7 = 1 in the OTP Control register (Table 7), this indicates that the four OTP user configuration tables are
unconfigured.
• Un-programmed product is shipped in this condition and ready for user self-program and customization.
• Configuration RAM data remains at the hard-wired set of default values.
• Initialization is now complete, and the part will operate per the default configuration settings.
• When powered up in I2C mode, the Configuration RAM registers can be written with the user's desired settings by the host system,
and the clock generator operated without ever programming any of the four OTP user configuration tables. Alternatively, the host
system (or a programming system) can program one of more of the four OTP user configuration tables, and also clear the OTP_
burned bit D7 in the OTP Control register (Table 7) to 0. The VersaClock 6E device will follow the behavior according to section 0
above for subsequent power ups.
Table 4. RAM Register Map Summary
Register Range RAM Register Block Corresponding OTP Register
Block Name Corresponding OTP Register Block Address Range
0x00 OTP Control OTP Control 0x000
0x01–0x0F Trim Trim 0x000–0x00F
0x10–0x1F Configuration–Main
CFG0
CFG1
CFG2
CFG3
0x010–0x069
0x06A–0x0C3
0x0C4–0x11D
0x11E–0x177
0x20–0x2F Configuration–CLK1
0x30–0x3F Configuration–CLK2
0x40–0x4F Configuration–CLK3
0x50–0x5F Configuration–CLK4
0x60–0x69 Configuration–Outputs
0x6A–0x6F Factory Use — —
0x70–0x7F OTP Control — —
0x80–0x8F Unused RAM — —
0x90–0x9F Factory Use — —

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VersaClock®6E Family Register Descriptions and Programming Guide
OTP Programming
The steps for OTP programming are given in Table 5. The procedure is to write the desired default data to the appropriate RAM registers,
and then to instruct the part to burn a desired register address range into OTP.
The RAM registers have an 8-bit register address (0x00 to 0x9F), while the user OTP registers have a 9-bit address (0x000 to 0x177).
This is because there are 4 banks of configuration data in OTP. The OTP addressing therefore extends across two RAM registers (Table
5). The 9-bit user start address is set by register 0x73[7:0] + 0x74[7]. The 9-bit user end address is set by register 0x75[7:0] + 0x76[7].
Table 5. OTP Programming Procedure
Step Procedure Notes
0Connect all VDD pins to a single 3.3V, with OUT0_SEL_I2CB pin
left floating. Power on the part in I²C mode.
1 Wait 100ms. Part power-up initialization.
2Write device RAM configuration registers 0x10 to 0x69 to the
desired state.
These RAM values will be programmed into OTP as new
default register values.
3 Write registers 0x73 to 0x78 following the procedure in Table 5. Set burn register source address range and destination register
bank CFG0, 1, 2, or 3.
4 Write register 0x72 = 0xF0. Reset burn bit.
5 Write register 0x72 = 0xF8. Burn the OTP range defined above.
6 Wait 500ms. Wait for burn to complete. Device stops acknowledging while
burning.
7 Write register 0x72 = 0xF0. Reset burn bit.
8 Write register 0x72 = 0xF8. Repeat the burn.
9 Wait 500ms. Wait for burn to complete. Device stops acknowledging while
burning.
10 Write register 0x72 = 0xF0. Reset burn bit.
11 Done programming. Programming complete.
12 Write register 0x72 = 0xF2. Perform margin read.
13 Write register 0x72 = 0xF0. Reset margin read bit.
14
Read register 0x9F:
If bit D1 = 0, programming was successful.
If bit D1 = 1, programming failed.
Test if OTP programming was successful.
15 Write register 0x9F = 0x00. Reset margin read status bit.
16 One configuration register bank (CFG0, 1, 2, or 3) is now burned.
To burn another bank, repeat the procedure from Step 2. Burn further configuration register banks if desired.
17
When all desired configuration register bank have been burned,
write device OTP Control register 0x00 with OTP_burned bit D7
clear.
Burn OTP Control register clearing OTP_burned bit D7. This
sets the part to load configuration data from OTP on power-up.
18 Exit. Done.

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VersaClock®6E Family Register Descriptions and Programming Guide
* Configuration CFG0 includes the Trim presets in 0x01 to 0x0F.
Use the steps in the following example as guidelines to program configuration 0 OTP registers:
1. Write the value from register address 0x00 to 0x69 (first bank) to RAM registers.
Starting at Address 0x00, write data: 61 F3 00 00 00 00 00 00 00 FF FD C0 00 B6 B4 92 A8 CC 81 80 00 03 8C 03 20 00 00 00 9F FF F0
80 00 81 00 00 00 00 00 00 00 00 04 00 01 01 90 00 00 8F 00 00 00 00 00 00 00 00 04 00 00 9C 40 00 00 81 02 00 00 00 00 00 00 00 04
00 00 00 C0 00 00 81 00 00 00 00 00 00 00 00 04 00 00 00 A0 00 3B 01 3B 00 BB 01 7B 01 FF FC
In above example, 61 is the value in register 0x00 that correspond to I2C address D4 and the trim presets are recommended defaults:
0x01–0x0F = “F3 00 00 00 00 00 00 00 FF FD C0 00 B6 B4 92".
In above example, a 25MHz crystal is expected, OUT0 is enabled, OUT1 is 50MHz LVCMOS, OUT2 is 10KHz LVCMOS, OUT3 is 100MHz
LVCMOSD and OUT4 is 125MHz LVDS. In case of 5P49V6967 and 5P49V6968, the OUT3 setting will determine the frequency of the
LP-HCSL outputs.
2. Write the following values to program the OTP with config0 and trim bits (Table 6):
• Reg Address (hex): 73 74 75 76 77 78
• Configuration 0: 00 4E 34 E1 00 00
3. Start Burn with Reg 0x72 set to F8.
4. Wait 500ms.
5. Reset Burn Start Bit 0x72 set to F0.
In-System VersaClock 6E OTP Non-Volatile Programming via I2C
For in-system programming of OTP, it is required to power the VDDA and VDDD pins from 3.3V. Other VDD pins can be powered from
1.8V, 2.5V or 3.3V, whatever is needed for the application.
Burning OTP requires a high internal voltage. The circuit responsible for generating the high internal voltage needs at least 3.3V to
generate a high enough internal voltage for reliable OTP burning with good data retention.
Default Register Values
The following tables have a column “Default Value”. These are values as they show in a 5P49V69xxA000, so called “blank” device that is
meant for field programming. When the device is still un-programmed, it runs a default mode with OUT0 enabled and OUT1 = 100MHz,
assuming a 25MHz crystal is connected. The default values are the register settings for this default mode.
Table 6. OTP Addressing For Programming
Register
User Start
Address[8:0]
Part-Select
Bit 0x73
Enable
Sub-block's
Test Mode
0x74
User End
Address[8:0]
Part-SelectBit
0x75
User End
Address[8:0]
Part-Select
Bits 0x76
BurnedRegister
Start Address
0x77
Read Register
Start Address
0x78
Registers
Burned To
OTP
OTP Control register 0x00 0x4E 0x00 0x61 0x00 0x00 0x00
Configuration CFG0* 0x00 0x4E 0x34 0xE1 0x00 0x00 0x00 to 0x69
Configuration CFG1 0x35 0x4E 0x61 0xE1 0x10 0x10 0x10 to 0x69
Configuration CFG2 0x62 0x4E 0x8E 0xE1 0x10 0x10 0x10 to 0x69
Configuration CFG3 0x8F 0x4E 0xBB 0xE1 0x10 0x10 0x10 to 0x69

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VersaClock®6E Family Register Descriptions and Programming Guide
OTP Control Register
The I2C slave address can be changed from the default 0xD4 to 0xD0 by programming the I2C_ADDR bit D0. Note that the I2C address
change occurs on the I2C ACK of the write transaction. An I2C write sequence to register 0x00 that changes the value of I2C_ADDR bit
D0 should be followed by an I2C STOP condition. Further I2C transactions to the part use the new address.
In the OTP Control Register (Table 7) bits can be set for the OTP Burn and OTP Trim status, VC6E or MEMS use and I2C address setting.
Four bits are left unused.
* The trim values are commonly written with default values and the OTP_TRIM bit is left at “1”.
Factory Reserved Registers for Internal Use Only
* Configuration Lock bits can be used to prevent future OTP burning that can modify OTP content.
Table 7. RAM0 0x00 – OTP Control Register
Bits Default Value Name Function
D7 1 OTP_burned
It's an active low state that indicates all the OTP burn process is done.
D7 = 1 tells the chip that OTP is not burned and it will run the default mode.
D7 = 0 tells the chip that OTP is burned and it will transfer OTP content to the registers for
operating settings.
D6 1 OTP_TRIM An active low state that indicates OTP trim part is burned.*
D5 1 Unused Unused.
D4 1 Unused Unused.
D3 1 Unused Unused.
D2 1 Unused Unused.
D1 1 Unused Unused.
D0 1 Device I2C_ADDR If I2C_ADDR = 0 then D0 and if I2C_ADDR = 1 then D4.
Table 8. RAM0 – 0x01: Factory Reserved Bits - Device ID for Chip Identification
Bits Default Value Name Function
D7 1 CFG0_LOCK* Set to “0” to disable burning OTP of Configuration 0.
D6 1 CFG1_LOCK* Set to “0” to disable burning OTP of Configuration 1.
D5 1 CFG2_LOCK* Set to “0” to disable burning OTP of Configuration 2.
D4 1 CFG3_LOCK* Set to “0” to disable burning OTP of Configuration 3.
D3 1 Unused Unused.
D2 1 Unused Unused.
D1 1 Reserved Factory reserved, leave at “1”.
D0 1 Reserved Factory reserved, leave at “1”.

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VersaClock®6E Family Register Descriptions and Programming Guide
Table 9. RAM0 – 0x02: Factory Reserved Bits - ADC Gain Setting
Bits Default Value Name Function
D7 0
ADC gain[7:0] ADC gain setting - Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 10. RAM0 – 0x03: Factory Reserved Bits - ADC Gain Setting
Bits Default Value Name Function
D7 0
ADC gain[15:8] ADC gain setting - Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 11. RAM0 – 0x04: Factory Reserved Bits - ADC OFFSET
Bits Default Value Name Function
D7 0
ADC offset[7:0] ADC offset - Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0

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VersaClock®6E Family Register Descriptions and Programming Guide
Table 12. RAM0 – 0x05: Factory reserved bits - ADC OFFSET
Bits Default Value Name Function
D7 0
ADC offset[15:8] ADC offset - Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 13. RAM0 – 0x06: Factory Reserved Bits
Bits Default Value Name Function
D7 0
TEMPY[7:0] Factory reserved bits
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 14. RAM0 – 0x07: Factory Reserved Bits
Bits Default Value Name Function
D7 1
OFFSET_TBIN<7:0> Unused Factory reserved bits
D6 1
D5 1
D4 1
D3 1
D2 1
D1 1
D0 1

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VersaClock®6E Family Register Descriptions and Programming Guide
Table 15. RAM0 – 0x08: Factory Reserved Bits
Bits Default Value Name Function
D7 1
GAIN<7:0> Unused Factory reserved bits
D6 1
D5 1
D4 1
D3 1
D2 1
D1 1
D0 1
Table 16. RAM0 – 0x09: Factory Reserved Bits
Bits Default Value Name Function
D7 1
test[3:0] Factory reserved bits
D6 1
D5 1
D4 1
D3 1
NP[3:0] Factory reserved bits
D2 1
D1 1
D0 1
Table 17. RAM0 – 0x0A: Factory Reserved Bits
Bits Default Value Name Function
D7 1 Reserved
Factory reserved bits
D6 1 Reserved
D5 1 Reserved
D4 1 Reserved
D3 1 Reserved
D2 1 Reserved
D1 0 Reserved
D0 1 Reserved

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VersaClock®6E Family Register Descriptions and Programming Guide
Table 18. RAM0 – 0x0B: Factory Reserved Bits
Bits Default Value Name Function
D7 0
bandgap_trim_up
[5:0]
bandgap voltage trim, one step is 1.2mV higher than current.
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0 unused bit
D0 0 unused bit
Table 19. RAM0 – 0x0C: Factory Reserved Bits
Bits Default Value Name Function
D7 0
bandgap_trim_dn
[5:0]
bandgap voltage trim, one step is 1.2mV lower than current.
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0 unused bit
D0 0 unused bit
Table 20. RAM0 – 0x0D: Factory Reserved Bits
Bits Default Value Name Function
D7 1
clk1_R_trim[2:0] clk_R_trim: trim for “R” variation, 1LSB is 10%, default is in the middle level.D6 0
D5 1
D4 1
clk2_R_trim[2:0] clk_R_trim: trim for “R” variation, 1LSB is 10%, default is in the middle level.D3 0
D2 1
D1 1 CLK4_amp[2] clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level.
D0 0 CLK4_amp[1] clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level.

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VersaClock®6E Family Register Descriptions and Programming Guide
Configuration Registers
The internal RAM configuration registers occupy 0x10 to 0x69 (Table 4).
The 4 OTP configuration banks CFG0, CFG1, CFG2, and CFG3 use the same register structure and setting behavior.
The tables with register details refer to the RAM register address for simplicity. Table 23 shows the 3-digit OTP register addresses 0x010
to 0x177 for the four banks of identical configuration registers, and the corresponding RAM register address.
Table 21. RAM0 – 0x0E: Factory Reserved Bits
Bits Default Value Name Function
D7 1
clk3_R_trim[2:0] clk_R_trim: trim for “R” variation, 1LSB is 10%, default is in the middle level.D6 0
D5 1
D4 1
clk4_R_trim[2:0] clk_R_trim: trim for “R” variation, 1LSB is 10%, default is in the middle level.D3 0
D2 1
D1 0 CLK4_amp[0] clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level.
D0 0 CLK3_amp[0] clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level.
Table 22. RAM0 – 0x0F: Factory Reserved Bits
Bits Default Value Name Function
D7 1 CLK1_amp[2]
clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level–Factory
reserved bits.
D6 0 CLK1_amp[1]
D5 0 CLK1_amp[0]
D4 1 CLK2_amp[2]
D3 0 CLK2_amp[1]
D2 0 CLK2_amp[0]
D1 1 CLK3_amp[2]
D0 0 CLK3_amp[1]
Table 23. RAM Configuration Registers and OTP Configuration Registers CFG0, CFG1, CFG2, CFG3
Summary
Register Address Function
RAM CFG0 CFG1 CFG2 CFG3
0x10 0x010 0x06A 0x0C4 0x11E Primary Source and Shutdown Register
0x11 0x011 0x06B 0x0C5 0x11F VCO Band and Factory Reserved Bits
0x12 0x012 0x06C 0x0C6 0x120 Crystal X1 Load Capacitor Register
0x13 0x013 0x06D 0x0C7 0x121 Crystal X2 Load Capacitor Register

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VersaClock®6E Family Register Descriptions and Programming Guide
0x14 0x014 0x06E 0x0C8 0x122 Factory Reserved Register
0x15 0x015 0x06F 0x0C9 0x123 Reference Divider Register
0x16 0x016 0x070 0x0CA 0x124 VCO Control Register and Pre-Divider
0x17 0x017 0x071 0x0CB 0x125 Feedback Integer Divider Register
0x18 0x018 0x072 0x0CC 0x126 Feedback Integer Divider Bits
0x19 0x019 0x073 0x0CD 0x127 Feedback Fractional Divider Register
0x1A 0x01A 0x074 0x0CE 0x128 Feedback Fractional Divider Register
0x1B 0x01B 0x075 0x0CF 0x129 Feedback Fractional Divider Register
0x1C 0x01C 0x076 0x0D0 0x12A Factory Reserved Register
0x1D 0x01D 0x077 0x0D1 0x12B Factory Reserved Register
0x1E 0x01E 0x078 0x0D2 0x12C RC Control Register
0x1F 0x01F 0x079 0x0D3 0x12D RC Control Register
0x20 0x020 0x07A 0x0D4 0x12E Unused Factory Reserved Register
0x21 0x021 0x07B 0x0D5 0x12F Output Divider 1 Control Register Settings
0x22 0x022 0x07C 0x0D6 0x130 Output Divider 1 Fractional Settings
0x23 0x023 0x07D 0x0D7 0x131 Output Divider 1 Fractional Settings
0x24 0x024 0x07E 0x0D8 0x132 Output Divider 1 Fractional Settings
0x25 0x025 0x07F 0x0D9 0x133 Output Divider1 Fractional Settings
0x26 0x026 0x080 0x0DA 0x134 Output Divider 1 Step Spread Configuration Register
0x27 0x027 0x081 0x0DB 0x135 Output Divider 1 Step Spread Configuration Register
0x28 0x028 0x082 0x0DC 0x136 Output Divider 1 Step Spread Configuration Register
0x29 0x029 0x083 0x0DD 0x137 Output Divider 1 Spread Modulation Rate Configuration Register
0x2A 0x02A 0x084 0x0DE 0x138 Output Divider 1 Spread Modulation Rate Configuration Register
0x2B 0x02B 0x085 0x0DF 0x139 Output Divider 1 Skew Integer Part
0x2C 0x02C 0x086 0x0E0 0x13A Output Divider 1 Skew Integer Part
0x2D 0x02D 0x087 0x0E1 0x13B Output Divider 1 Integer Part
0x2E 0x02E 0x088 0x0E2 0x13C Output Divider 1 Integer Part
0x2F 0x02F 0x089 0x0E3 0x13D Output Divider 1 Skew Fractional part
0x30 0x030 0x08A 0x0E4 0x13E Unused Factory Reserved Register
0x31 0x031 0x08B 0x0E5 0x13F Output Divider 2 Control Register Settings
0x32 0x032 0x08C 0x0E6 0x140 Output Divider 2 Fractional Settings
0x33 0x033 0x08D 0x0E7 0x141 Output Divider 2 Fractional Settings
0x34 0x034 0x08E 0x0E8 0x142 Output Divider 2 Fractional Settings
0x35 0x035 0x08F 0x0E9 0x143 Output Divider2 Fractional Settings
Table 23. RAM Configuration Registers and OTP Configuration Registers CFG0, CFG1, CFG2, CFG3
Summary (Cont.)
Register Address Function
RAM CFG0 CFG1 CFG2 CFG3

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VersaClock®6E Family Register Descriptions and Programming Guide
0x36 0x036 0x090 0x0EA 0x144 Output Divider 2 Step Spread Configuration Register
0x37 0x037 0x091 0x0EB 0x145 Output Divider 2 Step Spread Configuration Register
0x38 0x038 0x092 0x0EC 0x146 Output Divider 2 Step Spread Configuration Register
0x39 0x039 0x093 0x0ED 0x147 Output Divider 2 Spread Modulation Rate Configuration Register
0x3A 0x03A 0x094 0x0EE 0x148 Output Divider 2 Spread Modulation Rate Configuration Register
0x3B 0x03B 0x095 0x0EF 0x149 Output Divider 2 Skew Integer Part
0x3C 0x03C 0x096 0x0F0 0x14A Output Divider 2 Skew Integer Part
0x3D 0x03D 0x097 0x0F1 0x14B Output Divider 2 Integer Part
0x3E 0x03E 0x098 0x0F2 0x14C Output Divider 2 Integer Part
0x3F 0x03F 0x099 0x0F3 0x14D Output Divider 2 Skew Fractional part
0x40 0x040 0x09A 0x0F4 0x14E Unused Factory Reserved Register
0x41 0x041 0x09B 0x0F5 0x14F Output Divider 3 Control Register Settings
0x42 0x042 0x09C 0x0F6 0x150 Output Divider 3 Fractional Settings
0x43 0x043 0x09D 0x0F7 0x151 Output Divider 3 Fractional Settings
0x44 0x044 0x09E 0x0F8 0x152 Output Divider 3 Fractional Settings
0x45 0x045 0x09F 0x0F9 0x153 Output Divider 3 Fractional Settings
0x46 0x046 0x0A0 0x0FA 0x154 Output Divider 3 Step Spread Configuration Register
0x47 0x047 0x0A1 0x0FB 0x155 Output Divider 3 Step Spread Configuration Register
0x48 0x048 0x0A2 0x0FC 0x156 Output Divider 3 Step Spread Configuration Register
0x49 0x049 0x0A3 0x0FD 0x157 Output Divider 3 Spread Modulation Rate Configuration Register
0x4A 0x04A 0x0A4 0x0FE 0x158 Output Divider 3 Spread Modulation Rate Configuration Register
0x4B 0x04B 0x0A5 0x0FF 0x159 Output Divider 3 Skew Integer Part
0x4C 0x04C 0x0A6 0x100 0x15A Output Divider 3 Skew Integer Part
0x4D 0x04D 0x0A7 0x101 0x15B Output Divider 3 Integer Part
0x4E 0x04E 0x0A8 0x102 0x15C Output Divider 3 Integer Part
0x4F 0x04F 0x0A9 0x103 0x15D Output Divider 3 Skew Fractional part
0x50 0x050 0x0AA 0x104 0x15E Unused Factory Reserved Register
0x51 0x051 0x0AB 0x105 0x15F Output Divider 4 Control Register Settings
0x52 0x052 0x0AC 0x106 0x160 Output Divider 4 Fractional Settings
0x53 0x053 0x0AD 0x107 0x161 Output Divider 4 Fractional Settings
0x54 0x054 0x0AE 0x108 0x162 Output Divider 4 Fractional Settings
0x55 0x055 0x0AF 0x109 0x163 Output Divider 4 Fractional Settings
0x56 0x056 0x0B0 0x10A 0x164 Output Divider 4 Step Spread Configuration Register
0x57 0x057 0x0B1 0x10B 0x165 Output Divider 4 Step Spread Configuration Register
Table 23. RAM Configuration Registers and OTP Configuration Registers CFG0, CFG1, CFG2, CFG3
Summary (Cont.)
Register Address Function
RAM CFG0 CFG1 CFG2 CFG3

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VersaClock®6E Family Register Descriptions and Programming Guide
Configuration Register Detail and Functionality Description
Shutdown Function
The shutdown logic offers flexible configuration of shutdown signaling and clock output enable control. The shutdown logic is summarized
in Table 24.
When SP bit D1 = 0 in the Shutdown register 0x00 (Table 25), the SD/OE input is active low. When SP bit D1 = 1, SD/OE is active high.
SH bit D0 in the Shutdown register 0x10 (Table 25) configures the SD/OE input's action as either output enable (OE) for the clock outputs
(leaving the PLL running), or full part shutdown. SH bit D1 = 0 for OE function, or 1 for shutdown function.
In shutdown, the part is shut down, differential outputs are driven High/low, and the single-ended LVCMOS outputs are driven low. In
output-disable, individual outputs can be selected to be either Hi-Z or driven high/low, depending on the configuration of the CLKx_OS
and CLKx_OE bits shown in Table 24.
0x58 0x058 0x0B2 0x10C 0x166 Output Divider 4 Step Spread Configuration Register
0x59 0x059 0x0B3 0x10D 0x167 Output Divider 4 Spread Modulation Rate Configuration Register
0x5A 0x05A 0x0B4 0x10E 0x168 Output Divider 4 Spread Modulation Rate Configuration Register
0x5B 0x05B 0x0B5 0x10F 0x169 Output Divider 4 Skew Integer Part
0x5C 0x05C 0x0B6 0x110 0x16A Output Divider 4 Skew Integer Part
0x5D 0x05D 0x0B7 0x111 0x16B Output Divider 4 Integer Part
0x5E 0x05E 0x0B8 0x112 0x16C Output Divider 4 Integer Part
0x5F 0x05F 0x0B9 0x113 0x16D Output Divider 4 Skew Fractional Part
0x60 0x060 0x0BA 0x114 0x16E Clock 1 Output Configuration
0x61 0x061 0x0BB 0x115 0x16F Clock 2 Output Configuration
0x62 0x062 0x0BC 0x116 0x170 Clock 1 Output Configuration
0x63 0x063 0x0BD 0x117 0x171 Clock 2 Output Configuration
0x64 0x064 0x0BE 0x118 0x172 Clock 1 Output Configuration
0x65 0x065 0x0BF 0x119 0x173 Clock 2 Output Configuration
0x66 0x066 0x0C0 0x11A 0x174 Clock 1 Output Configuration
0x67 0x067 0x0C1 0x11B 0x175 Clock 2 Output Configuration
0x68 0x068 0x0C2 0x11C 0x176 CLK_OE/Shutdown Function
0x69 0x069 0x0C3 0x11D 0x177 CLK_OS/Shutdown Function
Table 23. RAM Configuration Registers and OTP Configuration Registers CFG0, CFG1, CFG2, CFG3
Summary (Cont.)
Register Address Function
RAM CFG0 CFG1 CFG2 CFG3

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VersaClock®6E Family Register Descriptions and Programming Guide
SH bit = “Shutdown Bit”: Enable shutdown mode where the SD/OE pin can disable more than just outputs.
SP bit = “SD/OE pin Polarity Bit”: Set the polarity of the SD/OE pin where outputs enable or disable. Only works with OE, not with SD.
OSn bit = “Output Suspend Bit”: Permanently disable an output, independent of SD/OE pin.
OEn bit = “Output Enable Bit”: Permanently enable an output, independent of SD/OE pin. Only works with OE, not with SD.
SDOE bit = “Output Disabled State”: Set the output state to either driven High/Low or Hi-Z when disabled with the SD/OE pin.
SD/OE pin = Physical pin on the device.
SH and SP bits exist only once and affect all outputs. Other bits exist per output and affect that specific output.
Setting Up a Low-Power Shutdown Mode through I2C
1. Tristate the outputs by writing b'001ss000' to registers 0x60, 0x62, 0x64, and 0x66 where ss = 00, 10, or 11 for output clock supply
voltages 1.8V, 2.5V, or 3.3V.
2. Program all outputs to single-ended CMOS by writing 0x00 to registers 0x68.
3. Enable shutdown functionality by either writing 0x83 or 0x43 to register 0x10, for crystal clock source or external clock respectively.
4. Disable all output dividers by writing 0x80 to registers 0x21, 0x31, 0x41, and 0x51.
5. Take the SD/OE input pin 7 high.
Table 24. Shutdown Truth Table
SH bit SP bit OSn bit OEn bit SD/OE bit SD/OE pin OUTn
0 x 1 0 x x Output Active
x011x 0OutputActive
0111x 1OutputActive
1 x 1 0 x 0 Output Active
00110 1OutputDrivenLogic“1”(High/Low)
x 1 1 1 0 0 Output Driven Logic “1” (High/Low)
1 x x x 0 1 Global Shutdown, Output Driven Logic “1” (High/Low)
x x 0 x x x Output Tri-stated (Hi-Z)
00111 1OutputTri-stated(Hi-Z)
x 1 1 1 1 0 Output Tri-stated (Hi-Z)
Table 25. RAM1 – 0x10: Primary Source and Shutdown Register
Bits Default Value Name Function
D7 1 en_xtal Crystal Oscillator circuit is disabled with 0 and enabled with 1.
D6 0 en_clkin CLKIN differential input circuit is disabled with 0 and enabled with 1.
D5 1 unused Unused Factory reserved bit.
D4 0 unused Unused Factory reserved bit.
D3 0 en_ref_doubler
Use “en_ref_doubler” is 1 to double the reference frequency for the Phase Frequency
Detector.
Use “en_ref_doubler” is 0 to bypass the doubler.

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VersaClock®6E Family Register Descriptions and Programming Guide
NOTE: Bit D6 is not used for 5P49V6967 and 5P49V6968 as these products have only a crystal input
D2 0 en_refmode Enable path from reference clock to OUT1. Set to 1 when OUT1 is a copy of the
reference clock (= OUT0). Set to 0 when using FOD1 for OUT1.
D1 0 SP
SD/OE input pin is active low if this bit is 0 and active high if this bit is 1. (If D0 = 0 then
D1 reverses SD/OE pin polarity, affecting OE bits in output polarity. If D0 = 1, SD/OE
pin = 1 causes global shutdown).
D0 0 en_global
shutdown
D1 reverses SD/OE pin polarity, affecting OE bits in output buffers and SD/OE input pin
is shutdown (SD) if this bit is 1.
Table 26. RAM6 – 0x68: CLK_OE/Shutdown Function
Bits Default Value Name Function
D7 1 CLK0_OE See Table 24 – This is bit OEn for output 0.
D6 1 CLK1_OE See Table 24 – This is bit OEn for output 1.
D5 1 CLK2_OE See Table 24 – This is bit OEn for output 2.
D4 1 CLK3_OE See Table 24 – This is bit OEn for output 3.
D3 1 CLK4_OE See Table 24 – This is bit OEn for output 4.
D2 1 clk0_slewrate[1]
CLK0 slew rate setting bit[1]
11 = Fastest
00 = Slowest (20% slower than 11)
D1 1
clk0_pwr_sel[1:0]
Clock output driver power supply voltage is indicated by these bits.
D1 D0 = 0x indicates 1.8V
D1 D0 = 10 indicates 2.5V
D1 D0 = 11 indicates 3.3V
D0 1
Table 27. RAM6 – 0x69: CLK_OS/Shutdown Function
Bits Default Value Name Function
D7 1 CLK0_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D6 1 CLK1_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D5 1 CLK2_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D4 1 CLK3_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D3 1 CLK4_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D2 1 clk0_slewrate[0] Depends on slew rate (depends on Shutdown function/truth table) – Set slew rate for
clk0.
D1 0
otp_pwr_sel[1:0]
Set Output Amplitude for OTP voltage:
Factory reserved
Use D1 D0 = 00.
D0 0
Table 25. RAM1 – 0x10: Primary Source and Shutdown Register (Cont.)
Bits Default Value Name Function

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VersaClock®6E Family Register Descriptions and Programming Guide
Crystal Load Capacitor Registers
Registers 0x12 and 0x13 are Crystal X1 and X2 Load capacitor registers respectively that are used to add load capacitance to X1 and X2
respectively. In X1 Switch mode is provided with different mode selection options and in X2 polarity selection of clock can be made whose
values are given in the table.
Figure 2. Crystal Oscillator
Short Example of Programming Crystal
Ci1 and Ci2 are on-chip capacitors that are programmable.
Cs is stray capacitance in the PCB and Ce is external capacitors for frequency fine tuning or for achieving load capacitance values
beyond the range of the on-chip programmability.
All these capacitors combined make the load capacitance for the crystal.
Capacitance on pin X1: Cx1 = Ci1 + Cs1 + Ce1.
Capacitance on pin X2: Cx2 = Ci2 + Cs2 + Ce2.
Total Crystal Load Capacitance CL= Cx1 × Cx2 / (Cx1 + Cx2).
Example: For a Xtal CLof 8pF, the registers need to be programmed with X1 = X2 = 6.92 pF to get a total
CL= (6.92pF+ 7.5pF + 1.5pF)/2 = 7.9pF which is the closest value to 8pF.
Here, Cstray = 1.5pF; Package stray = 7.5pF
The binary settings corresponding to this value will be: X1 = X2 = “10000”.
Table 28. RAM1 – 0x12: Crystal X1 Load Capacitor Register
Bits Default Value Name Function
D7 0
xtal_load_cap_x1[5:0]
Add 6.92pF load capacitance to X1.
D6 0 Add 3.46pF load capacitance to X1.
D5 0 Add 1.73pF load capacitance to X1.
D4 0 Add 0.86pF load capacitance to X1.
D3 0 Add 0.43pF load capacitance to X1.
D2 0 Add 0.43pF load capacitance to X1.
D1 0
SM1:0]
Switch Mode
Factory reserved.
Use D1 D0 = 00.
D0 1
R
F
GM
R
S
X
2
X1
Xtal Oscillator
Cs1
C i1
Cs
2
C i
2
Ce
1
Ce
2

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VersaClock®6E Family Register Descriptions and Programming Guide
Note: The 5P49V6975 use a pre-trimmed integrated crystal. Therefore, bits D7–D2 in registers 0x12 and 0x13 should be set to 1 to
prevent inaccuracy of the output frequencies.
PLL Pre-Divider Options
The reference presented to the fractional PLL can be either directly connected, divided by two or divided by the any value from the range
of three to 127 as set in the register Ref_Div[6:0]. The phase detector of the PLL has a maximum frequency of 150MHz, therefore the
default is to bypass the pre-divider by setting Bypss_prediv = 1 (Table 32). For the functionality of Sel_prediv2 and bypss_prediv bits, see
Figure 3. Table 31 and Table 32 explains the bit selections.
Table 29. RAM1 – 0x13: Factory Reserved Bits
Bits Default Value Name Function
D7 0
xtal_load_cap_x2[5:0]
Add 6.92pF load capacitance to X2.
D6 0 Add 3.46pF load capacitance to X2.
D5 0 Add 1.73pF load capacitance to X2.
D4 0 Add 0.86pF load capacitance to X2.
D3 0 Add 0.43pF load capacitance to X2.
D2 0 Add 0.43pF load capacitance to X2.
D1 0 PRIMSRC
The PRIMSRC (primary source) bit sets the polarity of the CLKSEL pin.
D1=0: When CLKSEL is Low, Crystal is selected. When CLKSEL is High, CLKIN input is
selected.
D1=1: When CLKSEL is Low, CLKIN input is selected. When CLKSEL is High, Crystal is
selected.
D0 0 clkok1024 Factory reserved.
Table 30. RAM1 – 0x14: Factory Reserved Bits
Bits Default Value Name Function
D7 0
xtal_reg_amp_sel[3:0] Unused Factory reserved bit.
D6 0
D5 0
D4 0
D3 0
xtal_I_sel[3:0] Unused Factory reserved bit.
D2 0
D1 0
D0 0

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VersaClock®6E Family Register Descriptions and Programming Guide
Figure 3. PLL Pre-Divider Options
If pre-divider is selected by selecting bypass_ prediv = 0 (Table 31) then user can select divider by 2 or divider values from 3 to 127.
Table 31. RAM1 – 0x15: Reference Divider Register
Bits Default Value Name Function
D7 0 Sel_prediv2 Select the divider by 2 function; Divide by 2 if set to 1. And if bypass is set to 0. If divide bit
set 0 and bypass bit set to 0 then reference divider bits (D6 to D0) will take effect.
D6 0
Ref_div[6:0]
Reference Divider value.
Use Ref_div setting for values 3 to 127.
Use bit D7 for divide by 2.
Use “Bypass_prediv” bit in Table 32 for divide by 1.
When “Bypass_prediv” is 1, register 0x15 setting is don't care.
When “Sel_prediv2” is 1, Ref_div[6:0] setting is don't care.
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 32. RAM1 – 0x16: VCO Control Register and Pre-Divider
Bits Default Value Name Function
D7 1 Bypass_prediv
Use D7 = 1 when phase frequency detector needs to be equal to the reference clock.
Use D7 = 0 when the reference clock needs to be divided by at least 2 for the phase
frequency detector. See Table 31 settings.
D6 0 dither_gain_cfg[2] Dither gain settings:
Factory reserved bits.
Use default values.
D5 0 dither_gain_cfg[1]
D4 0 dither_gain_cfg[0]
D3 1 afc_en Open loop vco control is enabled if 1 and disabled if 0–factory reserved bit.
D2 1
cnf_afc[2:0] Open loop vco control voltage bits–factory reserved bits. Use default values.D1 0
D0 0