GOWIN DK_START_GW1NSR-LX2CQN48PC5I4_V 2.1 User manual

DK_START_GW1NSR-LX2CQN48PC5I4_V
2.1
User Guide
DBUG401-1.0E, 08/19/2021

Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor
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assumes no liability and provides no warranty (either expressed or implied) and is not
responsible for any damage incurred to your hardware, software, data, or property resulting
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Terms and Conditions of Sale. All information in this document should be treated as
preliminary. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the current
documentation and errata.

Revision History
Date
Version
Description
08/19/2021
1.0E
Initial version published.

Contents
DBUG401-1.0E
i
Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................1
1.4 Support and Feedback ....................................................................................................... 3
2Development Board Description..................................................................4
2.1 Overview.............................................................................................................................4
2.2 A Development Board Suite................................................................................................ 5
2.3 PCB Components ............................................................................................................... 6
2.4 System Architecture............................................................................................................6
2.5 Features..............................................................................................................................7
2.6 Development Board Specification ......................................................................................8
3Development Board Circuit ........................................................................10
3.1 FPGA Module ...................................................................................................................10
Overview .................................................................................................................................10
I/O BANK Introduction ............................................................................................................10
3.2 Download..........................................................................................................................10
3.2.1 Overview........................................................................................................................10
3.2.2 USB Download Circuit ................................................................................................... 11
3.2.3 Download Flow .............................................................................................................. 11
3.2.4 Pinout............................................................................................................................. 11
3.3 Power Supply.................................................................................................................... 11
3.3.1 Overview........................................................................................................................ 11
3.3.2 Power System Distribution ............................................................................................12

Contents
DBUG401-1.0E
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3.3.1 Pinout.............................................................................................................................13
3.4 Clock, Reset .....................................................................................................................13
3.4.1 Overview........................................................................................................................13
3.4.2 Clock, Reset .................................................................................................................. 13
3.4.3 Pinout.............................................................................................................................13
3.5 LED ...................................................................................................................................14
3.5.1 Overview........................................................................................................................14
3.5.2 LED Circuit.....................................................................................................................14
3.5.3 Pinout.............................................................................................................................14
3.6 Key....................................................................................................................................14
3.6.1 Overview........................................................................................................................14
3.6.2 Key Circuit .....................................................................................................................15
3.6.3 Pinout.............................................................................................................................15
3.7 GPIO .................................................................................................................................15
3.7.1 Overview........................................................................................................................15
3.7.2 GPIO Circuit...................................................................................................................15
3.7.3 Pinout.............................................................................................................................16
3.8 MIPI/LVDS ........................................................................................................................16
3.8.1 Overview........................................................................................................................16
3.8.2 MIPI/LVDS Circuit ..........................................................................................................16
3.8.3 Pinout.............................................................................................................................17
3.9 ADC................................................................................................................................... 18
3.9.1 Overview........................................................................................................................18
3.9.2 ADC Circuit ....................................................................................................................19
3.9.3 Pinout.............................................................................................................................19
4Considerations ............................................................................................20
5Gowin Software ...........................................................................................21
6Quick Start ...................................................................................................22

List of Figures
DBUG401-1.0E
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List of Figures
Figure 2-1 DK_START_GW1NSR-LX2CQN48PC5I4_V2.1 Development Board .............................4
Figure 2-2 A Development Board Suite ............................................................................................. 5
Figure 2-3 PCB Components............................................................................................................. 6
Figure 2-4 System Architecture..........................................................................................................6
Figure 3-1 Connection Diagram for FPGA USB Downloading .......................................................... 11
Figure 3-2 Power System Distribution ............................................................................................... 12
Figure 3-3 Clock, Reset ..................................................................................................................... 13
Figure 3-4 LED Circuit .......................................................................................................................14
Figure 3-5 Key Circuit Diagram.......................................................................................................... 15
Figure 3-6 GPIO Circuit .....................................................................................................................15
Figure 3-7 LVDS Circuit ..................................................................................................................... 16
Figure 3-8 ADC Circuit .......................................................................................................................19

List of Tables
DBUG401-1.0E
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List of Tables
Table 1-1 Abbreviations and Terminology .......................................................................................... 2
Table 2-1 Development Board Specification......................................................................................8
Table 3-1 FPGA Download and Pinout ..............................................................................................11
Table 3-2 FPGA Power Pinout ........................................................................................................... 13
Table 3-3 FPGA Clock and Reset Pinout...........................................................................................13
Table 3-4 LED Pinout ......................................................................................................................... 14
Table 3-5 Key Pinout..........................................................................................................................15
Table 3-6 J14 GPIO Pinout ................................................................................................................16
Table 3-7 J15 FPGA Pinout................................................................................................................ 17
Table 3-8 J16 FPGA Pinout................................................................................................................ 17
Table 3-9 J15 ADC Pinout..................................................................................................................19

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK_START_GW1NSR-LX2CQN48PC5I4_V2.1 user manual
consists of the following four parts:
A brief introduction to the features and hardware resources of the
development board;
An introduction to the hardware circuits functions, circuit, and pins
distribution;
Precautions to be taken when using the development board;
Introduction to the use of the FPGA development software.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS861, GW1NSR series of FPGA Products Data Sheet
2. UG863, GW1NSR series of FPGA Products Package and Pinout
3. UG862, GW1NSR-2&2C Pinout
4. UG290, Gowin FPGA Products Programming and Configuration User
Guide
5. SUG100, Gowin Software User Guide
1.3 Abbreviations and Terminology
The abbreviations and terminology used in this manual are as shown
in Table 1-1 below.

1 About This Guide
1.3 Abbreviations and Terminology
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Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Full Name
FPGA
Field Programmable Gate Array
SoC
System On Chip
ARM
Advanced RISC Machines
AHB
Advanced High performance Bus
APB
Advanced Peripheral Bus
Timer
Timer
RS232
Universal Asynchronous Receiver/Transmitter
NVIC
Nested Vector Interrupt Controller
DAP
Debug Access Port
Watchdog
Watchdog
TimeStamp
TimeStamp
DWT
Data Watchpoint Trace
ITM
Instrumentation Trace Module
TUIP
Trace Port Interface Unit
USB
Universal Serial Bus
PHY
Physical Layer
ADC
Analog to Digital Converter
SAR
Successive Approximation Register
SFDR
Spurious-free Dynamic Range
SINAD
Signal to Noise And Distortion
LSB
Least Significant Bit
INL
Integral Nonlinearity
DNL
Differential Nonlinearity
CFU
Configurable Function Unit
CLS
Configurable Logic Slice
CRU
Configurable Routing Unit
LUT4
4-input Look-up Table
LUT5
5-input Look-up Table
LUT6
6-input Look-up Table
LUT7
7-input Look-up Table
LUT8
8-input Look-up Table
REG
Register
ALU
Arithmetic Logic Unit
IOB
Input / Output Block
SSRAM
Shadow Static Random Access Memory
BSRAM
Block Static Random Access Memory
SP
Single Port

1 About This Guide
1.4 Support and Feedback
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Abbreviations and Terminology
Full Name
SDP
Semi Dual Port
DP
Dual Port
PSRAM
Pseudo static random access memory
DQCE
Dynamic Quadrant Clock Enable
DCS
Dynamic Clock Selector
PLL
Phase-locked Loop
DLL
Delay-locked Loop
LQ144
LQFP144
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Development Board Description
2.1 Overview
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2Development Board Description
2.1 Overview
Figure 2-1 DK_START_GW1NSR-LX2CQN48PC5I4_V2.1 Development Board
The development board adopts the GW1NSR-2 SoC FPGA. SoC
FPGA is embedded with an ARM Cortex-M3 hard core processor, 32Mbit
PSRAM, 1Mbit User Flash and eight-channel ADC converter, etc. When
the ARM Cortex-M3 hard-core processor is employed as the core, the
needs of the Min. memory can be met. FPGA logic resources and other
embedded resources can flexibly facilitate the peripheral control functions,
which provide excellent calculation functions and exceptional system
response interrupts. They also offer high performance, low power
consumption, flexible usage, instant start-up, affordability, nonvolatile, high
security, and abundant package types, among other benefits.
The development board offers abundant external interfaces, including
MIPI/LVDS interfaces, GPIO interfaces, ADC interfaces, slide switches,
LED, clock, reset, etc.

2 Development Board Description
2.2 A Development Board Suite
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2.2 A Development Board Suite
A development board suite includes the following items:
DK_START_GW1NSR-LX2CQN48PC5I4_V2.1 development board
USB cable
Figure 2-2 A Development Board Suite
1
2
①DK_START_GW1NSR-LX2CQN48PC5I4_V2.1
development board
②USB Cable

2 Development Board Description
2.3 PCB Components
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2.3 PCB Components
Figure 2-3 PCB Components
Key
GPIO
1.2V
GPIO
3.3V
OSC
LED Reset
FPGA
Download
5V IN
FPGA
1.8V
LVDS
LVDS
2.5V Select FPGA /ARM
Download
2.4 System Architecture
Figure 2-4 System Architecture
2*LED
(Share I/Os
with
BUTTON)
OSC
50MHz
5Pairs
LVDS/MIPI
INPUT
2*BUTTON
5Pairs
LVDS/MIPI
OUTPUT
20PIN
GPIO
JTAG Interface
ARM
JTAG
FPGA
JTAG
10PIN
GPIO
8* CHADC
INPUT(ShareI/Os
with differential
input)
GW1NSR-
LX2CQN48PC5I4_V2.1

2 Development Board Description
2.5 Features
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2.5 Features
The structure and features of the development board are as follows:
1. FPGA
Adopts QN48 package
Up to 38 user I/O
Embedded flash, data not easily lost if power down
Abundant LUT4 resources
Multiple modes and capacities of B-SRAM
2. FPGA Configuration Mode
JTAG
AUTO BOOT
3. Clock resource
50MHz Clock Crystal Oscillator
4. Key switch and slide switch
One reset button
One key switches
5. LED
One power indicator (green)
One DONE indicator (green)
2 LEDs (green)
6. Memory
1Mbit built-in Flash
32Mbit built-in PSRAM
7. MIPI/LVDS
5 pairs of MIPI/LVDS differential input; 4 pairs of MIPI/LVDS differential
output
8. GPIO
7 I/O expansion resources
9. LDO Power
Support 3.3 V, 2.5V, 1.8 V, and1.2 V.

2 Development Board Description
2.6 Development Board Specification
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2.6 Development Board Specification
Table 2-1 Development Board Specification
No.
Item
Functions
Technical Conditions
Note
1
FPGA
Core chip
–
–
2
Download
Support an USB
interface; Support
JTAG, AUTOBOOT
USB-JTAG module on
board
–
3
Power Supply
Provide DC 5V input;
3.3 V, 2.5V,1.8V, and
1.2V output via LDO
circuit
Input power: 5V
Provide power for
FPGA, download
circuit and other
circuits via 5V–3.3 V
circuit;
Provide power for
FPGA via the 5V to
2.5V circuit;
Provide power for
FPGA via the 5V to
1.8V circuit;
Provide power to
FPGA core via 5 V–
1.2 V circuit.
–
4
Key Switches
Available for testing
1
–
5
Reset button
Reset for FPGA
1
–
6
LED
Test indicator, DONE
indicator, Power
indicator
Two green test
indicators (share I/O
resources with
keys);
One DONE
indicator, green
One Power
indicator, green
–
7
Crystal Oscillator
Provide 50MHz clock
for FPGA
Package5032
–
8
Memory
Provides abundant
Flash and PSRAM for
designs
1Mbit built-in Flash
32Mbit built-in
PSRAM
–
9
GPIO
I/O, convenient for user
extension and test
7
–

2 Development Board Description
2.6 Development Board Specification
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No.
Item
Functions
Technical Conditions
Note
10
MIPI/LVDS
MIPI/LVDS, used for
testing
5 pairs of input, 4 pairs of
output
–
11
Protection
USB interface: ESD
protection;
Power interface:
Inverse current and
over current protection
USB interface ESD
protection: ±15kV
non-contact
discharge, ± 8kV
contact discharge;
Schottky diode is
connected between
positive and
negative anodes of
power outlet;
2A self-recovery
fuses are connected
at power inlet
–
12
Voltage
–
Input Voltage: 5V
–
13
Humidity
–
95%
–
14
Temperature
–
Operating range: –
20°~70°
–

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
Overview
For the resources of GW1NSR series of FPGA products, please refer
to DS861, GW1NSR series of FPGA Products Data Sheet.
I/O BANK Introduction
For the I/O BANK, package and pinout information of the GW1NSR
series of FPGA products, please refer to UG863, GW1NSR series of FPGA
Products Package and Pinout.
3.2 Download
3.2.1 Overview
The development board provides an USB download interface. The
data stream file can be downloaded to the internal SRAM, or internal flash
as needed.
Note!
When downloaded to SRAM, the data stream file will be lost if the device is power
down, and it will need to be downloaded again after power-on.
If downloaded to flash, the data stream file will not be lost if the device is powered
down.

3 Development Board Circuit
3.3 Power Supply
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3.2.2 USB Download Circuit
Figure 3-1 Connection Diagram for FPGA USB Downloading
TMS
TCK
TDI
TDO
USB-to-JTAG
Chip
USB_D+
USB_D- 5
4
6
7
U1
U17
GW1NSR-
LX2CQN48PC5I4_V2.1
3.2.3 Download Flow
1. FPGA and MCU download mode:
Plug the USB cable to the USB interface (J6) on the development
board.
Note!
Before downloading, switch the SW3, SW4, SW5, and SW6 on the development
board to the FPGA Download side.
2. MCU download mode:
Connect the J-Link ARM emulator to the ARM JTAG interface (J8).
Note!
Before debugging, switch the SW3, SW4, SW5, and SW6 on the development board
to the ARM Download side.
3.2.4 Pinout
Table 3-1 FPGA Download and Pinout
Signal Name
Pin No.
BANK
Description
I/O
TMS
4
3
JTAG Signal
3.3V (ADC/LVDS)/
1.8V (MIPI/PSRAM)
TCK
5
3
JTAG Signal
3.3V (ADC/LVDS)/
TDI
6
3
JTAG Signal
1.8V (MIPI/PSRAM)
TDO
7
3
JTAG Signal
3.3V (ADC/LVDS)/
MODE2
48
0
One Mode selection pin
1.8V (MIPI/PSRAM)
DONE
9
3
One DONE indicator
3.3V (ADC/LVDS)/
3.3 Power Supply
3.3.1 Overview
DC5V is input. The TI LDO power supply chip is used to step down
voltage from 5V to 3.3V, 2.5V, 1.8V, and 1.0V, which can meet the power
demand of the development board.

3 Development Board Circuit
3.3 Power Supply
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3.3.2 Power System Distribution
Figure 3-2 Power System Distribution
USB Interface
DC5V Input
TPS7A7001
LDO
1.2V
TPS7A7001
LDO
3.3V
TPS7A7001
LDO
2.5V
USB-JTAG
（FT2232）
FPGA
VCCO0&VCCO3
(ADC/LVDS/MIPI)
FPGA VCCX
（UX FPGA）
Key&LED&Reset
FPGA VCCO2
(LVDS)
FPGA VCCO1
FPGA VCC
FPGA VCCO2
(MIPI)
TPS7A7001
LDO
1.8V
FPGA
VCCO0&VCCO3
(PSRAM)
FPGA VCCX
（LX FPGA）

3 Development Board Circuit
3.4 Clock, Reset
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3.3.1 Pinout
Table 3-2 FPGA Power Pinout
Signal Name
Pin No.
BANK
Description
I/O
VCCO0
1
0
I/O Bank Power
1.8V/3.3V
VCCO1
25
1
I/O Bank Power
2.5V
VCCO2
13
2
I/O Bank Power
1.2V/2.5V
VCCO3
1
3
I/O Bank Power
1.8V/3.3V
VCCX
8, 36
-
Auxiliary voltage
1.8/3.3V
VCC
12, 37
-
Core voltage
1.2V
VSS
2, 26
-
GND
-
3.4 Clock, Reset
3.4.1 Overview
A 50MHz crystal oscillator is provided in the development board that
connects to the PLL input pin. This can be employed as the input clock for
the PLL in FPGA, and the output clock as needed via multiplication and
division of the PLL frequency.
3.4.2 Clock, Reset
Figure 3-3 Clock, Reset
35
14
KEY3
50MHz
ADM811
3.3V
FPGA_RST_N
FPGA_CLK
U1
U2
X2
GW1NSR-
LX2CQN48PC5I4_V2.1
3.4.3 Pinout
Table 3-3 FPGA Clock and Reset Pinout
Signal Name
Pin No.
BANK
Description
I/O
FPGA_CLK
35
1
50MHz crystal oscillator Input
2.5V
FPGA_RST_N
34
1
Reset signal, active low
2.5V